Circuit

Families
Ref: Weste-Harris

1
 Static CMOS

Static CMOS circuits with complementary nMOS

pulldown and pMOS pullup networks are used for majority of
logic gates in integrated circuits.

They have good noise margins, and are fast, low power,
insensitive to device variations and easy to design.
CMOS VLSI Design 4th Ed. 2
 Pseudo-nMOS Logic
 In the old days, nMOS processes had no pMOS
– Instead, use pull-up transistor that is always ON

10: Circuit Families CMOS VLSI Design 4th Ed. 6

 Dynamic Logic: Unfooted
 Dynamic gates uses a clocked pMOS pullup
 Two modes: clock low (precharge) and clock high
(evaluate)

 Precharge Evaluate Precharge

10: Circuit Families CMOS VLSI Design 4th Ed. 8

 Dynamic Logic: Footed
 What if pulldown network is ON during precharge?
 Use series evaluation transistor to prevent fight.

precharge transistor  
 Y Y
Y inputs inputs
A f f

foot
footed unfooted

10: Circuit Families CMOS VLSI Design 4th Ed. 9

 Dynamic Logic Gates: Logical Effort

Inverter NAND2 NOR2

 1
Y
 1  1
A 2
unfooted Y Y
A 1 B 2 A 1 B 1
gd = 1/3 gd = 2/3 gd = 1/3
pd = 2/3 pd = 3/3 pd = 3/3

 1
Y
 1  1
A 3
Y Y
footed A 2 B 3 A 2 B 2
gd = 2/3 gd = 3/3 gd = 2/3
2 pd = 3/3 3 pd = 4/3 2 pd = 5/3

10: Circuit Families CMOS VLSI Design 4th Ed. 10

 Dynamic Logic:
Monotonicity Requirement
precharge transistor

Y
A
foot

 While a dynamic gate is in evaluation, the inputs

must be monotonically rising.
 The input can start LOW and remain LOW.
 The input can start LOW and rise HIGH.
 The input can start HIGH and remain HIGH.
 The input cannot start HIGH and fall LOW.

10: Circuit Families CMOS VLSI Design 4th Ed. 11

 Dynamic Logic:
Monotonicity Requirement
precharge transistor

Y
A
foot

violates monotonicity
during evaluation
A

 Precharge Evaluate Precharge

Output should rise but does not

Figure shows waveforms for a footed dynamic inverter in which the

input violates monotonicity.

10: Circuit Families CMOS VLSI Design 4th Ed. 12

 Dynamic Logic:
Cascading Problem with Monotonicity Requirement

The output of a dynamic gate begins HIGH and monotonically

falls LOW during evaluation.

This monotonically falling output X is not a suitable input to a

second dynamic gate. So, dynamic gates sharing the same clock
cannot be directly connected.
10: Circuit Families CMOS VLSI Design 4th Ed. 13
 Domino Logic
 Follow dynamic stage with inverting static gate
– Dynamic / static pair is called domino gate
domino AND

W X Y Z
A
B C


dynamic static
NAND inverter

10: Circuit Families CMOS VLSI Design 4th Ed. 14

 Domino Logic
domino AND
 The monotonicity problem can
W X Y Z be solved by placing a static
A CMOS inverter between
B C
dynamic gates. This converts

the monotonically falling output
dynamic static
NAND inverter into a monotonically rising
 Precharge Evaluate Precharge
signal suitable for the next
gate.
W

 
 
A W X A X
H Y =
B H Z B Z
C C

10: Circuit Families CMOS VLSI Design 4th Ed. 15

 Domino Logic
domino AND
 A single clock can be used
W X Y Z to precharge and evaluate
A
B C
all the logic gates within the
 chain.
dynamic static
NAND inverter
 Precharge Evaluate Precharge
 Precharge occurs in
W
parallel, but evaluation
X occurs sequentially. Thus
evaluation is more critical
Y
than precharge.
Z

 
 
A W X A X
H Y =
B H Z B Z
C C

10: Circuit Families CMOS VLSI Design 4th Ed. 16

 Domino Optimization:
Compound Domino

 In domino logic, more complex inverting static CMOS gates such as

NANDs or NORs can be used in place of the inverter. This mixture of
dynamic and static logic is called compound domino.

 In the figure, an 8-input domino multiplexer is built from two 4-input

dynamic multiplexers and a NAND gate.
10: Circuit Families CMOS VLSI Design 4th Ed. 17
 Dual-Rail Domino
 Domino only performs noninverting functions:
– AND, OR but not NAND, NOR
 Dual-rail domino solves this problem
– Takes true and complementary inputs
– Produces true and complementary outputs

sig_h sig_l Meaning

Y_l  Y_h
0 0 Precharged
0 1 ‘0’ inputs
f f
1 0 ‘1’
1 1 invalid 

10: Circuit Families CMOS VLSI Design 4th Ed. 18

Dual-Rail Domino Example: AND/NAND

 Given A_h, A_l, B_h, B_l

 Compute Y_h = AB, Y_l = AB
 Pulldown networks are complements

Y_l  Y_h
= A*B A_h = A*B
A_l B_l B_h

10: Circuit Families CMOS VLSI Design 4th Ed. 19

 Cascode Voltage Switch Logic (CVSL)

 Cascode Voltage Switch Logic (CVSL) uses both true and

complementary input signals and computes both true and
complementary outputs using a pair of nMOS pulldown
networks.

10: Circuit Families CMOS VLSI Design 4th Ed. 21

 Cascode Voltage Switch Logic (CVSL)

 Figure shows a CVSL AND/NAND gate. The pulldown network f implements

the logic function as in a static CMOS gate, while f_bar uses inverted inputs
feeding transistors arranged in complement.

 For any given input pattern, one of the pulldown networks will be ON and the
other OFF. The pulldown network that is ON will pull that output low. This low
output turns ON the pMOS transistor to pull the opposite output high. When the
opposite output rises, the other pMOS transistor turns OFF so no static power
dissipation occurs.

10: Circuit Families CMOS VLSI Design 4th Ed. 22

 Multiple-Output Domino Logic (MODL)

 If it is necessary to compute multiple functions

where one is a subfunction of another, Multiple-
output domino logic (MODL) saves area by
combining all of the computations into a multiple-
output gate.

10: Circuit Families CMOS VLSI Design 4th Ed. 24

 Multiple-Output Domino Logic (MODL)

 An example of MODL application is addition, where the

carry-out ci of each bit of a 4-bit block must be computed.
 Each bit position i in the block can either propagate the
carry (pi) or generate a carry (gi). The carry-out logic is

 Here, each output is a function of the less significant outputs.

10: Circuit Families CMOS VLSI Design 4th Ed. 25

 Multiple-Output Domino Logic (MODL)

 The carry-out logic can be implemented in four compound AOI gates.

10: Circuit Families CMOS VLSI Design 4th Ed. 26

 Multiple-Output Domino Logic (MODL)

 The carry-out logic can also be implemented in MODL which results in

a more compact design. It is often called a Manchester carry chain.

10: Circuit Families CMOS VLSI Design 4th Ed. 27

 Dynamic Logic: Leakage Problem

precharge transistor

Y
A
foot

 In dynamic circuits, if a dynamic node is precharged

high and then left floating, the voltage will drift over
time due to leakage.
 The time constants tend to be in the millisecond to
nanosecond range, depending on process and
temperature.

10: Circuit Families CMOS VLSI Design 4th Ed. 30

 Dynamic Logic: Keepers
weak keeper
 1 k
X
H Y
A 2
2

 Leakage problem can be addressed by adding a keeper circuit.

A conventional keeper is a weak transistor that holds the output
at the correct level when it would otherwise float.
 When the dynamic node X is high, the output Y is low and the
keeper is ON to prevent X from floating.

10: Circuit Families CMOS VLSI Design 4th Ed. 31

 Dynamic Logic: Keepers
weak keeper
 1 k
X
H Y
A 2
2

 When X falls, the keeper initially opposes the transition so it

must be much weaker than the pulldown network. Eventually Y
rises, turning the keeper OFF and avoiding static power
dissipation.
 The keeper must be strong (i.e., wide) enough to compensate
for any leakage current drawn when the output is floating and
the pulldown stack is OFF.

10: Circuit Families CMOS VLSI Design 4th Ed. 32

 Pass Transistor Logic
 Use pass transistors like switches to do logic
 Inputs drive diffusion terminals as well as gates

 CMOS + Transmission Gates:

– 2-input multiplexer

S S

A A

S Y S Y

B B

S S

10: Circuit Families CMOS VLSI Design 4th Ed. 34