Section 2 - Port Control on SAMD20

Tasks

In this section you will learn:

• How to configure the I/O pins on the SAMD20 to function as a GPIO

• Registers used for PORT control
• How to turn LED On & Off
• How to handle button push

04/12/2013
 Table of Contents

1. GPIO and Pin Control .........................................................................1

2. Introduction to the SAMD20 PORT module ......................................2
2.1 Naming Convention...................................................................................... 3
2.2 Port Registers .............................................................................................. 3

3. Embedded C Review: Pointers ..........................................................4

4. Task 1: Configuration of hardware pin as GPIO in output mode....7
4.1 Which registers are used for output mode? ................................................. 7
4.2 Understanding the SAMD20 System level header files ............................... 8
4.2.1 SAMD20_XPLAINED_PRO.h ......................................................... 8
4.2.2 component_port.h ........................................................................... 8
4.2.3 samD20J18.h ................................................................................ 10
4.3 Turning ON the LED0 on the SAMD20 Eval Kit ......................................... 10
4.3.1 Accessing the Port Register.......................................................... 10

5. Task 2: Configuration of hardware as GPIO in input mode ..........12

5.1 Which registers to use for input mode? ..................................................... 12
5.2 Handling button push ................................................................................. 12

6. Task 3: Toggle LED0 when SW0 button is pushed ........................14

7. Conclusion ........................................................................................15

ii
1. GPIO and Pin Control
GPIO stands for General Purpose Input/Output which is basically a hardware pin on a chip. From a hardware
Engineer’s point of view, this pin is simply a pad on a silicon die or ball on a BGA package and serves no
special purpose. Each pad is driven by a specific piece of logic, called a cell.
The user can make the pin an input or output or bidirectional. This pin may be connected to a supply voltage
or Ground via a pull-up or pull-down resistor. As an example, a hardware pin can be made an output pin and
pulled high. This pin can then drive an LED. Figure 1 is a simple representation of this concept.

Figure 1. GPIO
The salient features of GPIO can be summarized as below:
• Drives a line (a one-bit signal) high or low.
• Reads a one-bit signal as high or low.
• The pins as such can be enabled or disabled.
• Can be specified as open drain/open source for e.g. wired-AND.
• Control registers for each cell are typically grouped into a 32 bit register where you can set features
such as pull-up/pull-down by setting/clearing a particular bit N in the register.
• The GPIO logic adds edge detection logic for rising or falling edges and level detection logic for high or
low levels when the pin is used as an input

Typically, the hardware pin is used to serve a special purpose other than GPIO such as SPI, USART, etc.
This is made possible by adding “pin multiplexing”, where the same pin can serve multiple functions. With the
help of specific hardware and set of registers, the pin control system is able to multiplex, bias, set load
capacitance, set drive strength, etc. for individual pins or groups of pins. This is represented in Figure 2. From

Page 1 of 15
 Figure 1 and 2, we can see that while GPIO is a rather simple implementation, by adding additional hardware
and control, we are able to establish a complete pin control system.
A group of pins are assigned to a controller of the peripheral such as I2C controller. Groups of pins can
overlap in functionality and it is the role of the controller to ensure that the pin is not already in use. The
peripheral controller along with the pinmux will then configure the pin(s) according to the function to be
performed. The pinmux, in addition to assigning a particular function to the pin, may also be used to perform
de bouncing, detect input signal and generate interrupt or wakeup event, drive the pin to be pull-up or pull-
down, etc.
The salient features of a pin control system can be summarized as below:
• Pin multiplexing: Allows for reusing the same pin for different purposes, such as one pin being a
UART TX pin, HSI data line or GPIO. Multiplexing can affect groups of pins or
individual pins.
• Pin configuration: Configuring electronic properties of pins such as pull-up, pull-down, driver strength
etc.

Figure 2. Overview of the Peripheral Functions Multiplexing

2. Introduction to the SAMD20 PORT module

The IO pins in the SAMD20 are organized as groups of 32 pins. These pins can be controlled as a group or
individually. They can function as a General purpose IO or perform as a specific peripheral such as TWI, SPI,
etc. This flexibility is brought about by a port multiplexer as shown in Figure 3.

Page 2 of 15
 Figure 3. Overview of the PORT

2.1 Naming Convention

Each hardware pin on the SAMD20 is uniquely identified using a simple naming scheme: Pxy. Here, x is the
pin Bank. There are two banks - Bank A and Bank B. Each bank has 32 pins which is identified using letter y.
Therefore SAMD20 has pins ranging from PA0 through PA31 and PB0 through PB31.

2.2 Port Registers

The register mapping for port control on the SAMD20 is as shown in Table 1. Using these registers, the Port
can be fully configured to function as either a GPIO or perform a peripheral function such as TWI, SPI, etc.
But how can one access these hardware registers for peripheral control? The C language provides this
functionality via hardware pointers through which a programmer can control hardware. In the next section we
will review the concept of hardware control through software using C Pointers.

Page 3 of 15
 Table 1: Port Control Register Summary

Offset Register Name Access

0x00 Data Direction DIR R/W

0x04 Data Direction Clear DIRCLR R/W

0x08 Data Direction Set DIRSET R/W

0x0C Data Direction Toggle DIRTGL R/W

0x10 Data Output Value OUT R/W

0x14 Data Output Value Clear OUTCLR R/W

0x18 Data Output Value Set OUTSET R/W

0x1C Data Output Value Toggle OUTTGL R/W

0x20 Data Input Value IN R

0x24 Control CTRL R/W

Read the “Register Description” section on page 300 of Section 22 in the datasheet
and learn the functions of each register.

3. Embedded C Review: Pointers

Pointers are a critical facility provided by the C language that makes it one of the most preferred languages in
embedded programming. Technically C is known as a middle level language since it provides many of the
higher language control structures but also allows simple and direct control of hardware. It does this through
the concept of the hardware pointer. Basic control of not just the core process but of all the peripheral blocks
in a microcontroller is presented in sets of registers that are realized as special memory locations mapped
directly into the address space of the processor being used.
In a standard C program a pointer to the variable loop_index is defined as per the following:

int loop_index;
int *loop_index_ptr;

At this point, however, loop_index_ptr is pointing to something random and not to loop_index. That problem is
solved by the following statement:

loop_index_ptr = &loop_index;

Now the value of loop_index can be modified by two ways:

loop_index = 5;
*loop_index_ptr = 5;

Page 4 of 15
Applied to hardware mapped registers the real power of this function becomes very clear.
The Port0 GPIO controller for the SAM D20 microcontroller is located at address 0x41004400. Starting from
this memory address there are registers that are specifically designed to control the Port0 functions. The
following extract from the SAM D20 datasheet documents the first three registers of the PORT0 peripheral:

For reasons partially related to the fact that the SAMD20 is a 32-bit micro-controller many of the registers in
this peripheral are 32 bits wide. Thus the first register in the set DIR spans the address range 0x41004400 -
0x41004403. The SAM D20 is a little endian processor, so the LSB is located at address 0x41004400.
To define a pointer to this specific memory address we can do the following

PORT0_DIR_ptr = (unsigned int*)(0x41004400);

Value can now be written or read from this memory location:

// read a value from the PORT0_DIR register

port0_value = *PORT0_DIR_ptr;

// write Bit 23, Bit 13 and Bit 4 as 1 in the PORT0_DIR

*PORT_DIR_ptr = (1 << 23) | (1 << 13) | (1 <<4);

The entire peripheral register set can now be so mapped in the header files using symbolic names for the
addresses to make the code more readable:

#define REG_PORT_DIR0 (0x41004400U) /* (PORT) Data Direction Register 0 */

#define REG_PORT_DIRCLR0 (0x41004404U) /* (PORT) Data Direction Clear Register 0 */
#define REG_PORT_DIRSET0 (0x41004408U) /* (PORT) Data Direction Set Register 0 */
#define REG_PORT_DIRTGL0 (0x4100440CU) /* (PORT) Data Direction Toggle Register 0 */

<and so on>

Additionally bit fields within the register can be addressed in the raw numeric form directly relating bit
positions as left shift offset operations. While the DIR0 register is an example of the trivial, the offset of bit5 is
usually defined
This is a standard method of defining peripheral register sets in micro controllers and is one of the ways the
SAMD20 peripheral registers are defined.

Page 5 of 15
 There is another more elegant way of defining register sets that encapsulates the definition of the registers as
a more complete object. A structure can be defined that clones the structure of the register set and then the
head of the structure can then be assigned the starting address of the peripheral set. Since microcontrollers
generally have more than one of a specific peripheral available, this allows very easy access to multiple
peripherals sets with only the change in the starting address for each instance that is created.
The SAM D20 register definition #typdef’s add one more layer of abstraction in order to allow the use of the
direct register value or defined bit fields within the register definition as shown by the following extract for the
SERCOM peripheral CTRLA register:

typedef union {
struct {
uint32_t SWRST:1; /*!< bit: 0 Software Reset */
uint32_t ENABLE:1; /*!< bit: 1 Enable */
uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */
uint32_t :2; /*!< bit: 5.. 6 Reserved */
uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */
uint32_t :8; /*!< bit: 8..15 Reserved */
uint32_t TXPO:1; /*!< bit: 16 Transmit Data Pinout */
uint32_t :3; /*!< bit: 17..19 Reserved */
uint32_t RXPO:2; /*!< bit: 20..21 Receive Data Pinout */
uint32_t :2; /*!< bit: 22..23 Reserved */
uint32_t FORM:4; /*!< bit: 24..27 Frame Format */
uint32_t CMODE:1; /*!< bit: 28 Communication Mode */
uint32_t CPOL:1; /*!< bit: 29 Clock Polarity */
uint32_t DORD:1; /*!< bit: 30 Data Order */
uint32_t :1; /*!< bit: 31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} SERCOM_USART_CTRLA_Type;

This compound register definition is now used as one of the members of the SERCOM USART mode
definition structure:

typedef struct { /* USART Mode */

__IO SERCOM_USART_CTRLA_Type CTRLA; /*Offset: 0x00 (R/W 32) USART Control Register A */
__IO SERCOM_USART_CTRLB_Type CTRLB; /*Offset: 0x04 (R/W 32) USART Control Register B */
__IO SERCOM_USART_DBGCTRL_Type DBGCTRL; /*Offset: 0x08 (R/W 8) USART Debug Register */
RoReg8 Reserved1[0x1];
__IO SERCOM_USART_BAUD_Type BAUD; /*Offset: 0x0A (R/W 16) USART Baud Rate Register */
__IO SERCOM_USART_INTENCLR_Type INTENCLR; /*Offset: 0x0C (R/W 8) USART Interrupt Enable Clear
Register */
__IO SERCOM_USART_INTENSET_Type INTENSET; /*Offset: 0x0D (R/W 8) USART Interrupt Enable Set
Register */
__IO SERCOM_USART_INTFLAG_Type INTFLAG; /* Offset: 0x0E (R/W 8) USART Interrupt Flag Status
and Clear Register */
RoReg8 Reserved2[0x1];
__IO SERCOM_USART_STATUS_Type STATUS; /*Offset: 0x10 (R/W 16) USART Status Register */
RoReg8 Reserved3[0x6];
__IO SERCOM_USART_DATA_Type DATA; /*Offset: 0x18 (R/W 16) USART Data Register */
} SercomUsart;

Note that memory gaps have been padded with arrays called Reserved1, Reserved2, and Reserved 3 to
properly align the offsets of the register definitions to the proper memory offset given that the CTRLA register
is at memory offset 0x00.

Page 6 of 15
 There are now two ways to access a specific bit field in the PINCFG register using this definition, but first we
need to define the structure pointer and assign it the proper address to the start of the structure:

SercomUsart *sercom0_ptr = (SercomUsart *) (0x42000800U);

Accessing specific bit fields in the CTRLA register can now happen in two ways: either using OR-masking at
the full register level or adjusting bit fields directly

sercom0_ptr->CTRLA.reg = SERCOM_USART_CTRLA_MODE(0x01) |
SERCOM_USART_CTRLA_RUNSTDBY |
SERCOM_USART_CTRLA_RXPO(0x02);

or

sercom0_ptr->CTRLA.bit.MODE = 0x01;
sercom0_ptr->CTRLA.bit.RUNSTDBY = 0x01;
sercom0_ptr->CTRLA.bit.RXPO = 0x02;

Both code fragments above achieve the same task.

There are advantages to both approaches. The bit masking approach uses less program space and executes
faster since the final value written to the CTRLA register in this case is calculated at compile time. Direct bit
field manipulation, however, can be extremely useful to bring specific attention to a critical operation of
peripheral such as the enable bit.

sercom0_ptr->CTRLA.bit.ENABLE = 1;

4. Task 1: Configuration of hardware pin as GPIO in output mode

Before you start the first task, you should be familiar with the following:

• The organization of the hardware pins in SAMD20 and their naming

convention.
• The SAMD20 registers available for port control.
• Studio 6 IDE.

4.1 Which registers are used for output mode?

Fill in Table 2 below with the registers that will enable you to set a hardware pin to be
a GPIO in output mode.

Page 7 of 15
 Table 2. Registers to set pin to GPIO output

Register Function

4.2 Understanding the SAMD20 System level header files

As already mentioned you have been provided with a template project to work on. This project is based on a
typical ASF Example project so as to make you more familiar with the organization of its source and header
files. This way, when you eventually start programming with ASF, you should have no problems managing
and debugging the code.
Let us now take a closer look at some header files that you need to understand in order to configure the Port
registers.

4.2.1 SAMD20_XPLAINED_PRO.h
The samd20_xplained_pro.h header file contains all the board level definitions.
The various hardware pin headers, push buttons, LEDs, etc are all defined in the samd20_xplained_pro.h
header file. Other than hardware pin definitions, the on-board 32kHz crystal is also defined.

Look for pin definitions of LED0 and SW0 in the samd20_xplained_pro.h header file
and note them down.

4.2.2 component_port.h
The component_port.h header file has important definitions pertaining to the PORT module. It defines a
structure called PortGroup that lists all registers related to PORT control as shown below:

typedef struct {
__IO PORT_DIR_Type DIR; /**< Offset: 0x00 (R/W 32) Data Direction
Register */
__IO PORT_DIRCLR_Type DIRCLR; /**< Offset: 0x04 (R/W 32) Data Direction
Clear Register */
__IO PORT_DIRSET_Type DIRSET; /**< Offset: 0x08 (R/W 32) Data Direction
Set Register */
__IO PORT_DIRTGL_Type DIRTGL; /**< Offset: 0x0C (R/W 32) Data Direction
Toggle Register */
__IO PORT_OUT_Type OUT; /**< Offset: 0x10 (R/W 32) Data Output
Value Register */
__IO PORT_OUTCLR_Type OUTCLR; /**< Offset: 0x14 (R/W 32) Data Output
Value Clear Register */
__IO PORT_OUTSET_Type OUTSET; /**< Offset: 0x18 (R/W 32) Data Output
Value Set Register */
__IO PORT_OUTTGL_Type OUTTGL; /**< Offset: 0x1C (R/W 32) Data Output
Value Toggle Register */
__I PORT_IN_Type IN; /**< Offset: 0x20 (R/ 32) Data Input
Value Register */

Page 8 of 15
 __IO PORT_CTRL_Type CTRL; /**< Offset: 0x24 (R/W 32) Control
Register */
__O PORT_WRCONFIG_Type WRCONFIG; /**< Offset: 0x28 ( /W 32) Write
Configuration Register */
RoReg8 Reserved1[0x4];
__IO PORT_PMUX_Type PMUX[16]; /**< Offset: 0x30 (R/W 8) Peripheral
Multiplexing Register */
__IO PORT_PINCFG_Type PINCFG[32]; /**< Offset: 0x40 (R/W 8) Pin
Configuration Register */
RoReg8 Reserved2[0x20];
} PortGroup;

Each register is assigned a “type” such as PORT_DIR_Type:

typedef union {
struct {
uint32_t DIR:32; /*!< bit: 0..31 Port Data Direction */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PORT_DIR_Type;

You can access the DIR register using “uint32_t reg” in the following way:

port->DIRSET.reg = <value to be assigned>;

Here, port is the pointer variable to the PortGroup structure. The reset value of each register is also defined
in the header file. For example:

#define PORT_DIRCLR_OFFSET 0x04 /**< (PORT_DIRCLR offset) Data Direction

Clear Register */
#define PORT_DIRCLR_RESETVALUE 0x00000000 /**< (PORT_DIRCLR reset_value) Data
Direction Clear Register */
Finally, the bit-wise register description is provided in the header file. For example, here is the description of
the Data Direction Register from the datasheet:

Page 9 of 15
 Figure 4. Description of the DIR Register

Note down how the Data Direction Register is defined in the component_port.h header
file.

4.2.3 samD20J18.h
This header file has some important definitions pertaining to the SAMD20J18 variant of the SAMD20 family of
microcontrollers such as:
i. It enumerates the IRQ numbers of all the peripherals.
ii. All the interrupt handler function prototypes are declared.
iii. The base address memory mapping of all the peripherals are defined.

4.3 Turning ON the LED0 on the SAMD20 Eval Kit

Now that we have become familiar with some important Studio 6 header files and have understood how to
access the Port Control Registers let us proceed with the given assignment and set the LED0 pin as an
output pin and turn it ON.

4.3.1 Accessing the Port Register

Clearly the PortGroup structure, shown below, defines all the registers available for PORT control.

Page 10 of 15
typedef struct {
__IO PORT_DIR_Type DIR; /**< Offset: 0x00 (R/W 32) Data Direction Register */
__IO PORT_DIRCLR_Type DIRCLR; /**< Offset: 0x04 (R/W 32) Data Direction Clear
Register */
__IO PORT_DIRSET_Type DIRSET; /**< Offset: 0x08 (R/W 32) Data Direction Set
Register */
__IO PORT_DIRTGL_Type DIRTGL; /**< Offset: 0x0C (R/W 32) Data Direction Toggle
Register */
__IO PORT_OUT_Type OUT; /**< Offset: 0x10 (R/W 32) Data Output Value Register
*/
__IO PORT_OUTCLR_Type OUTCLR; /**< Offset: 0x14 (R/W 32) Data Output Value Clear
Register */
__IO PORT_OUTSET_Type OUTSET; /**< Offset: 0x18 (R/W 32) Data Output Value Set
Register */
__IO PORT_OUTTGL_Type OUTTGL; /**< Offset: 0x1C (R/W 32) Data Output Value Toggle
Register */
__I PORT_IN_Type IN; /**< Offset: 0x20 (R/ 32) Data Input Value Register
*/
__IO PORT_CTRL_Type CTRL; /**< Offset: 0x24 (R/W 32) Control Register */
__O PORT_WRCONFIG_Type WRCONFIG; /**< Offset: 0x28 ( /W 32) Write Configuration
Register */
RoReg8 Reserved1[0x4];
__IO PORT_PMUX_Type PMUX[16]; /**< Offset: 0x30 (R/W 8) Peripheral Multiplexing
Register */
__IO PORT_PINCFG_Type PINCFG[32]; /**< Offset: 0x40 (R/W 8) Pin Configuration Register
*/
RoReg8 Reserved2[0x20];
} PortGroup;

Recall that there are 2 port groups or banks in the SAMD20. The Port structure allows us to easily access the
register of either port by creating an array of the PortGroup structure:
typedef struct {
PortGroup Group[2]; /**< Offset: 0x00 PortGroup groups [GROUPS] */
} Port;

Since the LED0 pin is part of Bank or Group A, we could easily access its register this way:

Port *ports = PORT;

PortGroup *p = &(ports->Group[0]);
Here PORT is the base address definition:
#define PORT (0x41004400U) /**< (PORT) APB Base Address */

Using the minimal Studio 6 application template provided, set up the hardware pin
corresponding to LED0 as a GPIO output with logic HIGH. Refer to the SAMD20
Xplained Pro User Guide for a list of connectors and headers and their connections.

Page 11 of 15
5. Task 2: Configuration of hardware as GPIO in input mode
Now that you are able to set a hardware pin as a GPIO in output mode, you will now set another pin as GPIO
in input mode.

5.1 Which registers to use for input mode?

Fill in Table 3 below with the proper registers that will enable you to set a hardware pin
to be a GPIO in input mode.

Table 3. Registers used to set pin to GPIO input

Register Function

We set a pin to be GPIO input using these steps:

1. Enable input for the pin
2. Set the direction of the pin to input
3. Set the input pull direction to an internal pull-up

Notice that the pull direction needs to be set to internal pull-up for input, whereas this step is not needed for
output. Most systems initially boot with input—and output—directions pulled down to prevent any sudden and
inadvertent current to the chip.

Again, using the minimal Studio 6 application template provided, configure the PORT
registers with the right value to turn the pin connected to push button SW0 to handle
button pushes as an input pin.

5.2 Handling button push

Now that the pin has been configured as an input, let us see how to handle button pushes. Think about what
happens when the button is pressed.
Pushing the button for SW0 will drive the GPIO pin to input low. Releasing it will raise the pin back high.
Figure 5 shows the button pressed, released, and then pressed again over a 5 second period. The pin is held
low for the duration of the button press. Therefore we can conclude that if the SW0 GPIO pin goes low, the
button is pushed.

Page 12 of 15
 Figure 5. Oscilloscope capture of steady button press

Recall that the bouncing of the switch results in an unsteady transition for the state of the GPIO pin. This may
be problematic if the switch is set up as a counter or as a toggle switch. The output response macroscopically
seen in Figure 5 was captured in a window of a few long seconds. Focusing in on a shorter interval with a
rapid press of the switch, we can see volatility in the reading, as shown in Figure 6. The bottom half of the
figure—a 10 ms span—is a zoomed view of the darkened interval of the top half, which shows a falling edge.
Notice this is not a smooth transition.

Figure 6. Oscilloscope capture of quick button press

Page 13 of 15
 There are a few simple ways to fix this with software. One method is to sample the output signal at regular
intervals and to ignore any sudden changes. Another way that works well is to simply set an ample delay
period after a change in input level is detected. Since the delay function has not yet been covered, inserting a
delay loop will do for now.

Which register handles detection of change in the logic level of an input pin?

Write a function that checks for when the SW0 pin goes high.

6. Task 3: Toggle LED0 when SW0 button is pushed

Now that the hardware pin of LED0 is configured to output and the pin of SW0 is configured to input, we can
set our board to toggle the LED with each push of the button.
The problem with switch bouncing—along with the length of the button press—applies to this task. Pressing
the SW0 button once may toggle LED0 many times. To overcome this, we will insert a waiting period after
each successful toggle into our code.
Here is an example in which we define a function WAIT to only increment the counter until a user-defined
number is reached:

void wait(int t)
{
int count = 0;
do
count++;
while(count < (t*1000));
}

Now combine the output and input concepts to turn on LED0 when SW0 is pressed.

Page 14 of 15
7. Conclusion
In this section we learnt about the Ports peripheral in SAMD20. We are now familiar with the registers
available for port control and how these registers can be accessed through software using C pointers.
Specifically we can now do the following:
1. Turn an LED on. Therefore we know how to make a pin an output.
2. Detect a button push. This means we know how to configure a hardware pin as an input.

Page 15 of 15
Atmel Corporation Atmel Asia Limited Atmel Munich GmbH Atmel Japan G.K.
1600 Technology Drive Unit 01-5 & 16, 19F Business Campus 16F Shin-Osaki Kangyo Bldg.
San Jose, CA 95110 BEA Tower, Millennium City 5 Parkring 4 1-6-4 Osaki, Shinagawa-ku
USA 418 Kwun Tong Road D-85748 Garching b. Munich Tokyo 141-0032
Tel: (+1)(408) 441-0311 Kwun Tong, Kowloon GERMANY JAPAN
Fax: (+1)(408) 487-2600 HONG KONG Tel: (+49) 89-31970-0 Tel: (+81)(3) 6417-0300
www.atmel.com Tel: (+852) 2245-6100 Fax: (+49) 89-3194621 Fax: (+81)(3) 6417-0370
Fax: (+852) 2722-1369

© 2013 Atmel Corporation. All rights reserved. / Rev.: 04/12/2013

Atmel®, Atmel logo and combinations thereof, Enabling Unlimited Possibilities®, and others are registered trademarks or trademarks of Atmel Corporation or its
subsidiaries. Other terms and product names may be trademarks of others.

Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this
document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN THE ATMEL TERMS AND CONDITIONS OF SALES LOCATED ON THE ATMEL WEBSITE, ATMEL ASSUMES
NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS AND PROFITS, BUSINESS INTERRUPTION, OR LOSS OF
INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no
representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and products descriptions at any time
without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in,
automotive applications. Atmel products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life.