ispLSI 1016E ®

In-System Programmable High Density PLD

Features Functional Block Diagram

• HIGH-DENSITY PROGRAMMABLE LOGIC
— 2000 PLD Gates
— 32 I/O Pins, Four Dedicated Inputs
— 96 Registers
— High-Speed Global Interconnect A0 B7
— Wide Input Gating for Fast Counters, State D Q
A1 B6

Output Routing Pool

Output Routing Pool

Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic A2 D Q B5
Logic
• HIGH-PERFORMANCE E2CMOS® TECHNOLOGY A3 Array D Q
GLB B4
— fmax = 125 MHz Maximum Operating Frequency A4 B3
— tpd = 7.5 ns Propagation Delay
D Q

A5 B2
— TTL Compatible Inputs and Outputs
— Electrically Erasable and Reprogrammable A6 B1
— Non-Volatile A7 Global Routing Pool (GRP) B0
— 100% Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power CLK
• IN-SYSTEM PROGRAMMABLE
— In-System Programmable (ISP™) 5V Only
— Increased Manufacturing Yields, Reduced Time-to- 0139C1-isp

Market and Improved Product Quality Description

— Reprogram Soldered Device for Faster Prototyping
• OFFERS THE EASE OF USE AND FAST SYSTEM The ispLSI 1016E is a High Density Programmable Logic
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY Device containing 96 Registers, 32 Universal I/O pins,
OF FIELD PROGRAMMABLE GATE ARRAYS four Dedicated Input pins, three Dedicated Clock Input
— Complete Programmable Device Can Combine Glue pins, one Global OE input pin and a Global Routing Pool
Logic and Structured Designs
— Enhanced Pin Locking Capability
(GRP). The GRP provides complete interconnectivity
— Three Dedicated Clock Input Pins between all of these elements. The ispLSI 1016E features
— Synchronous and Asynchronous Clocks 5V in-system programming and in-system diagnostic
— Programmable Output Slew Rate Control to capabilities. The ispLSI 1016E offers non-volatile
Minimize Switching Noise reprogrammability of the logic, as well as the interconnect
— Flexible Pin Placement to provide truly reconfigurable systems. A functional
— Optimized Global Routing Pool Provides Global superset of the ispLSI 1016 architecture, the ispLSI
Interconnectivity
1016E device adds a new global output enable pin.
• ispDesignEXPERT™ – LOGIC COMPILER AND COM-
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL The basic unit of logic on the ispLSI 1016E device is the
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING Generic Logic Block (GLB). The GLBs are labeled A0,
— Superior Quality of Results A1...B7 (see Figure 1). There are a total of 16 GLBs in the
— Tightly Integrated with Leading CAE Vendor Tools ispLSI 1016E device. Each GLB has 18 inputs, a
— Productivity Enhancing Timing Analyzer, Explore programmable AND/OR/Exclusive OR array, and four
Tools, Timing Simulator and ispANALYZER™ outputs which can be configured to be either combinatorial
— PC and UNIX Platforms
or registered. Inputs to the GLB come from the GRP and
dedicated inputs. All of the GLB outputs are brought back
into the GRP so that they can be connected to the inputs
of any other GLB on the device.

Copyright © 1998 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. October 1998
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

1016e_06 1
 Specifications ispLSI 1016E

Functional Block Diagram

Figure 1. ispLSI 1016E Functional Block Diagram

Generic
Logic Blocks
(GLBs)
GOE 0/IN 3
MODE/IN 2

I/O 31
B7
I/O 30
I/O 0 I/O 29
I/O 1 A0
B6 I/O 28
I/O 2
I/O 3 A1

Output Routing Pool (ORP)

I/O 27
B5
I/O 26
Output Routing Pool (ORP)

I/O 4 I/O 25
A2
I/O 5

lnput Bus
B4 I/O 24
I/O 6 Global
Routing
Input Bus

I/O 7 A3
Pool B3 I/O 23
(GRP) I/O 22
I/O 8 A4 I/O 21
I/O 9 B2 I/O 20
I/O 10
I/O 11 A5
B1 I/O 19
I/O 18
I/O 12 A6 I/O 17
I/O 13 B0
I/O 16
I/O 14
I/O 15 A7

SDI/IN 0 CLK 0
SDO/IN 1 CLK 1
Clock
CLK 2
Distribution
IOCLK 0
Network
IOCLK 1
Megablock

ispEN

0139B(1a)-isp
SCLK/Y2
Y1/RESET*
Y0

*Note: Y1 and RESET are multiplexed on the same pin

The device also has 32 I/O cells, each of which is directly The GRP has, as its inputs, the outputs from all of the
connected to an I/O pin. Each I/O cell can be individually GLBs and all of the inputs from the bi-directional I/O cells.
programmed to be a combinatorial input, registered in- All of these signals are made available to the inputs of the
put, latched input, output or bi-directional GLBs. Delays through the GRP have been equalized to
I/O pin with 3-state control. The signal levels are TTL minimize timing skew.
compatible voltages and the output drivers can source Clocks in the ispLSI 1016E device are selected using the
4 mA or sink 8 mA. Each output can be programmed Clock Distribution Network. Three dedicated clock pins
independently for fast or slow output slew rate to mini- (Y0, Y1 and Y2) are brought into the distribution network,
mize overall output switching noise. and five clock outputs (CLK 0, CLK 1, CLK 2, IOCLK 0
and IOCLK 1) are provided to route clocks to the GLBs
Eight GLBs, 16 I/O cells, two dedicated inputs and one
and I/O cells. The Clock Distribution Network can also be
ORP are connected together to make a Megablock (see
driven from a special clock GLB (B0 on the ispLSI 1016E
Figure 1). The outputs of the eight GLBs are connected
device). The logic of this GLB allows the user to create an
to a set of 16 universal I/O cells by the ORP. Each ispLSI
internal clock from a combination of internal signals
1016E device contains two Megablocks.
within the device.

2
 Specifications ispLSI 1016E

Absolute Maximum Ratings 1

Supply Voltage VCC ................................ -0.5 to +7.0V

Input Voltage Applied ........................ -2.5 to VCC +1.0V

Off-State Output Voltage Applied ..... -2.5 to VCC +1.0V

Storage Temperature ................................ -65 to 150°C

Case Temp. with Power Applied .............. -55 to 125°C

Max. Junction Temp. (TJ) with Power Applied ... 150°C

1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).

DC Recommended Operating Conditions

SYMBOL PARAMETER MIN. MAX. UNITS

Commercial TA = 0°C to + 70°C 4.75 5.25 V
VCC Supply Voltage
Industrial TA = -40°C to + 85°C 4.5 5.5 V
VIL Input Low Voltage 0 0.8 V
VIH Input High Voltage 2.0 Vcc+1 V
Table 2-0005/1016E

Capacitance (TA=25oC, f=1.0 MHz)

SYMBOL PARAMETER TYPICAL UNITS TEST CONDITIONS

C1 Dedicated Input, I/O, Y1, Y2, Y3, Clock Capacitance 8 pf VCC = 5.0V, VPIN = 2.0V
(Commercial/Industrial)
C2 Y0 Clock Capacitance 12 pf VCC = 5.0V, VPIN = 2.0V
Table 2-0006/1016E

Data Retention Specifications

PARAMETER MINIMUM MAXIMUM UNITS

Data Retention 20 – Years
Erase/Reprogram Cycles 10000 – Cycles
Table 2-0008/1016E

3
 Specifications ispLSI 1016E

Switching Test Conditions

Input Pulse Levels GND to 3.0V Figure 2. Test Load

Input Rise and Fall Time -125 ≤ 2 ns
+ 5V
10% to 90% -100, -80 ≤ 3 ns
Input Timing Reference Levels 1.5V
R1
Output Timing Reference Levels 1.5V
Output Load See Figure 2 Device Test
3-state levels are measured 0.5V from Table 2-0003/1016E Output Point
steady-state active level.
R2 CL*
Output Load Conditions (see Figure 2)

TEST CONDITION R1 R2 CL
A 470Ω 390Ω 35pF *CL includes Test Fixture and Probe Capacitance.
0213a

Active High ∞ 390Ω 35pF

B
Active Low 470Ω 390Ω 35pF
Active High to Z ∞ 390Ω 5pF
at VOH -0.5V
C
Active Low to Z
at VOL +0.5V 470Ω 390Ω 5pF
Table 2-0004/1016E

DC Electrical Characteristics
Over Recommended Operating Conditions
3
SYMBOL PARAMETER CONDITION MIN. TYP. MAX. UNITS
VOL Output Low Voltage IOL= 8 mA – – 0.4 V
VOH Output High Voltage IOH = -4 mA 2.4 – – V
IIL Input or I/O Low Leakage Current 0V ≤ VIN ≤ VIL (Max.) – – -10 µA
IIH Input or I/O High Leakage Current 3.5V ≤ VIN ≤ VCC – – 10 µA
IIL-isp ispEN Input Low Leakage Current 0V ≤ VIN ≤ VIL – – -150 µA
IIL-PU I/O Active Pull-Up Current 0V ≤ VIN ≤ VIL – – -150 µA
IOS1 Output Short Circuit Current VCC = 5V, VOUT = 0.5V – – -200 mA
VIL = 0.5V, VIH = 3.0V Commercial – 90 – mA
ICC2, 4 Operating Power Supply Current
fCLOCK = 1 MHz Industrial – 90 – mA
Table 2-0007/1016E
1. One output at a time for a maximum duration of one second. VOUT = 0.5V was selected to avoid test problems
by tester ground degradation. Characterized but not 100% tested.
2. Measured using four 16-bit counters.
3. Typical values are at VCC = 5V and TA= 25°C.
4. Maximum I CC varies widely with specific device configuration and operating frequency. Refer to the Power Consumption
section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to estimate
maximum ICC .

4
 Specifications ispLSI 1016E

External Timing Parameters

Over Recommended Operating Conditions
4 -125 -100 -80
TEST
PARAMETER #2 DESCRIPTION 1 UNITS
COND. MIN. MAX. MIN. MAX. MIN. MAX.
tpd1 A 1 Data Prop. Delay, 4PT Bypass, ORP Bypass – 7.5 – 10.0 – 15.0 ns
tpd2 A 2 Data Prop. Delay, Worst Case Path – 10.0 – 13.0 – 18.5 ns
3
fmax A 3 Clk. Frequency with Int. Feedback 125 – 100 – 84.0 – MHz
1
fmax (Ext.) – 4 Clk. Frequency with Ext. Feedback( )
tsu2 + tco1 100 – 77.0 – 57.0 – MHz
1
fmax (Tog.) – 5 Clk. Frequency, Max. Toggle( twh + tw1 ) 167 – 125 – 100 – MHz
tsu1 – 6 GLB Reg. Setup Time before Clk., 4 PT Bypass 5.0 – 7.0 – 8.5 – ns
tco1 A 7 GLB Reg. Clk. to Output Delay, ORP Bypass – 4.5 – 5.0 – 8.0 ns
th1 – 8 GLB Reg. Hold Time after Clk., 4 PT Bypass 0.0 – 0.0 – 0.0 – ns
tsu2 – 9 GLB Reg. Setup Time before Clk. 5.5 – 8.0 – 9.5 – ns
tco2 – 10 GLB Reg. Clk. to Output Delay – 5.5 – 6.0 – 9.5 ns
th2 – 11 GLB Reg. Hold Time after Clk. 0.0 – 0.0 – 0.0 – ns
tr1 A 12 Ext. Reset Pin to Output Delay – 10.0 – 13.5 – 17.0 ns
trw1 – 13 Ext. Reset Pulse Duration 5.0 – 6.5 – 10.0 – ns
tptoeen B 14 Input to Output Enable – 12.0 – 15.0 – 20.0 ns
tptoedis C 15 Input to Output Disable – 12.0 – 15.0 – 20.0 ns
tgoeen B 16 Global OE Output Enable – 7.0 – 9.0 – 10.5 ns
tgoedis C 17 Global OE Output Disable – 7.0 – 9.0 – 10.5 ns
twh – 18 Ext. Sync. Clk. Pulse Duration, High 3.0 – 4.0 – 5.0 – ns
twl – 19 Ext. Sync. Clk. Pulse Duration, Low 3.0 – 4.0 – 5.0 – ns
tsu3 – 20 I/O Reg. Setup Time before Ext. Sync. Clk. (Y2, Y3) 3.0 – 3.5 – 4.5 – ns
th3 – 21 I/O Reg. Hold Time after Ext. Sync. Clk. (Y2, Y3) 0.0 – 0.0 – 0.0 – ns
Table 2-0030-16/125,100, 80
1. Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock.
2. Refer to Timing Model in this data sheet for further details.
3. Standard 16-bit counter using GRP feedback.
4. Reference Switching Test Conditions Section.

5
 Specifications ispLSI 1016E

Internal Timing Parameters1

2 -125 -100 -80

PARAMETER # DESCRIPTION UNITS
MIN. MAX. MIN. MAX. MIN. MAX.
Inputs
tiobp 22 I/O Register Bypass – 0.3 – 0.4 – 0.6 ns
tiolat 23 I/O Latch Delay – 1.8 – 2.4 – 3.6 ns
tiosu 24 I/O Register Setup Time before Clock 3.0 – 3.5 – 4.5 – ns
tioh 25 I/O Register Hold Time after Clock -0.3 – -0.4 – -0.6 – ns
tioco 26 I/O Register Clock to Out Delay – 4.0 – 5.0 – 7.5 ns
tior 27 I/O Register Reset to Out Delay – 4.0 – 5.0 – 7.5 ns
tdin 28 Dedicated Input Delay – 2.2 – 2.6 – 3.9 ns
GRP
tgrp1 29 GRP Delay, 1 GLB Load – 1.8 – 1.9 – 2.9 ns
tgrp4 30 GRP Delay, 4 GLB Loads – 1.9 – 2.2 – 3.3 ns
tgrp8 31 GRP Delay, 8 GLB Loads – 2.1 – 2.5 – 3.8 ns
tgrp16 32 GRP Delay, 16 GLB Loads – 2.4 – 3.1 – 4.7 ns
GLB
t4ptbpc 34 4 Product Term Bypass Path Delay (Combinatorial) – 3.9 – 5.7 – 8.1 ns
t4ptbpr 35 4 Product Term Bypass Path Delay (Registered) – 3.9 – 5.6 – 7.3 ns
t1ptxor 36 1 Product Term/XOR Path Delay – 4.4 – 6.1 – 7.1 ns
t20ptxor 37 20 Product Term/XOR Path Delay – 4.4 – 6.1 – 8.2 ns
txoradj 38 XOR Adjacent Path Delay 3 – 4.4 – 6.6 – 8.3 ns
tgbp 39 GLB Register Bypass Delay – 1.0 – 1.6 – 1.9 ns
tgsu 40 GLB Register Setup Time before Clock 0.2 – 0.2 – -0.6 – ns
tgh 41 GLB Register Hold Time after Clock 1.5 – 2.5 – 4.3 – ns
tgco 42 GLB Register Clock to Output Delay – 1.8 – 1.9 – 2.9 ns
tgro 43 GLB Register Reset to Output Delay – 4.4 – 6.3 – 7.0 ns
tptre 44 GLB Product Term Reset to Register Delay – 3.5 – 5.1 – 7.2 ns
tptoe 45 GLB Product Term Output Enable to I/O Cell Delay – 5.5 – 7.1 – 9.7 ns
tptck 46 GLB Product Term Clock Delay 3.2 3.5 4.8 5.3 6.8 7.5 ns
ORP
torp 47 ORP Delay – 1.0 – 1.0 – 1.5 ns
torpbp 48 ORP Bypass Delay – 0.0 – 0.0 – 0.0 ns
Table 2-0036-16/125,100, 80
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR Adjacent path can only be used by Lattice hard macros.

6
 Specifications ispLSI 1016E

Internal Timing Parameters1

-125 -100 -80

PARAMETER #2 DESCRIPTION UNITS
MIN. MAX. MIN. MAX. MIN. MAX.
Outputs
tob 49 Output Buffer Delay – 1.4 – 1.7 – 3.0 ns
tsl 50 Output Slew Limited Delay Adder – 10.0 – 10.0 – 10.0 ns
toen 51 I/O Cell OE to Output Enabled – 4.3 – 5.3 – 6.4 ns
todis 52 I/O Cell OE to Output Disabled – 4.3 – 5.3 – 6.4 ns
tgoe 53 Global Output Enable – 2.7 – 3.7 – 4.1 ns
Clocks
tgy0 54 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock) 1.3 1.3 1.4 1.4 2.1 2.1 ns
tgy1/2 55 Clock Delay, Y1 or Y2 to Global GLB Clock Line 2.3 2.7 2.4 2.9 3.6 4.4 ns
tgcp 56 Clock Delay, Clock GLB to Global GLB Clock Line 0.8 1.8 0.8 1.8 1.2 2.7 ns
tioy1/2 57 Clock Delay, Y1 or Y2 to I/O Cell Global Clock Line 0.0 0.3 0.0 0.4 0.0 0.6 ns
tiocp 58 Clock Delay, Clock GLB to I/O Cell Global Clock Line 0.8 1.8 0.8 1.8 1.2 2.7 ns
Global Reset
tgr 59 Global Reset to GLB and I/O Registers – 3.2 – 4.5 – 5.5 ns
Table 2-0037-16/125,100,80
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.

7
 Specifications ispLSI 1016E

ispLSI 1016E Timing Model

I/O Cell GRP GLB ORP I/O Cell

Feedback

Ded. In Comb 4 PT Bypass #34

#28
I/O Reg Bypass Reg 4 PT Bypass GLB Reg Bypass ORP Bypass
I/O Pin #49, 50 I/O Pin
#22 #30 #35 #39 #48
(Input) (Output)
Input GRP 20 PT GLB Reg ORP
Loading #51, 52
D Register Q Delay XOR Delays Delay Delay
RST D Q
#59 #23 - 27 #29, 31, 32 #36-38 #47
RST
#59 #40-43
Reset

Clock Control RE
Distribution
PTs OE
Y1,2 #55-58 #44-46 CK

#54
Y0 0491-16

#53
GOE 0

Derivations of tsu, th and tco from the Product Term Clock 1

tsu = Logic + Reg su - Clock (min)
= (tiobp + tgrp4 + t20ptxor) + (tgsu) - (tiobp + tgrp4 + tptck(min))
= (#22 + #30 + #37) + (#40) - (#22 + #30 + #46)
1.4 ns = (0.3 + 1.9 + 4.4) + (0.2) - (0.3 + 1.9 + 3.2)
th = Clock (max) + Reg h - Logic
= (tiobp + tgrp4 + tptck(max)) + (tgh) - (tiobp + tgrp4 + t20ptxor)
= (#22 + #30 + #46) + (#41) - (#22 + #30 + #37)
0.6 ns = (0.3 + 1.9 + 3.5) + (1.5) - (0.3 + 1.9 + 4.4)
tco = Clock (max) + Reg co + Output
= (tiobp + tgrp4 + tptck(max)) + (tgco) + (torp + tob)
= (#22 + #30 + #46) + (#42) + (#47 + #49)
9.9 ns = (0.3 + 1.9 + 3.5) + (1.8) + (1.0 + 1.4)

Derivations of tsu, th and tco from the Clock GLB 1

tsu = Logic + Reg su - Clock (min)
= (tiobp + tgrp4 + t20ptxor) + (tgsu) - (tgy0(min) + tgco + tgcp(min))
= (#22 + #30 + #37) + (#40) - (#54 + #42 + #56)
2.9 ns = (0.3 + 1.9 + 4.4) + (0.2) - (1.3 + 1.8 + 0.8)
th = Clock (max) + Reg h - Logic
= (tgy0(max) + tgco + tgcp(max)) + (tgh) - (tiobp + tgrp4 + t20ptxor)
= (#54 + #42 + #56) + (#41) - (#22 + #30 + #37)
-0.2 ns = (1.3 + 1.8 + 1.8) + (1.5) - (0.3 + 1.9 + 4.4)
tco = Clock (max) + Reg co + Output
= (tgy0(max) + tgco + tgcp(max)) + (tgco) + (torp + tob)
= (#54 + #42 + #56) + (#42) + (#47 + #49)
9.1 ns = (1.3 + 1.8 + 1.8) + (1.8) + (1.0 + 1.4)
Table 2-0042-16

1. Calculations are based upon timing specifications for the ispLSI 1016E-125

8
 Specifications ispLSI 1016E

Maximum GRP Delay vs GLB Loads

ispLSI 1016E-80
3

ispLSI 1016E-100

GRP Delay (ns)

ispLSI 1016E-125

1 4 8 12 16
GLB Load
16E GRP/GLB.eps

Power Consumption

Power consumption in the ispLSI 1016E device depends Figure 3 shows the relationship between power and
on two primary factors: the speed at which the device is operating speed.
operating and the number of Product Terms used.
Figure 3. Typical Device Power Consumption vs fmax

130
ispLSI 1016E
120

110
ICC (mA)

100

90

80

0 20 40 60 80 100 120 140

fmax (MHz)
Notes: Configuration of four 16-bit counters
Typical current at 5V, 25°C

ICC can be estimated for the ispLSI 1016E using the following equation:

ICC(mA) = 23 + (# of PTs * 0.52) + (# of nets * max freq * 0.004)

Where:
# of PTs = Number of product terms used in design
# of nets = Number of signals used in device
Max freq = Highest clock frequency to the device (in MHz)

The ICC estimate is based on typical conditions (VCC = 5.0V, room temperature) and an assumption of four GLB loads
on average exists and the device is filled with four 16-bit counters. These values are for estimates only. Since the
value of ICC is sensitive to operating conditions and the program in the device, the actual ICC should be verified.
0127B-16-80-isp/1016

9
 Specifications ispLSI 1016E

Pin Description
PLCC TQFP
NAME DESCRIPTION
PIN NUMBERS PIN NUMBERS
I/O 0 - I/O 3 15, 16, 17, 18, 9, 10, 11, 12, Input/Output Pins - These are the general purpose I/O pins used by the logic
I/O 4 - I/O 7 19, 20, 21, 22, 13, 14, 15, 16, array.
I/O 8 - I/O 11 25, 26, 27, 28, 19, 20, 21, 22,
I/O 12 - I/O 15 29, 30, 31, 32, 23, 24, 25, 26,
I/O 16 - I/O 19 37, 38, 39, 40, 31, 32, 33, 34,
I/O 20 - I/O 23 41, 42, 43, 44, 35, 36, 37, 38,
I/O 24 - I/O 27 3, 4, 5, 6, 41, 42, 43, 44,
I/O 28 - I/O 31 7, 8, 9, 10 1, 2, 3, 4

GOE 0/IN 32 2 40 This is a dual function pin. It can be used either as Global Output Enable for
all I/O cells or it can be used as a dedicated input pin.

ispEN 13 7 Input - Dedicated in-system programming enable input pin. This pin is
brought low to enable the programming mode. The MODE, SDI, SDO and
SCLK controls become active.
SDI/IN 01 14 8 Input - This pin performs two functions. When ispEN is logic low, it functions
as an input pin to load programming data into the device. It is a dedicated
input pin when ispEN is logic high.SDI/IN0 also is used as one of the two
control pins for the isp state machine.
MODE/IN 21 36 30 Input - This pin performs two functions. When ispEN is logic low, it functions
as a pin to control the operation of the isp state machine. It is a dedicated
input pin when ispEN is logic high.
SDO/IN 11 24 18 Output/Input - This pin performs two functions. When ispEN is logic low, it
functions as an output pin to read serial shift register data. It is a dedicated
input pin when ispEN is logic high.

SCLK/Y21 33 27 Input - This pin performs two functions. When ispEN is logic low, it
functions as a clock pin for the Serial Shift Register. It is a dedicated clock
input when ispEN is logic high. This clock input is brought into the Clock
Distribution Network, and can optionally be routed to any GLB and/or I/O
cell on the device.
Y0 11 5 Dedicated Clock input. This clock input is connected to one of the clock
inputs of all the GLBs on the device.
Y1/RESET 35 29 This pin performs two functions:
- Dedicated clock input. This clock input is brought into the Clock
Distribution Network, and can optionally be routed to any GLB and/or
I/O cell on the device.
- Active Low (0) Reset pin which resets all of the GLB and I/O registers
in the device.

GND 1, 23 17, 39 Ground (GND)

VCC 12, 34 6, 28 Vcc
Table 2-0002C-16-isp
1. Pins have dual function capability.
2. Pins have dual function capability which is software selectable.

10
 Specifications ispLSI 1016E

Pin Configurations
ispLSI 1016E 44-Pin PLCC Pinout Diagram

GOE 0/IN 32
I/O 27
I/O 26
I/O 25
I/O 24

I/O 23
I/O 22
I/O 21
I/O 20
I/O 19
GND
6 5 4 3 2 1 44 43 42 41 40

I/O 28 7 39 I/O 18
I/O 29 8 38 I/O 17
I/O 30 9 37 I/O 16
I/O 31 10 36 MODE/IN 21
Y0 11 35 Y1/RESET
VCC 12 ispLSI 1016E 34 VCC
ispEN 13 Top View 33 SCLK/Y21
1
SDI/IN 0 14 32 I/O 15
I/O 0 15 31 I/O 14
I/O 1 16 30 I/O 13
I/O 2 17 29 I/O 12

18 19 20 21 22 23 24 25 26 27 28
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
GND
1
I/O 8
I/O 9
I/O 10
I/O 11
1SDO/IN

1. Pins have dual function capability.

2. Pins have dual function capability which is software selectable.
0123A-isp1016

ispLSI 1016E 44-Pin TQFP Pinout Diagram

GOE 0/IN 32
I/O 27
I/O 26
I/O 25
I/O 24

I/O 23
I/O 22
I/O 21
I/O 20
I/O 19
GND

44 43 42 41 40 39 38 37 36 35 34

I/O 28 1 33 I/O 18
I/O 29 2 32 I/O 17
I/O 30 3 31 I/O 16
I/O 31 4 30 MODE/IN 21
Y0 5 29 Y1/RESET
VCC 6
ispLSI 1016E 28 VCC
ispEN 7 Top View 27 SCLK/Y21
1SDI/IN 0 8 26 I/O 15
I/O 0 9 25 I/O 14
I/O 1 10 24 I/O 13
I/O 2 11 23 I/O 12

12 13 14 15 16 17 18 19 20 21 22
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
GND
1
I/O 8
I/O 9
I/O 10
I/O 11
1SDO/IN

1. Pins have dual function capability.

2. Pins have dual function capability which is software selectable.
0851-16E/TQFP

11
 Specifications ispLSI 1016E

Part Number Description

ispLSI 1016E – XXX X XXX X

Device Family Grade
Blank = Commercial
I = Industrial
Device Number
Package
Speed J = PLCC
125 = 125 MHz fmax T44 = TQFP
100 = 100 MHz fmax
80 = 84 MHz fmax Power
L = Low
0212/1016E

ispLSI 1016E Ordering Information

COMMERCIAL
FAMILY fmax (MHz) tpd (ns) ORDERING NUMBER PACKAGE
125 7.5 ispLSI 1016E-125LJ 44-Pin PLCC
125 7.5 ispLSI 1016E-125LT44 44-Pin TQFP
100 10 ispLSI 1016E-100LJ 44-Pin PLCC
ispLSI
100 10 ispLSI 1016E-100LT44 44-Pin TQFP
84 15 ispLSI 1016E-80LJ 44-Pin PLCC
84 15 ispLSI 1016E-80LT44 44-Pin TQFP
Table 2-0041A/1016E

INDUSTRIAL
FAMILY fmax (MHz) tpd (ns) ORDERING NUMBER PACKAGE
84 15 ispLSI 1016E-80LJI 44-Pin PLCC
ispLSI
84 15 ispLSI 1016E-80LT44I 44-Pin TQFP
Table 2-0041B/1016E

12