Volume 7, Issue 7, July – 2022 International Journal of Innovative Science and Research Technology

ISSN No:-2456-2165

Implementation of Turbo Coder Using Verilog

HDL for LTE
V S Sneha
M. TECH VLSI (S4 )
NCERC, Trissur, Kerala, India
Nithin Joe
Assistant Professor ECE Dept
NCERC, Trissur, Kerala, India

Abstract:- In many communication systems, turbo encoder and turbo decoder are components of the turbo coder
codesare employed to repair errors. Turbo codes architecture. Two Recursive Convolutional Encoders (RSC)
demonstrate high error correction when compared to other and an interleaver make up the encoder. As a result of the
error correction methods. A Very Large Scale Integration employment of a pseudo-random interleaver in this study, the
is suggested in this study. VLSI architecture for the Turbo interleaved version of the code tends to be lengthy and chaotic,
encoder implementation, Interleaves and de interleaves, which improves the performance of random codes. RSC
and soft-in-soft-out decoders are employed. This study encoders are used in turbo code implementation rather than
employs a technique that for the encoder portion, includes traditional convolutional encoders because they provide low
two recursive systematic convolutional (RSC) encoders , a weight parity codes. This system employs an Soft Output
Block interleaver and the decoder part involve Soft Output Virtebi Algorithm (SOVA) decoder. Data that has been turbo-
Virtebi Algorithm (SOVA) decoder. A convolutional code is encoded with mistakes that are created on purpose and then
a sort of error-correcting code used in communications that certified as error- free after decoding. Turbo codes are a series
creates parity signals by sliding a Boolean polynomial of high- performance forward error correction (FEC) codes
function across a data stream. The word "convolutional that were developed in the 1990s and 1991s but weren't
coding" comes from the sliding application, which depicts formally presented until 1993. Turbo codes were originally
the encoder's "convolution" across the data. Convolutional known as Turbo codes in French. The Shannon limit, also
codes sliding properties make it easier to do trellis decoding known as the maximum channel capacity, refers to the greatest
with a time-invariant trellis. Convolutional codes can be coding rate at which reliable communication is still possible in
maximum-likelihood soft-decision decoded with a the presence of a specific noise level. They were the first
manageable level of complexity thanks to time invariant practical codes to approach this limit. Turbo codes are
trellis decoding. The Viterbi algorithm, also known as the employed in 3G/4G mobile communications (like UMTS and
Viterbi path, is a dynamic programming approach for LTE), in (deep space) satellite communications, and in other
determining the greatest probability estimate of the most applications where programmers need to achieve dependable
probable series of hidden states that leads to a series of data transfer over bandwidth- or latency-constrained
observed events. The quantity of times needed to decode communication links while contending with data-corrupting
the bits is been reduced in this methodology. A block noise.
interleaver accepts a set of symbols and rearranges them,
without repeating or omitting any of the symbols in the set. II. METHODOLOGY
The number of symbols in each set is fixed for a given
interleaver. Turbo encoding, as well as decoding A. Architecture of Turbo Coder
simulations are done using Modelsim software. The Turbo coder architecture is made up of a turbo
encoder and a turbo decoder. Using pseudorandom interleavers
Keywords:- Turbo Codes; Interleaver; Viterbi Algorithm; and convolutional encoders (RSC) makes up the turbo encoder.
SOVA. A third of the workforce is employed by LTE. Fast code with
simultaneous concatenation rate. Various RSCs work on two
I. INTRODUCTION unique sets of data. The first is given original data second
encoder gets the interleaved data from the first version of the
When data is transported from a source system to a data entered. Interleaving is a technique that scrambles the data
destination system in a communication system, errors may be bits. a significant effect on a decoder's performance when the
present in the signal that is received at the source end. To get interleaving method is used, is seen. The outputs from RSC1
the original message back, rectification is needed. Turbo and RSC2 encoders as well as systematic input consists of a 24
codes, first made available in 1993, symbolise a channel bitoutput. The output of the turbo encoder, which is a 24 bit out
coding methods make a quantum leap, and the tide is turning a put that is composed of the RSC1 and RSC2 encoder outputs
plus for current digital communication. Using turbo codes one as well as systematic input. This will be sent to the Turbo deco
of the potent error-correcting codes currently in use. Booster der through the channel.
codes has motivated the programming community with the
potential for using an iterative decoding method. To obtain
close channel capacity, use simple constituent code. Turbo

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Volume 7, Issue 7, July – 2022 International Journal of Innovative Science and Research Technology
ISSN No:-2456-2165
C. Interleaver Design
Between the two component encoders for turbo codes,
there is an interleaver. The input sequences are given
randomization thanks to the interleaver. For RSC Encoder 1,
the input sequence x generates the low-weight recursive
convolutional coding sequence c2. The interleaver permutes
the input sequence x to prevent RSC Encoder 2 from creating
Fig2.1 Block diagram of Turbo Coder another low-weight recursive output sequence obtain an
alternative sequence that, ideally, results in a high-weight
A r = 1/3 turbo code encoder is shown in Figure 2.1. recursive convolutional Coding pattern c3. The coding weight
of the turbo code is therefore minimal when coupled from
While the second RSC encoder discards its systematic Low- weight code from encoder 1 and high-weight code from
sequence and only produces the recursive convolutional c3 encoder 2.
sequence, the first RSC encoder outputs the systematic c1 and
recursive convolutional c2 sequences.

B. Recursive Systematic Convolutional (RSC) Encoder

By feeding back one of its encoded outputs to its input,
the non recursive nonsystematic (conventional) convolutional
encoder is transformed into the recursive systematic
convolutional (RSC) encoder. A typical convolutional encoder
is shown in Figure 2.2. The generator sequences g1 = [111] and Fig 2.4 The interleaver increases the code weight for RSC
g2 = [101] are used to represent the traditional convolutional Encoder 2 as compared to RSC Encoder
encoder, which may also be expressed more succinctly as
G=[g1, g2]. D. Block Interleaver
The block interleaver is the interleaver that
communication systems employ most frequently. It reads out
rows from left to right and top to bottom and writes in columns
from top to bottom and left to right. A block interleaver is seen
in Figure 2.5.

Fig 2.2 Conventional convolutional encoder with r=1/2

and K=3
Fig 2.5 Block Interleaver
The first output (represented by g1) is sent back to the
input in the RSC encoder of this standard convolutional E. Soft Output Viterbi Algorithm (SOVA)
encoder, which is represented as G=[1, g2 / g1]. In the diagram Because of its straightforward implementation, the
above, 1 stands for the systematic output, g2 for the Viterbi algorithm (VA) is a popular technique for maximum
feedforward output, and g1 for the feedback to the RSC likelihood decoding that can be employed in the majority of
encoder's input. The finished RSC encoder is displayed real-world scenarios. However, one of its drawbacks is that it
in Figure 1.3.According to [Bat93], excellent codes can be is unable to deliver soft-decision outputs. Contrary to soft-
produced by s etting the feedback of the RSC encoder to a output decoders, combining two VA decoders results in a
primitive polynomi al since this adds randomness to the turbo significant performance loss. The SOVA produces a soft (or
code by generating maximum-length sequences. real) dependability number corresponding to each decoded bit
rather than decoded bits (i.e., hard judgments). Other system
components (like a serially concatenated convolutional coding
system) can exploit these soft outputs to enhance overall
performance.

Fig 2.6 Block diagram of SOVA

Fig 2.3 The RSC encoder obtained (from fig 1.2) with r=1/2
and K=3.

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Volume 7, Issue 7, July – 2022 International Journal of Innovative Science and Research Technology
ISSN No:-2456-2165
The turbo decoding algorithm's iterative design principle
in between the two SISO component decoders that are shown
Figure 2.7. It consists of two decoders, those that work
simultaneously to enhance and improve the estimated number
of original data bits. Secondly, the SISO decoder decodes the
convolutional either the first or second CE's code is produced.
A fast iteration is equivalent to one pass of the primary
component decoder, which a trip through the second
component decoder follows.

Fig 3.1 Simulation output of Turbo Encoder

Fig2.7 Block diagram of Turbo Decoder

III. RESULT AND DISCUSSIONS

Verilog HDL is the coding language employed in this

proposed system and the timing analysis has been performed
using Modelsim Software.

F. Simulation Output of Turbo Encoder

Figure 3.1 shows the simulation output of turbo encoder.
Signals st1 and st2 represents clock and reset signals Fig 3.2 Simulation Output of Turbo Decoder
respectively. The signal x represents the input signal of the
system. For RSC Encoder 1, the input sequence x generates the IV. CONCLUSION
low-weight recursive convolutional coding sequence c2. The
interleaver permutes the input sequence x to prevent RSC Turbo encoder and turbo decoder are components of the
Encoder 2 from creating another low-weight recursive output turbo coder architecture. Two Recursive Convolutional
sequence obtain an alternative sequence that, ideally, results in Encoders (RSC) and an interleaver make up the encoder. As a
a high-weight recursive convolutional Coding pattern c3. The result of the employment of a pseudo-random interleaver in
coding weight of the turbo code is therefore minimal when this study, the interleaved version of the code tends to be
coupled from Low-weight code from encoder 1 and high - lengthy and chaotic, which improves the performance of
weight code from encoder 2. While the second RSC encoder random codes. RSC encoders are used in turbo code
discards its systematic sequence and only produces the implementation rather than traditional convolutional encoders
recursive convolutional c3 sequence, the first RSC encoder because they provide low weight parity codes. Good codes can
outputs the systematic c1 and recursive convolutional c2 be obtained by setting the feedback of the RSC encoder to a
sequences. primitive polynomial, because the primitive polynomial
generates maximum-length sequences which adds randomness
G. Simulation Output of Turbo Decoder to the turbo code This system employs an Soft Output Virtebi
The turbo decoding algorithm's iterative design principle Algorithm (SOVA) decoder. Data that has been turbo-encoded
in between the two SISO component decoders. It consists of with mistakes that are created on purpose and then certified as
two decoders, those that work simultaneously to enhance and error-free after decoding. The optimal decoding technique,
improve the estimated number of original data bits. Secondly, known as the Viterbi decoding method, identifies the most
the SISO decoder decodes the convolutional either the first or likely pattern from the incoming data using the maximum
second CE's code is produced. A fast iteration is equivalent to likelihood decoding (MLD) algorithm. This makes Viterbi
one pass of the primary component decoder, which a trip decoding method most efficient when compared to the other
through the second component decoder follows. existing decoding methods .

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Volume 7, Issue 7, July – 2022 International Journal of Innovative Science and Research Technology
ISSN No:-2456-2165
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