A Parallel Systems Technical Note

Defining constraints for a DDR memory in PCB Editor

DDR Constraints example

This application note will describe the basic setup options required to constraint a DDR memory. This is a generic
example of how to set and define constraints using Cadence OrCAD PCB Professional and should be checked with
your own specific design guidelines / rules from the component manufacturers. This is not a working or tested
version of DDR memory but an example of how to set Constraints using the Cadence PCB tools. The version used
in this example is 17.4-2019 S003, although the methods used should be consistent with other versions of this
software provided that they enable access to the relevant Electrical worksheets in Constraint Manager. There are
also different methods available to achieve this setup, for example by using Allegro PCB Designer + High Speed
Option which would simplify the pin pair creation and by using SI Explorer, which would provide the ability to
make templates of the nets in question, then apply those templates to netclasses to achieve the same results
more quickly.

DDR Schematic

Click here for a link to the PDF file for a simple schematic used in this example. It contains one FPGA and four
memory devices plus decoupling capacitors and termination resistors. The general idea for this setup is to route
these together using a daisy chain (fly-by) topology meaning start the routing from the controller to the first
memory device then the next and so on. Based on this schematic U1 > U2 > U3 > U4 > U5, The following two
pictures show the FPGA device and one of the memory devices. Open the PDF for a full view of the schematic.

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Defining constraints for a DDR memory in PCB Editor

Constraints
All the rules defined are setup using Constraint Manager. This can be accessed from either OrCAD Capture or PCB
Editor. Both methods allow access to a full Constraint Manager. If setting constraints via the front end (OrCAD
Capture) the key is to ensure that the schematic and PCB stay in sync. ALWAYS ensure using the Design Sync
command from the board file into the schematic has been completed before making changes.

Physical and Spacing Constraints

This design has three physical rules and one spacing rule. (You may also need additional physical and spacing rules
depending on your specific design). Constraint Regions (rules by area) may also be required, for example where
additional rules may be required to neck down the track and decrease gap rules to allow you to route the board.
The three physical rules are as shown below and can be created by selecting the default rule and right click >
Create > Physical CSet, then enter the required name and setting the appropriate values.

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Defining constraints for a DDR memory in PCB Editor

For spacing rules, the default rule is good enough for this example with all values set to 0.15mm.

The Power rule is applied to the three power nets DDR_VDD, DDR_VTT and GND and the DIFFPAIR rules are
applied to three differential pairs DP_LDQS, DP_CK and DP_UDQS. These were made with
Objects>Create>Differential Pair and the relevant net names selected and named. These have been grouped into
a Netclass to simplify the constraints.

Electrical Constraints
We will start by creating some netclasses to define the nets into their relevant groups. In Constraint
Manager>Electrical>Net>Routing>Wiring group select DDR.A0>DDR.A15 then right click>Create>Netclass and
name this ADDRESS. We also need to make two byte lanes that consist of DDR.DQ0-7, DDR.LDM and DDR.LDQS#
in one and DDR.DQ8-15, DDR.UDM and DDR/UDQS# in the other. These have been named BYTELANE0 and
BYTELANE1. You will notice that only one half of each differential pair has been put into each bytelane. This will
allow the diff pair members to be matched with one set of constraints (static phase) and avoid over constraining
the design.

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Defining constraints for a DDR memory in PCB Editor

Create an Electrical CSet for the differential pairs so under Constraint Manager>Electrical>Electrical Constraint Set
>Routing>Differential Pair make a new rule for the differential pairs, remember that we only need to define the
uncoupled length, static and dynamic phase rules since the coupling parameters (track and gap) are covered by
physical rules.

Once the rule is created, apply this to the three differential pairs.

Matched Groups.
The IC rules typically define how and what nets are required to be length matched and by what tolerance. For the
first part we need to match the Address and Control lines from the FPGA to the first memory device (U1>U2).
Locate the relevant nets in Constraint Manager>Electrical>Net>Routing>Relative Propagation Delay worksheet
and right click>Create>Pin Pair, choose the start and end and define the pin pairs required. (If you had access to
an Allegro PCB Designer + High Speed license this could be achieved using Sig Explorer by making a topology
template).

Another method would be to create a Match Group name (say DIMM1) then select the Match Group name and
choose right click>Match Group Members, you will notice that this only lists Nets.

To generate the PinPairs quickly open the Min/Max Propagation Delay worksheet and specify a value for Min
length for the Address and Bytelane classes (1mm will do) and OrCAD Professional automatically generates all the
relevant pin pairs.

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Defining constraints for a DDR memory in PCB Editor

Return to the Relative Propagation delay worksheet, select the Match Group name and right click>Match Group
Members and now notice that the Pin Pairs are available to be selected. Use the Filters for U1.*:U2 to filter the
list and move the objects to cerate the match group members. Repeat for the remainder of the match groups you
require.

Remember to remove the Min Propagation delay rule you defined to aid in the quick generation of Pin Pairs.

Once all the pin pairs are created, select them all (left click + shift left click) then right click>Create>Match Group.
Specify the name. Once created set the Delta:Tolerance values and either accept a default Target (longest
unrouted member) or choose your required target.

To visualise this, enable Analysis>Analysis Mode>Electrical and turn on DRC unrouted Relative Propagation Delay,
or right click the Delta:Tolerance cell of the pin pair you want to be the Target value and choose Set as Target.

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Defining constraints for a DDR memory in PCB Editor

Repeat these steps for U2>U3, U3>U4 AND U4>U5 as shown below:-

Using the same method create the pin pairs for the byte lanes. These also follow the fly by topology (so
U1>U2>U3>U4>U5.

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Defining constraints for a DDR memory in PCB Editor

Another useful Electrical Constraint is a Wiring constraint to verify that the net(s) in question are routed the way
you want them to be. For this design use Edit>Net Schedule, then pick each net and select the path you want to
route it on. This creates a User Defined schedule (Constraint Manager>Electrical>Net>Routing>Wiring worksheet)
which can then have a Verify set to Yes to confirm that you follow this topology. You can also define a maximum
stub length (fanout via distance). In this example all the nets have been manually scheduled, if you have access to
Allegro PCB Designer you can schedule one net then make an ECSet from that and apply it to all the other nets. If
you have access to Allegro PCB Designer + High Speed, then this can all be achieved within SigExplorer and
applied directly to the design. (Address bus shown only for information).

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Defining constraints for a DDR memory in PCB Editor

Routing the design

Once the rules are set (and remember this is just an example of a DDR fly-by topology). You are now ready to start
routing the design. This can be done either manually or automatically using the OrCAD Designer Professional
autorouter. In this example though the routing was completed manually using four routing layers, TOP, INNER1,
INNER2 and BOTTOM, leaving a dedicated GND plane and a Split power plane for DDR_VDD and DDR_VDD. To
improve impedance and limit crosstalk you may want to route the majority of the DDR routes onto inner layers.
When routing remember to leave enough room between the traces to allow for length matching patterns such as
accordion and trombone. The automatic tools (AiDT and AiPT available from Allegro + High Speed) will spread the
routing but try and allow for this if possible. You can get an idea about how much room you need from the
screenshots in the next few pages.

Once the basic routing has been added you could if you have access use the Allegro PCB Designer + High Speed
option and use tools such as Timing Vision and Auto Interactive Delay and Phase tuning to match the lengths of
the match groups defined. If you don’t have access to these you can still achieve the results using Delay and Phase
Tuning, it just might take longer.

You can download the actual OrCAD/Allegro board file. In the PDF look at the Attachments icon then right click –
Save Attachment and save the board file locally.

PCB Layers
Below are screenshots of each layer of the PCB to give you an idea of the routing.

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Defining constraints for a DDR memory in PCB Editor

TOP

GND

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Defining constraints for a DDR memory in PCB Editor

INNER1

INNER2

POWER

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BOTTOM

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Defining constraints for a DDR memory in PCB Editor

Considerations
There are some instances in this design where some of the design rules may have been tweaked to allow for a
successful route. Differential Pair uncoupled length is one example where a decision to match the differential pair
lengths to meet the criteria was made over the differential pair being uncoupled longer for certain sections of the
routing. That may/may not be the correct decision, but these are choices you can make on your own designs.

The same can also be said for Stub length where a default fanout via may have been moved to improve routing
channels.

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