Introduction to RTL

GCC Resource Center

(www.cse.iitb.ac.in/˜uday)

Department of Computer Science and Engineering,

Indian Institute of Technology, Bombay

March 2010
March 2010 RTL: Outline 1/27

Outline

• RTL: The Overall Perspective

• RTL: An External View

• RTL: An Internal View

• RTL: An Example Program to Manipulate RTL

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 Part 1

RTL: The Overall Perspective

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What is RTL ?

RTL = Register Transfer Language

Assembly language for an abstract machine with infinite registers

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Why RTL?

A lot of work in the back-end depends on RTL. Like,

• Low level optimizations like loop optimization, loop dependence,
common subexpression elimination, etc
• Instruction scheduling
• Register Allocation
• Register Movement

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Why RTL?

For tasks such as those, RTL supports many low level features, like,
• Register classes
• Memory addressing modes
• Word sizes and types
• Compare and branch instructions
• Calling Conventions
• Bitfield operations

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The Dual Role of RTL

• For specifying machine descriptions

Machine description constructs:
◮ define insn, define expand, match operand
• For representing program during compilation
IR constructs
◮ insn, jump insn, code label, note, barrier

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Role of Machine Descriptions in Translation

Target Independent Target Dependent

Tree SSA Generate Generate
Parse Gimplify Optimize RTL
Optimize RTL ASM

Gimple → RTL RTL → ASM

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Role of Machine Descriptions in Translation

Target Independent Target Dependent

Tree SSA Generate Generate
Parse Gimplify Optimize RTL
Optimize RTL ASM

Gimple → RTL RTL → ASM

MD Info Required

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Generating RTL IR During Compilation

C Source Code

Parser local reg allocator

AST lregs
Gimplifier global reg allocator
Gimple Gregs
Linearizer pro epilogue generation
Lower prologue-epilogue
CFG Generator Pattern Matcher
CFG
RTL Generator ASM Program
RTL expand

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A Target Instruction in Machine Descriptions

(define_insn
"movsi"
(set
(match_operand 0 "register_operand" "r")
(match_operand 1 "const_int_operand" "k")
)
"" /* C boolean expression, if required */
"li %0, %1"
)

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A Target Instruction in Machine Descriptions

Define instruction pattern Standard Pattern Name

(define_insn
"movsi"
(set
(match_operand 0 "register_operand" "r")
(match_operand 1 "const_int_operand" "k")
)
"" /* C boolean expression, if required */
"li %0, %1"
)

RTL Expression (RTX): target asm inst. =

Semantics of target instruction Concrete syntax for RTX

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A Target Instruction in Machine Descriptions

RTL operator MD constructs

(define_insn
"movsi"
(set
(match_operand 0 "register_operand" "r")
(match_operand 1 "const_int_operand" "k")
)
"" /* C boolean expression, if required */
"li %0, %1"
)

Predicates Constraints

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An Example of Translation

(define_insn
"movsi"
(set
(match_operand 0 "register_operand" "r")
(match_operand 1 "const_int_operand" "k")
)
"" /* C boolean expression, if required */
"li %0, %1"
)

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March 2010 RTL: The Overall Perspective 9/27

An Example of Translation

(define_insn
"movsi"

Development
(set
(match_operand 0 "register_operand" "r")
(match_operand 1 "const_int_operand" "k")
)
"" /* C boolean expression, if required */
"li %0, %1"
)

(set

Use
(reg:SI 58 [D.1283])
D.1283 = 10; (const int 10: [0xa]) li $t0, 10
)
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The Essence of Retargetability

When are the machine descriptions read?

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The Essence of Retargetability

When are the machine descriptions read?

• During the build process

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The Essence of Retargetability

When are the machine descriptions read?

• During the build process
• When a program is compiled by gcc the information gleaned from
machine descriptions is consulted

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March 2010 RTL: The Overall Perspective 11/27

Retargetability Mechanism of GCC

Input Language Target Name

Compiler Generation Framework

Language and Machine

Language
Machine Dependent Machine Development
Specific Time
Independent Generator Descriptions
Code
Generic Code Code

Selected Copied Generated Build

Time
Copied
Generated

Tree SSA RTL Code Use

Parser Gimplifier Optimizer
Optimizer Generator Generator Time
Generated Compiler

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March 2010 RTL: The Overall Perspective 11/27

Retargetability Mechanism of GCC

Input Language Target Name

Compiler Generation Framework

Language and Machine

Language
Machine Dependent Machine Development
Specific Time
Independent Generator Descriptions
Code
Generic Code Code

Selected Copied Generated Build

Time
Copied
Generated
Gimple → IR-RTL
Tree SSA RTL Code Use
Parser Gimplifier
Optimizer Generator
Optimizer
Generator Time
+
Generated Compiler
IR-RTL → ASM

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Retargetability Mechanism of GCC

Input Language Target Name

Compiler Generation Framework

Gimple → PN
Language and Machine +
Language
Machine Dependent Machine Development
Specific
Independent Generator Descriptions Time PN → IR-RTL
Code +
Generic Code Code
IR-RTL → ASM
Selected Copied Generated Build
Time
Copied
Generated
Gimple → IR-RTL
Tree SSA RTL Code Use
Parser Gimplifier
Optimizer Generator
Optimizer
Generator Time
+
Generated Compiler
IR-RTL → ASM

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March 2010 RTL: The Overall Perspective 11/27

Retargetability Mechanism of GCC

Input Language Target Name

Compiler Generation Framework

Gimple → PN
Language and Machine +
Language
Machine Dependent Machine Development
Specific
Independent Generator Descriptions Time PN → IR-RTL
Code +
Generic Code Code
IR-RTL → ASM
Selected Copied Generated Build
Time
Copied
Generated
Gimple → IR-RTL
Tree SSA RTL Code Use
Parser Gimplifier
Optimizer Generator
Optimizer
Generator Time
+
Generated Compiler
IR-RTL → ASM

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March 2010 RTL: The Overall Perspective 11/27

Retargetability Mechanism of GCC

Input Language Target Name

Compiler Generation Framework

Gimple → PN
Language and Machine +
Language
Machine Dependent Machine Development
Specific
Independent Generator Descriptions Time PN → IR-RTL
Code +
Generic Code Code
IR-RTL → ASM
Selected Copied Generated Build
Time
Copied
Generated
Gimple → IR-RTL
Tree SSA RTL Code Use
Parser Gimplifier
Optimizer Generator
Optimizer
Generator Time
+
Generated Compiler
IR-RTL → ASM

Essential Abstrations in GCC GCC Resource Center, IIT Bombay

 Part 2

RTL: An External View

March 2010 RTL: An External View 12/27

RTL for i386: Examples

Translation of a = a + 1
Dump file: test.c.131r.expand stack($fp - 4) = stack($fp - 4) + 1
|| flags=?

(insn 12 11 10 (parallel [ Low addr

(set (mem/c/i:SI (plus:SI
(reg/f:SI 54 virtual-stack-vars) $fp - 4 a
(const int -4 [...])) [...]) $fp
(plus:SI
(mem/c/i:SI (plus:SI
(reg/f:SI 54 virtual-stack-vars) High addr
(const int -4 [...])) [...])
(const int 1 [...])))
(clobber (reg:CC 17 flags))
]) -1 (nil))
Plus operation computes $fp - 4 as the address of variable a

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March 2010 RTL: An External View 12/27

RTL for i386: Examples

Translation of a = a + 1
Dump file: test.c.131r.expand stack($fp - 4) = stack($fp - 4) + 1
|| flags=?
(insn 12 11 10 (parallel[
( set (mem/c/i:SI (plus:SI
(reg/f:SI 54 virtual-stack-vars)
(const int -4 [...])) [...])
(plus:SI
(mem/c/i:SI (plus:SI
(reg/f:SI 54 virtual-stack-vars)
(const int -4 [...])) [...])
(const int 1 [...])))
(clobber (reg:CC 17 flags))
]) -1 (nil))

Set denotes assignment

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March 2010 RTL: An External View 12/27

RTL for i386: Examples

Translation of a = a + 1
Dump file: test.c.131r.expand stack($fp - 4) = stack($fp - 4) + 1
|| flags=?

(insn 12 11 10 (parallel [
( set (mem/c/i:SI (plus:SI
(reg/f:SI 54 virtual-stack-vars)
(const int -4 [...])) [...])
(plus:SI
(mem/c/i:SI (plus:SI
(reg/f:SI 54 virtual-stack-vars)
(const int -4 [...])) [...])
(const int 1 [...])))
(clobber (reg:CC 17 flags))
]) -1 (nil))
1 is added to variable a

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March 2010 RTL: An External View 12/27

RTL for i386: Examples

Translation of a = a + 1
Dump file: test.c.131r.expand stack($fp - 4) = stack($fp - 4) + 1
|| flags=?

(insn 12 11 10 (parallel [
( set (mem/c/i:SI (plus:SI
(reg/f:SI 54 virtual-stack-vars)
(const int -4 [...])) [...])
(plus:SI
(mem/c/i:SI (plus:SI
(reg/f:SI 54 virtual-stack-vars)
(const int -4 [...])) [...])
(const int 1 [...])))
(clobber (reg:CC 17 flags))
]) -1 (nil))

Condition Code register is clobbered to record possible side effect of plus

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March 2010 RTL: An External View 13/27

Flags in RTL Expressions

Meanings of some of the common flags

/c memory reference that does not trap

/i scalar that is not part of an aggregate
/f register that holds a pointer

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March 2010 RTL: An External View 14/27

RTL for spim: Examples

Translation of a = a + 1
Dump file: test.c.131r.expand
r39=stack($fp - 4)
r40=r39+1
stack($fp - 4)=r40
(insn 7 6 8 test.c:6 (set (reg:SI 39)
(mem/c/i:SI (plus:SI (reg/f:SI 33 virtual-stack-vars)
(const_int -4 [...])) [...])) -1 (nil))
(insn 8 7 9 test.c:6 (set (reg:SI 40)
(plus:SI (reg:SI 39)
(const_int 1 [...]))) -1 (nil))
(insn 9 8 0 test.c:6 (set
(mem/c/i:SI (plus:SI (reg/f:SI 33 virtual-stack-vars)
(const_int -4 [...])) [...])
(reg:SI 40)) -1 (nil))

In spim, a variable is loaded into register to perform any instruction,

hence three instructions are generated

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March 2010 RTL: An External View 14/27

RTL for spim: Examples

Translation of a = a + 1
Dump file: test.c.131r.expand
r39=stack($fp - 4)
r40=r39+1
stack($fp - 4)=r40
(insn 7 6 8 test.c:6 (set (reg:SI 39)
(mem/c/i:SI (plus:SI (reg/f:SI 33 virtual-stack-vars)
(const_int -4 [...])) [...])) -1 (nil))
(insn 8 7 9 test.c:6 (set (reg:SI 40)
(plus:SI (reg:SI 39)
(const_int 1 [...]))) -1 (nil))
(insn 9 8 0 test.c:6 (set
(mem/c/i:SI (plus:SI (reg/f:SI 33 virtual-stack-vars)
(const_int -4 [...])) [...])
(reg:SI 40)) -1 (nil))

In spim, a variable is loaded into register to perform any instruction,

hence three instructions are generated

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March 2010 RTL: An External View 14/27

RTL for spim: Examples

Translation of a = a + 1
Dump file: test.c.131r.expand
r39=stack($fp - 4)
r40=r39+1
stack($fp - 4)=r40
(insn 7 6 8 test.c:6 (set (reg:SI 39)
(mem/c/i:SI (plus:SI (reg/f:SI 33 virtual-stack-vars)
(const_int -4 [...])) [...])) -1 (nil))
(insn 8 7 9 test.c:6 (set (reg:SI 40)
(plus:SI (reg:SI 39)
(const_int 1 [...]))) -1 (nil))
(insn 9 8 0 test.c:6 (set
(mem/c/i:SI (plus:SI (reg/f:SI 33 virtual-stack-vars)
(const_int -4 [...])) [...])
(reg:SI 40)) -1 (nil))

In spim, a variable is loaded into register to perform any instruction,

hence three instructions are generated

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March 2010 RTL: An External View 15/27

RTL for i386: Examples

What does this represent?

(jump insn 15 14 16 4 p1.c:6 (set (pc)

(if then else (lt (reg:CCGC 17 flags)
(const int 0 [0x0]))
(label ref 12)
(pc))) (nil)
(nil))

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March 2010 RTL: An External View 15/27

RTL for i386: Examples

What does this represent?

(jump insn 15 14 16 4 p1.c:6 (set (pc)

(if then else (lt (reg:CCGC 17 flags)
(const int 0 [0x0]))
(label ref 12)
(pc))) (nil)
(nil))

pc = r17 <0 ? label(12) : pc

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RTL for i386: Examples

Translation of if (a > b)
Dump file: test.c.131r.expand

(insn 8 7 9 test.c:7 (set (reg:SI 61)

(mem/c/i:SI (plus:SI (reg/f:SI 54 virtual-stack-vars)
(const int -8 [0xfffffff8])) [0 a+0 S4 A32])) -1 (nil))
(insn 9 8 10 test.c:7 (set (reg:CCGC 17 flags)
(compare:CCGC (reg:SI 61)
(mem/c/i:SI (plus:SI (reg/f:SI 54 virtual-stack-vars)
(const int -4 [0xfffffffc])) [0 b+0 S4 A32]))) -1 (nil)
(jump insn 10 9 0 test.c:7 (set (pc)
(if then else (le (reg:CCGC 17 flags)
(const int 0 [0x0]))
(label ref 0)
(pc))) -1 (nil))

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RTL for i386: Examples

Translation of if (a > b)
Dump file: test.c.131r.expand

(insn 8 7 9 test.c:7 (set (reg:SI 61)

(mem/c/i:SI (plus:SI (reg/f:SI 54 virtual-stack-vars)
(const int -8 [0xfffffff8])) [0 a+0 S4 A32])) -1 (nil))
(insn 9 8 10 test.c:7 (set (reg:CCGC 17 flags)
(compare:CCGC (reg:SI 61)
(mem/c/i:SI (plus:SI (reg/f:SI 54 virtual-stack-vars)
(const int -4 [0xfffffffc])) [0 b+0 S4 A32]))) -1 (nil)
(jump insn 10 9 0 test.c:7 (set (pc)
(if then else (le (reg:CCGC 17 flags)
(const int 0 [0x0]))
(label ref 0)
(pc))) -1 (nil))

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RTL for i386: Examples

Translation of if (a > b)
Dump file: test.c.131r.expand

(insn 8 7 9 test.c:7 (set (reg:SI 61)

(mem/c/i:SI (plus:SI (reg/f:SI 54 virtual-stack-vars)
(const int -8 [0xfffffff8])) [0 a+0 S4 A32])) -1 (nil))
(insn 9 8 10 test.c:7 (set (reg:CCGC 17 flags)
(compare:CCGC (reg:SI 61)
(mem/c/i:SI (plus:SI (reg/f:SI 54 virtual-stack-vars)
(const int -4 [0xfffffffc])) [0 b+0 S4 A32]))) -1 (nil)
(jump insn 10 9 0 test.c:7 (set (pc)
(if then else (le (reg:CCGC 17 flags)
(const int 0 [0x0]))
(label ref 0)
(pc))) -1 (nil))

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 Part 3

RTL: An Internal View

March 2010 RTL: An Internal View 17/27

RTL Objects

• Types of RTL Objects

◮ Expressions

◮ Integers
◮ Wide Integers

◮ Strings

◮ Vectors

• Internal representation of RTL Expressions

◮ Expressions in RTX are represented as trees
◮ A pointer to the C data structure for RTL is called rtx

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RTX Codes

RTL Expressions are classified into RTX codes :

• Expression codes are names defined in rtl.def
• RTX codes are C enumeration constants
• Expression codes and their meanings are machine-independent
• Extract the code of a RTX with the macro GET CODE(x)

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RTL Classes

RTL expressions are divided into few classes, like:

• RTX UNARY : NEG, NOT, ABS
• RTX BIN ARITH : MINUS, DIV
• RTX COMM ARITH : PLUS, MULT
• RTX OBJ : REG, MEM, SYMBOL REF
• RTX COMPARE : GE, LT
• RTX TERNARY : IF THEN ELSE
• RTX INSN : INSN, JUMP INSN, CALL INSN
• RTX EXTRA : SET, USE

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March 2010 RTL: An Internal View 20/27

RTX Codes
The RTX codes are defined in rtl.def using cpp macro call
DEF RTL EXPR, like :
• DEF RTL EXPR(INSN, "insn", "iuuBieie", RTX INSN)
• DEF RTL EXPR(SET, "set", "ee", RTX EXTRA)
• DEF RTL EXPR(PLUS, "plus", "ee", RTX COMM ARITH)
• DEF RTL EXPR(IF THEN ELSE, "if then else", "eee",
RTX TERNARY)

The operands of the macro are :

• Internal name of the rtx used in C source. It’s a tag in
enumeration ‘‘enum rtx code"
• name of the rtx in the external ASCII format
• Format string of the rtx, defined in rtx format[]
• Class of the rtx

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March 2010 RTL: An Internal View 21/27

RTX Formats

DEF RTL EXPR(INSN, "insn", "iuuBieie", RTX INSN)

• i : Integer
• u : Integer representing a pointer
• B : Pointer to basic block
• e : Expression

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March 2010 RTL: An Internal View 22/27

RTL statements

• RTL statements are instances of type rtx

• RTL insns contain embedded links
• Types of RTL insns :
◮ INSN : Normal non-jumping instruction
◮ JUMP INSN : Conditional and unconditional jumps
◮ CALL INSN : Function calls
◮ CODE LABEL: Target label for JUMP INSN
◮ BARRIER : End of control Flow
◮ NOTE : Debugging information

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March 2010 RTL: An Internal View 23/27

Basic RTL APIs

• XEXP,XINT,XWINT,XSTR
◮ Example: XINT(x,2) accesses the 2nd operand of rtx x as an

integer
◮ Example: XEXP(x,2) accesses the same operand as an expression

• Any operand can be accessed as any type of RTX object

◮ So operand accessor to be chosen based on the format string of the

containing expression
• Special macros are available for Vector operands
◮ XVEC(exp,idx) : Access the vector-pointer which is operand

number idx in exp

◮ XVECLEN (exp, idx ) : Access the length (number of elements) in

the vector which is in operand number idx in exp. This value is an int
◮ XVECEXP (exp, idx, eltnum ) : Access element number

“eltnum” in the vector which is in operand number idx in exp. This

value is an RTX

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March 2010 RTL: An Internal View 24/27

RTL Insns

• A function’s code is a doubly linked chain of INSN objects

• Insns are rtxs with special code
• Each insn contains atleast 3 extra fields :
◮ Unique id of the insn , accessed by INSN UID(i)
◮ PREV INSN(i) accesses the chain pointer to the INSN
preceeding i
◮ NEXT INSN(i) accesses the chain pointer to the INSN
succeeding i
• The first insn is accessed by using get insns()
• The last insn is accessed by using get last insn()

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 Part 4

RTL: An Example Program to

Manipulate RTL
March 2010 RTL: An Example Program to Manipulate RTL 25/27

Sample Demo Program

Problem statement : Counting the number of SET objects in a basic

block by adding a new RTL pass
• Add your new pass after pass expand
• new rtl pass main is the main function of the pass
• Iterate through different instructions in the doubly linked list of
instructions and for each expression, call eval rtx(insn) for that
expression which recurse in the expression tree to find the set
statements

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int new rtl pass main(void){

basic block bb;
rtx last,insn,opd1,opd2;
int bbno,code,type;
count = 0;
for (insn=get insns(), last=get last insn(),
last=NEXT INSN(last); insn!=last; insn=NEXT INSN(insn))
{ int is insn;
is insn = INSN P (insn);
if(flag dump new rtl pass)
print rtl single(dump file,insn);
code = GET CODE(insn);
if(code==NOTE){ ... }
if(is insn)
{ rtx subexp = XEXP(insn,5);
eval rtx(subexp);
}
}
...
}
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March 2010 RTL: An Example Program to Manipulate RTL 26/27

int new rtl pass main(void){

basic block bb;
rtx last,insn,opd1,opd2;
int bbno,code,type;
count = 0;
for (insn=get insns(), last=get last insn(),
last=NEXT INSN(last); insn!=last; insn=NEXT INSN(insn))
{ int is insn;
is insn = INSN P (insn);
if(flag dump new rtl pass)
print rtl single(dump file,insn);
code = GET CODE(insn);
if(code==NOTE){ ... }
if(is insn)
{ rtx subexp = XEXP(insn,5);
eval rtx(subexp);
}
}
...
}
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March 2010 RTL: An Example Program to Manipulate RTL 27/27

void eval rtx(rtx exp)

{ rtx temp;
int veclen,i,
int rt code = GET CODE(exp);
switch(rt code)
{ case SET:
if(flag dump new rtl pass){
fprintf(dump file,"\nSet statement %d : \t",count+1);
print rtl single(dump file,exp);}
count++; break;
case PARALLEL:
veclen = XVECLEN(exp, 0);
for(i = 0; i < veclen; i++)
{ temp = XVECEXP(exp, 0, i);
eval rtx(temp);
}
break;
default: break;
}
}
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March 2010 RTL: An Example Program to Manipulate RTL 27/27

void eval rtx(rtx exp)

{ rtx temp;
int veclen,i,
int rt code = GET CODE(exp);
switch(rt code)
{ case SET:
if(flag dump new rtl pass){
fprintf(dump file,"\nSet statement %d : \t",count+1);
print rtl single(dump file,exp);}
count++; break;
case PARALLEL:
veclen = XVECLEN(exp, 0);
for(i = 0; i < veclen; i++)
{ temp = XVECEXP(exp, 0, i);
eval rtx(temp);
}
break;
default: break;
}
}
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March 2010 RTL: An Example Program to Manipulate RTL 27/27

void eval rtx(rtx exp)

{ rtx temp;
int veclen,i,
int rt code = GET CODE(exp);
switch(rt code)
{ case SET:
if(flag dump new rtl pass){
fprintf(dump file,"\nSet statement %d : \t",count+1);
print rtl single(dump file,exp);}
count++; break;
case PARALLEL:
veclen = XVECLEN(exp, 0);
for(i = 0; i < veclen; i++)
{ temp = XVECEXP(exp, 0, i);
eval rtx(temp);
}
break;
default: break;
}
}
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