MT29F64G08CBAAA Micron

Micron Confidential and Proprietary
64Gb, 128Gb, 256Gb, 512Gb Asynchronous/Synchronous NAND

Features
NAND Flash Memory

MT29F64G08CBAA[A/B], MT29F128G08C[E/F]AAA, MT29F128G08CFAAB,
MT29F256G08C[J/K/M]AAA, MT29F256G08CJAAB, MT29F512G08CUAAA,
MT29F64G08CBCAB, MT29F128G08CECAB, MT29F256G08C[K/M]CAB,
MT29F512G08CUCAB
Features • RESET (FFh) required as first command after power-

on
• Open NAND Flash Interface (ONFI) 2.2-compliant1
• Multiple-level cell (MLC) technology • Operation status byte provides software method for
• Organization detecting
– Page size x8: 8640 bytes (8192 + 448 bytes) – Operation completion
– Block size: 256 pages (2048K + 112K bytes) – Pass/fail condition
– Plane size: 2 planes x 2048 blocks per plane – Write-protect status
– Device size: 64Gb: 4096 blocks; • Data strobe (DQS) signals provide a hardware meth-
128Gb: 8192 blocks; od for synchronizing data DQ in the synchronous
256Gb: 16,384 blocks; interface
512Gb: 32,786 blocks • Copyback operations supported within the plane
• Synchronous I/O performance from which data is read
– Up to synchronous timing mode 52 • Quality and reliability
– Clock rate: 10ns (DDR) – Data retention: JESD47G compliant; see qualifica-
– Read/write throughput per pin: 200 MT/s tion report
• Asynchronous I/O performance – Endurance: 3000 PROGRAM/ERASE cycles
– Up to asynchronous timing mode 5 • Operating temperature:
– tRC/tWC: 20ns (MIN) – Commercial: 0°C to +70°C
– Up to asynchronous timing mode 5 – Industrial (IT): –40ºC to +85ºC
– Read/write throughput per pin: 50 MT/s • Package
• Array performance – 52-pad LGA
– Read page: 75µs (MAX) – 48-pin TSOP
– Program page: 1300µs (TYP) – 100-ball BGA
– Erase block: 3.8ms (TYP) Notes: 1. The ONFI 2.2 specification is available at
• Operating Voltage Range www.onfi.org.
– VCC: 2.7–3.6V 2. BGA devices up to Synchronous timing
– VCCQ: 1.7–1.95V, 2.7–3.6V mode 5. TSOP devices up to Synchronous tim-
• Command set: ONFI NAND Flash Protocol ing mode 4.
• Advanced Command Set
– Program cache
– Read cache sequential
– Read cache random
– One-time programmable (OTP) mode
– Multi-plane commands
– Multi-LUN operations
– Read unique ID
– Copyback
• First block (block address 00h) is valid when ship-
ped from factory. For minimum required ECC, see
Error Management (page 109).
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Rev. E 3/11 EN 1 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.

Features
Part Numbering Information

Micron NAND Flash devices are available in different configurations and densities. Verify valid part numbers by
using Micron’s part catalog search at www.micron.com. To compare features and specifications by device type,
visit www.micron.com/products. Contact the factory for devices not found.
Figure 1: Part Numbering
MT 29F 64G 08 C B A A A WP ES :A
Micron Technology Design Revision

A = First revision
NAND Flash
29F = NAND Flash memory Production Status
Blank = Production
ES = Engineering sample
Density
64G = 64Gb
128G = 128Gb
256G = 256Gb Reserved for Future Use
512G = 512Gb Blank
Device Width Operating Temperature Range

08 = 8 bits Blank = Commercial (0°C to +70°C)
IT = Industrial (–40°C to +85°C)
Level
Bit/Cell Speed Grade (synchronous mode only)
-12 = 166 MT/s
C 2-bit -10 = 200 MT/s
Classification Package Code

Die # of CE# # of R/B# I/O C5 = 52-pad VLGA 14mm x 18mm x 1.0mm1
H1 = 100-ball VBGA 12mm x 18mm x 1.0mm1
B 1 1 1 Common
H2 = 100-ball TBGA 12mm x 18mm x 1.2mm1
E 2 2 2 Separate H3 = 100-ball LBGA 12mm x 18mm x 1.4mm1
F 2 2 2 Common WP = 48-pin TSOP1 (CPL)
J 4 2 2 Common
K 4 2 2 Separate Interface
M 4 4 4 Separate A = Async only
U 8 4 4 Separate B = Sync/Async
Generation Feature Set

Operating Voltage Range A = First set of device features
A = VCC: 3.3V (2.7–3.6V), VCCQ: 3.3V (2.7–3.6V)
C = VCC: 3.3V (2.7–3.6V), VCCQ: 1.8V (1.7–1.95V)
Note: 1. Pb-free package.
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Features
Contents
General Description ......................................................................................................................................... 9
Asynchronous and Synchronous Signal Descriptions ......................................................................................... 9
Signal Assignments ......................................................................................................................................... 11
Package Dimensions ...................................................................................................................................... 14
Architecture ................................................................................................................................................... 19
Device and Array Organization ....................................................................................................................... 20
Bus Operation – Asynchronous Interface ........................................................................................................ 27
Asynchronous Enable/Standby ................................................................................................................... 27
Asynchronous Bus Idle ............................................................................................................................... 27
Asynchronous Commands .......................................................................................................................... 28
Asynchronous Addresses ............................................................................................................................ 29
Asynchronous Data Input ........................................................................................................................... 30
Asynchronous Data Output ........................................................................................................................ 31
Write Protect .............................................................................................................................................. 32
Ready/Busy# .............................................................................................................................................. 32
Bus Operation – Synchronous Interface ........................................................................................................... 37
Synchronous Enable/Standby ..................................................................................................................... 38
Synchronous Bus Idle/Driving .................................................................................................................... 38
Synchronous Commands ........................................................................................................................... 39
Synchronous Addresses .............................................................................................................................. 40
Synchronous DDR Data Input ..................................................................................................................... 41
Synchronous DDR Data Output .................................................................................................................. 42
Write Protect .............................................................................................................................................. 44
Ready/Busy# .............................................................................................................................................. 44
Device Initialization ....................................................................................................................................... 45
Activating Interfaces ....................................................................................................................................... 46
Activating the Asynchronous Interface ........................................................................................................ 46
Activating the Synchronous Interface .......................................................................................................... 46
Command Definitions .................................................................................................................................... 48
Reset Operations ............................................................................................................................................ 50
RESET (FFh) ............................................................................................................................................... 50
SYNCHRONOUS RESET (FCh) .................................................................................................................... 51
RESET LUN (FAh) ....................................................................................................................................... 52
Identification Operations ................................................................................................................................ 53
READ ID (90h) ............................................................................................................................................ 53
READ ID Parameter Tables ......................................................................................................................... 54
READ PARAMETER PAGE (ECh) .................................................................................................................. 55
Parameter Page Data Structure Tables ..................................................................................................... 56
READ UNIQUE ID (EDh) ............................................................................................................................ 67
Configuration Operations ............................................................................................................................... 68
SET FEATURES (EFh) ................................................................................................................................. 68
GET FEATURES (EEh) ................................................................................................................................. 69
Status Operations ........................................................................................................................................... 73
READ STATUS (70h) ................................................................................................................................... 74
READ STATUS ENHANCED (78h) ............................................................................................................... 75
Column Address Operations ........................................................................................................................... 76
CHANGE READ COLUMN (05h-E0h) .......................................................................................................... 76
CHANGE READ COLUMN ENHANCED (06h-E0h) ....................................................................................... 77
CHANGE WRITE COLUMN (85h) ................................................................................................................ 78
CHANGE ROW ADDRESS (85h) ................................................................................................................... 79
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Features
Read Operations ............................................................................................................................................. 81

READ MODE (00h) ..................................................................................................................................... 83
READ PAGE (00h-30h) ................................................................................................................................ 84
READ PAGE CACHE SEQUENTIAL (31h) ..................................................................................................... 85
READ PAGE CACHE RANDOM (00h-31h) .................................................................................................... 86
READ PAGE CACHE LAST (3Fh) .................................................................................................................. 88
READ PAGE MULTI-PLANE (00h-32h) ........................................................................................................ 89
Program Operations ....................................................................................................................................... 91
PROGRAM PAGE (80h-10h) ........................................................................................................................ 91
PROGRAM PAGE CACHE (80h-15h) ............................................................................................................ 93
PROGRAM PAGE MULTI-PLANE (80h-11h) ................................................................................................. 95
Erase Operations ............................................................................................................................................ 97
ERASE BLOCK (60h-D0h) ............................................................................................................................ 97
ERASE BLOCK MULTI-PLANE (60h-D1h) .................................................................................................... 98
Copyback Operations ..................................................................................................................................... 99
COPYBACK READ (00h-35h) ...................................................................................................................... 100
COPYBACK PROGRAM (85h–10h) .............................................................................................................. 101
COPYBACK READ MULTI-PLANE (00h-32h) .............................................................................................. 101
COPYBACK PROGRAM MULTI-PLANE (85h-11h) ....................................................................................... 102
One-Time Programmable (OTP) Operations ................................................................................................... 103
PROGRAM OTP PAGE (80h-10h) ................................................................................................................ 104
PROTECT OTP AREA (80h-10h) .................................................................................................................. 105
READ OTP PAGE (00h-30h) ........................................................................................................................ 106
Multi-Plane Operations ................................................................................................................................. 107
Multi-Plane Addressing ............................................................................................................................. 107
Interleaved Die (Multi-LUN) Operations ........................................................................................................ 108
Error Management ........................................................................................................................................ 109
Shared Pages ................................................................................................................................................. 110
Output Drive Impedance ............................................................................................................................... 112
AC Overshoot/Undershoot Specifications ...................................................................................................... 115
Synchronous Input Slew Rate ........................................................................................................................ 116
Output Slew Rate ........................................................................................................................................... 117
Electrical Specifications ................................................................................................................................. 118
Electrical Specifications – DC Characteristics and Operating Conditions (Asynchronous) ................................. 120
Electrical Specifications – DC Characteristics and Operating Conditions (Synchronous) .................................. 121
Electrical Specifications – DC Characteristics and Operating Conditions (VCCQ) ............................................... 121
Electrical Specifications – AC Characteristics and Operating Conditions (Asynchronous) ................................. 122
Electrical Specifications – AC Characteristics and Operating Conditions (Synchronous) ................................... 124
Electrical Specifications – Array Characteristics .............................................................................................. 127
Asynchronous Interface Timing Diagrams ...................................................................................................... 128
Synchronous Interface Timing Diagrams ........................................................................................................ 139
Revision History ............................................................................................................................................ 161
Rev. E Production – 3/11 ............................................................................................................................ 161
Rev. D Production – 12/10 ......................................................................................................................... 161
Rev. C – 7/10 ............................................................................................................................................. 161
Rev. B – 2/10 ............................................................................................................................................. 161
Rev. A – 11/09 ............................................................................................................................................ 161
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Features
List of Tables
Table 1: Asynchronous and Synchronous Signal Definitions ............................................................................. 9
Table 2: Array Addressing for Logical Unit (LUN) ............................................................................................ 26
Table 3: Asynchronous Interface Mode Selection ........................................................................................... 27
Table 4: Synchronous Interface Mode Selection ............................................................................................. 37
Table 5: Command Set .................................................................................................................................. 48
Table 6: Read ID Parameters for Address 00h ................................................................................................. 54
Table 7: Read ID Parameters for Address 20h .................................................................................................. 54
Table 8: Parameter Page Data Structure ......................................................................................................... 56
Table 9: Feature Address Definitions .............................................................................................................. 68
Table 10: Feature Address 01h: Timing Mode ................................................................................................. 70
Table 11: Feature Addresses 10h and 80h: Programmable Output Drive Strength ............................................. 71
Table 12: Feature Addresses 81h: Programmable R/B# Pull-Down Strength ..................................................... 71
Table 13: Feature Addresses 90h: Array Operation Mode ................................................................................. 72
Table 14: Status Register Definition ............................................................................................................... 73
Table 15: OTP Area Details ........................................................................................................................... 104
Table 16: Error Management Details ............................................................................................................. 109
Table 17: Shared Pages ................................................................................................................................. 110
Table 18: Output Drive Strength Test Conditions (VCCQ = 1.7–1.95V) .............................................................. 112
Table 19: Output Drive Strength Impedance Values (VCCQ = 1.7–1.95V) .......................................................... 112
Table 20: Output Drive Strength Conditions (VCCQ = 2.7–3.6V) ....................................................................... 113
Table 21: Output Drive Strength Impedance Values (VCCQ = 2.7–3.6V) ............................................................ 113
Table 22: Pull-Up and Pull-Down Output Impedance Mismatch .................................................................... 114
Table 23: Overshoot/Undershoot Parameters ................................................................................................ 115
Table 24: Test Conditions for Input Slew Rate ................................................................................................ 116
Table 25: Input Slew Rate (VCCQ = 1.7–1.95V) ................................................................................................. 116
Table 26: Input Slew Rate (VCCQ= 2.7–3.6V) ................................................................................................... 116
Table 27: Test Conditions for Output Slew Rate ............................................................................................. 117
Table 28: Output Slew Rate (VCCQ = 1.7–1.95V) .............................................................................................. 117
Table 29: Output Slew Rate (VCCQ = 2.7–3.6V) ................................................................................................ 117
Table 30: Absolute Maximum Ratings by Device ............................................................................................ 118
Table 31: Recommended Operating Conditions ............................................................................................ 118
Table 32: Valid Blocks per LUN ..................................................................................................................... 118
Table 33: Capacitance: 100-Ball BGA Package ................................................................................................ 119
Table 34: Capacitance: 48-Pin TSOP Package ................................................................................................ 119
Table 35: Capacitance: 52-Pad LGA Package .................................................................................................. 119
Table 36: Test Conditions ............................................................................................................................. 120
Table 37: DC Characteristics and Operating Conditions (Asynchronous Interface) .......................................... 120
Table 38: DC Characteristics and Operating Conditions (Synchronous Interface) ........................................... 121
Table 39: DC Characteristics and Operating Conditions (3.3V VCCQ) ............................................................... 121
Table 40: DC Characteristics and Operating Conditions (1.8V VCCQ) ............................................................... 122
Table 41: AC Characteristics: Asynchronous Command, Address, and Data .................................................... 122
Table 42: AC Characteristics: Synchronous Command, Address, and Data ...................................................... 124
Table 43: Array Characteristics ..................................................................................................................... 127
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Features
List of Figures
Figure 1: Part Numbering ................................................................................................................................ 2
Figure 2: 48-Pin TSOP Type 1 (Top View) ....................................................................................................... 11
Figure 3: 52-Pad LGA (Top View) ................................................................................................................... 12
Figure 4: 100-Ball BGA (Ball-Down, Top View) ................................................................................................ 13
Figure 5: 48-Pin TSOP – Type 1 CPL (Package Code: WP) ................................................................................ 14
Figure 6: 52-Pad VLGA .................................................................................................................................. 15
Figure 7: 100-Ball VBGA – 12mm x 18mm (Package Code: H1) ......................................................................... 16
Figure 8: 100-Ball TBGA – 12mm x 18mm (Package Code: H2) ......................................................................... 17
Figure 9: 100-Ball LBGA – 12mm x 18mm (Package Code: H3) ......................................................................... 18
Figure 10: NAND Flash Die (LUN) Functional Block Diagram ......................................................................... 19
Figure 11: Device Organization for Single-Die Package (TSOP/BGA) ............................................................... 20
Figure 12: Device Organization for Two-Die Package (TSOP) .......................................................................... 20
Figure 13: Device Organization for Two-Die Package (BGA/LGA) .................................................................... 21
Figure 14: Device Organization for Four-Die Package (TSOP) .......................................................................... 22
Figure 15: Device Organization for Four-Die Package with CE# and CE2# (BGA/LGA) ...................................... 23
Figure 16: Device Organization for Four-Die Package with CE#, CE2#, CE3#, and CE4# (BGA/LGA) .................. 24
Figure 17: Device Organization for Eight-Die Package (BGA/LGA) ................................................................... 25
Figure 18: Array Organization per Logical Unit (LUN) ..................................................................................... 26
Figure 19: Asynchronous Command Latch Cycle ............................................................................................ 28
Figure 20: Asynchronous Address Latch Cycle ................................................................................................ 29
Figure 21: Asynchronous Data Input Cycles ................................................................................................... 30
Figure 22: Asynchronous Data Output Cycles ................................................................................................. 31
Figure 23: Asynchronous Data Output Cycles (EDO Mode) ............................................................................. 32
Figure 24: READ/BUSY# Open Drain ............................................................................................................. 33
Figure 25: tFall and tRise (VCCQ = 2.7-3.6V) ...................................................................................................... 34
Figure 26: tFall and tRise (VCCQ = 1.7-1.95V) .................................................................................................... 34
Figure 27: IOL vs Rp (VCCQ = 2.7-3.6V) ............................................................................................................ 35
Figure 28: IOL vs Rp (VCCQ = 1.7-1.95V) .......................................................................................................... 35
Figure 29: TC vs Rp ........................................................................................................................................ 36
Figure 30: Synchronous Bus Idle/Driving Behavior ......................................................................................... 39
Figure 31: Synchronous Command Cycle ....................................................................................................... 40
Figure 32: Synchronous Address Cycle ........................................................................................................... 41
Figure 33: Synchronous DDR Data Input Cycles ............................................................................................. 42
Figure 34: Synchronous DDR Data Output Cycles ........................................................................................... 44
Figure 35: R/B# Power-On Behavior ............................................................................................................... 45
Figure 36: Activating the Synchronous Interface ............................................................................................. 47
Figure 37: RESET (FFh) Operation ................................................................................................................. 50
Figure 38: SYNCHRONOUS RESET (FCh) Operation ....................................................................................... 51
Figure 39: RESET LUN (FAh) Operation ......................................................................................................... 52
Figure 40: READ ID (90h) with 00h Address Operation .................................................................................... 53
Figure 41: READ ID (90h) with 20h Address Operation .................................................................................... 53
Figure 42: READ PARAMETER (ECh) Operation .............................................................................................. 55
Figure 43: READ UNIQUE ID (EDh) Operation ............................................................................................... 67
Figure 44: SET FEATURES (EFh) Operation .................................................................................................... 69
Figure 45: GET FEATURES (EEh) Operation ................................................................................................... 69
Figure 46: READ STATUS (70h) Operation ...................................................................................................... 75
Figure 47: READ STATUS ENHANCED (78h) Operation .................................................................................. 75
Figure 48: CHANGE READ COLUMN (05h-E0h) Operation ............................................................................. 76
Figure 49: CHANGE READ COLUMN ENHANCED (06h-E0h) Operation ......................................................... 77
Figure 50: CHANGE WRITE COLUMN (85h) Operation ................................................................................... 78
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Features
Figure 51: CHANGE ROW ADDRESS (85h) Operation ..................................................................................... 80

Figure 52: READ PAGE (00h-30h) Operation ................................................................................................... 84
Figure 53: READ PAGE CACHE SEQUENTIAL (31h) Operation ........................................................................ 85
Figure 54: READ PAGE CACHE RANDOM (00h-31h) Operation ....................................................................... 87
Figure 55: READ PAGE CACHE LAST (3Fh) Operation ..................................................................................... 88
Figure 56: READ PAGE MULTI-PLANE (00h-32h) Operation ........................................................................... 90
Figure 57: PROGRAM PAGE (80h-10h) Operation ........................................................................................... 92
Figure 58: PROGRAM PAGE CACHE (80h–15h) Operation (Start) .................................................................... 94
Figure 59: PROGRAM PAGE CACHE (80h–15h) Operation (End) ..................................................................... 94
Figure 60: PROGRAM PAGE MULTI-PLANE (80h–11h) Operation ................................................................... 96
Figure 61: ERASE BLOCK (60h-D0h) Operation .............................................................................................. 97
Figure 62: ERASE BLOCK MULTI-PLANE (60h–D1h) Operation ...................................................................... 98
Figure 63: COPYBACK READ (00h-35h) Operation ......................................................................................... 100
Figure 64: COPYBACK READ (00h–35h) with CHANGE READ COLUMN (05h–E0h) Operation ......................... 100
Figure 65: COPYBACK PROGRAM (85h–10h) Operation ................................................................................. 101
Figure 66: COPYBACK PROGRAM (85h-10h) with CHANGE WRITE COLUMN (85h) Operation ....................... 101
Figure 67: COPYBACK PROGRAM MULTI-PLANE (85h-11h) Operation .......................................................... 102
Figure 68: PROGRAM OTP PAGE (80h-10h) Operation ................................................................................... 104
Figure 69: PROGRAM OTP PAGE (80h-10h) with CHANGE WRITE COLUMN (85h) Operation ......................... 105
Figure 70: PROTECT OTP AREA (80h-10h) Operation .................................................................................... 106
Figure 71: READ OTP PAGE (00h-30h) Operation .......................................................................................... 106
Figure 72: Overshoot .................................................................................................................................... 115
Figure 73: Undershoot ................................................................................................................................. 115
Figure 74: RESET Operation ......................................................................................................................... 128
Figure 75: RESET LUN Operation .................................................................................................................. 128
Figure 76: READ STATUS Cycle ..................................................................................................................... 129
Figure 77: READ STATUS ENHANCED Cycle ................................................................................................. 129
Figure 78: READ PARAMETER PAGE ............................................................................................................. 130
Figure 79: READ PAGE ................................................................................................................................. 130
Figure 80: READ PAGE Operation with CE# “Don’t Care” ............................................................................... 131
Figure 81: CHANGE READ COLUMN ............................................................................................................ 132
Figure 82: READ PAGE CACHE SEQUENTIAL ................................................................................................ 133
Figure 83: READ PAGE CACHE RANDOM ..................................................................................................... 134
Figure 84: READ ID Operation ...................................................................................................................... 135
Figure 85: PROGRAM PAGE Operation .......................................................................................................... 135
Figure 86: PROGRAM PAGE Operation with CE# “Don’t Care” ....................................................................... 136
Figure 87: PROGRAM PAGE Operation with CHANGE WRITE COLUMN ........................................................ 136
Figure 88: PROGRAM PAGE CACHE .............................................................................................................. 137
Figure 89: PROGRAM PAGE CACHE Ending on 15h ....................................................................................... 137
Figure 90: COPYBACK .................................................................................................................................. 138
Figure 91: ERASE BLOCK Operation .............................................................................................................. 138
Figure 92: SET FEATURES Operation ............................................................................................................ 139
Figure 93: READ ID Operation ...................................................................................................................... 140
Figure 94: GET FEATURES Operation ........................................................................................................... 141
Figure 95: RESET (FCh) Operation ................................................................................................................ 142
Figure 96: READ STATUS Cycle ..................................................................................................................... 143
Figure 97: READ STATUS ENHANCED Operation .......................................................................................... 144
Figure 98: READ PARAMETER PAGE Operation ............................................................................................. 145
Figure 99: READ PAGE Operation ................................................................................................................. 146
Figure 100: CHANGE READ COLUMN .......................................................................................................... 147
Figure 101: READ PAGE CACHE SEQUENTIAL (1 of 2) ................................................................................... 148
Figure 102: READ PAGE CACHE SEQUENTIAL (2 of 2) ................................................................................... 149
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Features
Figure 103: READ PAGE CACHE RANDOM (1 of 2) ......................................................................................... 150

Figure 104: READ PAGE CACHE RANDOM (2 of 2) ......................................................................................... 150
Figure 105: Multi-Plane Read Page (1 of 2) ..................................................................................................... 151
Figure 106: Multi-Plane Read Page (2 of 2) ..................................................................................................... 152
Figure 107: PROGRAM PAGE Operation (1 of 2) ............................................................................................. 153
Figure 108: PROGRAM PAGE Operation (2 of 2) ............................................................................................. 153
Figure 109: CHANGE WRITE COLUMN ......................................................................................................... 154
Figure 110: Multi-Plane Program Page .......................................................................................................... 155
Figure 111: ERASE BLOCK ............................................................................................................................ 156
Figure 112: COPYBACK (1 of 3) ..................................................................................................................... 156
Figure 115: READ OTP PAGE ........................................................................................................................ 158
Figure 116: PROGRAM OTP PAGE (1 of 2) ...................................................................................................... 159
Figure 117: PROGRAM OTP PAGE (2 of 2) ...................................................................................................... 159
Figure 118: PROTECT OTP AREA .................................................................................................................. 160
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General Description
General Description
Micron NAND Flash devices include an asynchronous data interface for high-perform-
ance I/O operations. These devices use a highly multiplexed 8-bit bus (DQx) to transfer
commands, address, and data. There are five control signals used to implement the asyn-
chronous data interface: CE#, CLE, ALE, WE#, and RE#. Additional signals control
hardware write protection (WP#) and monitor device status (R/B#).
This Micron NAND Flash device additionally includes a synchronous data interface for
high-performance I/O operations. When the synchronous interface is active, WE# be-
comes CLK and RE# becomes W/R#. Data transfers include a bidirectional data strobe
(DQS).
This hardware interface creates a low pin-count device with a standard pinout that re-
mains the same from one density to another, enabling future upgrades to higher densi-
ties with no board redesign.
A target is the unit of memory accessed by a chip enable signal. A target contains one or
more NAND Flash die. A NAND Flash die is the minimum unit that can independently
execute commands and report status. A NAND Flash die, in the ONFI specification, is
referred to as a logical unit (LUN). For further details, see Device and Array Organization.
Asynchronous and Synchronous Signal Descriptions
Table 1: Asynchronous and Synchronous Signal Definitions
Asynchronous Synchronous
Signal1 Signal1 Type Description2
ALE ALE Input Address latch enable: Loads an address from DQx into the address reg-
ister.
CE# CE# Input Chip enable: Enables or disables one or more die (LUNs) in a target1.
CLE CLE Input Command latch enable: Loads a command from DQx into the com-
mand register.
DQx DQx I/O Data inputs/outputs: The bidirectional I/Os transfer address, data, and
command information.
– DQS I/O Data strobe: Provides a synchronous reference for data input and out-
put.
RE# W/R# Input Read enable and write/read: RE# transfers serial data from the NAND
Flash to the host system when the asynchronous interface is active.
When the synchronous interface is active, W/R# controls the direction of
DQx and DQS.
WE# CLK Input Write enable and clock: WE# transfers commands, addresses, and seri-
al data from the host system to the NAND Flash when the asynchronous
interface is active. When the synchronous interface is active, CLK latches
command and address cycles.
WP# WP# Input Write protect: Enables or disables array PROGRAM and ERASE opera-
tions.
R/B# R/B# Output Ready/busy: An open-drain, active-low output that requires an exter-
nal pull-up resistor. This signal indicates target array activity.
VCC VCC Supply VCC: Core power supply
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Asynchronous and Synchronous Signal Descriptions
Table 1: Asynchronous and Synchronous Signal Definitions (Continued)
Asynchronous Synchronous
Signal1 Signal1 Type Description2
VCCQ VCCQ Supply VCCQ: I/O power supply
VSS VSS Supply VSS: Core ground connection
VSSQ VSSQ Supply VSSQ: I/O ground connection
NC NC – No connect: NCs are not internally connected. They can be driven or
left unconnected.
DNU DNU – Do not use: DNUs must be left unconnected.
RFU RFU – Reserved for future use: RFUs must be left unconnected.
Notes: 1. See Device and Array Organization for detailed signal connections.
2. See Bus Operation – Asynchronous Interface (page 27) and Bus Operation – Synchro-
nous Interface (page 37) for detailed asynchronous and synchronous interface signal
descriptions.
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Signal Assignments
Signal Assignments
Figure 2: 48-Pin TSOP Type 1 (Top View)
Sync Async Async Sync
x8 x8 x8 x8
NC NC 1l 48 DNU/VSSQ2 DNU/VSSQ2
NC NC 2 47 NC NC
NC NC 3 46 NC NC
NC NC 4 45 NC NC
NC NC 5 44 DQ7 DQ7
R/B2#1 R/B2#1 6 43 DQ6 DQ6
R/B# R/B# 7 42 DQ5 DQ5
W/R# RE# 8 41 DQ4 DQ4
CE# CE# 9 40 NC NC
CE2#1 CE2#1 10 39 DNU/VCCQ2 DNU/VCCQ2
NC NC 11 38 DNU DNU
VCC VCC 12 37 VCC VCC
VSS VSS 13 36 VSS VSS
NC NC 14 35 DNU DQS
NC NC 15 34 DNU/VCCQ2 DNU/VCCQ2
CLE CLE 16 33 NC NC
ALE ALE 17 32 DQ3 DQ3
CLK WE# 18 31 DQ2 DQ2
WP# WP# 19 30 DQ1 DQ1
NC NC 20 29 DQ0 DQ0
NC NC 21 28 NC NC
NC NC 22 27 NC NC
NC NC 23 26 DNU DNU
NC NC 24 25 DNU/VSSQ2 DNU/VSSQ2
Notes: 1. CE2# and R/B2# are available on dual die and quad die packages. They are NC for other
configurations.
2. These VCCQ and VSSQ pins are for compatibility with ONFI 2.2. If not supplying VCCQ or
VSSQ to these pins, do not use them.
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Signal Assignments
Figure 3: 52-Pad LGA (Top View)

0 1 2 3 4 5 6 7 8
NC
OA CE4#2 R/B4#2
A CE3#2 CLE-1 CE# R/B3#2
B VSS VCC
OB NC NC
C ALE-1 CLE-21 CE2#1 RE#-1
D ALE-21 RE#-21
OC DNU DNU
E WE#-21 WE#-1 R/B# R/B2#1
F WP#-1 VSS
G DQ0-21 DQ0-1 WP#-21 DQ7-21
H DQ1-1 DQ7-1
J DQ1-21 DQ2-1 DQ6-1 DQ6-21

OD DNU/ DNU
VSS
K DQ3-1 DQ5-1
L DQ2-21 VSS DQ4-1 DQ5-21

DNU/
OE NC
VSS
M VSS VCC
N DNU/ DQ3-21 DQ4-21 DNU/

VCC VCC
OF NC NC
Top View, Pads Down
Notes: 1. These signals are available on dual, quad, and octal die packages. They are NC for other
configurations.
2. These signals are available on quad die four CE# or octal die packages. They are NC for
other configurations.
PDF: 09005aef83d2277a

Signal Assignments
Figure 4: 100-Ball BGA (Ball-Down, Top View)

1 2 3 4 5 6 7 8 9 10
A NC NC NC NC A
B NC NC B
D RFU DNU NC WP#-23 NC NC DNU RFU D
E RFU DNU NC WP#-1 NC NC DNU RFU E
F VCC VCC VCC VCC VCC VCC VCC VCC F
G VSS VSS VSS VSS VSS VSS VSS VSS G
H Vssq Vccq RFU RFU R/B2#3 R/B4#4 Vccq Vssq H
J DQ0-23 DQ2-23 ALE-23 CE4#4 R/B# R/B3#4 DQ5-23 DQ7-23 J
K DQ0-1 DQ2-1 ALE-1 CE3#4 CE2#3 CE# DQ5-1 DQ7-1 K
L Vccq Vssq Vccq CLE-23 RE#-23 Vccq Vssq Vccq L

(W/R#-2)
M DQ1-23 DQ3-23 Vssq CLE-1 RE#-1 Vssq DQ4-23 DQ6-23 M

(W/R#-1)
N DQ1-1 DQ3-1 RFU N/A1 RFU WE#-23 DQ4-1 DQ6-1 N

(DQS-23) (CLK-2)
P Vssq RFU N/A1 RFU WE#-1 Vccq Vssq

P
Vccq
(DQS-1) (CLK-1)
T NC NC T
U NC NC NC NC U
1 2 3 4 5 6 7 8 9 10
Notes: 1. N/A: This signal is tri-stated when the asynchronous interface is active.
2. Signal names in parentheses are the signal names when the synchronous interface is active.
3. These signals are available on dual, quad, and octal die packages. They are NC for other
configurations.
4. These signals are available on quad die four CE# or octal die packages. They are NC for
other configurations.
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Package Dimensions
Package Dimensions
Figure 5: 48-Pin TSOP – Type 1 CPL (Package Code: WP)
0.25 Mold compound:

20.00 ±0.25 for reference only Epoxy novolac
0.50 TYP Plated lead finish:
18.40 ±0.08 for reference 100% Sn
48 only
1
Package width and length
do not include mold
protrusion. Allowable
protrusion is 0.25 per side.
12.00 ±0.08
0.27 MAX
0.17 MIN
24 25
0.25
0.10 Gage
+0.03 plane
0.15 See detail A
-0.02
1.20 MAX +0.10
0.10
-0.05
0.50 ±0.1
0.80
Detail A
Note: 1. All dimensions are in millimeters.
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Package Dimensions
Figure 6: 52-Pad VLGA
Seating
plane
A
0.1 A See Note 1
See Detail B
Section A–A Detail B2
Not to scale
40X Ø0.71 6 CTR Substrate material: plastic laminate.

Mold compound: epoxy novolac.
4 CTR
Terminal
12X Ø11
8 7 6 5 4 3 2 1 0
A1 ID Terminal A1 ID
OA
A
B
OB
C
D
OC
E
F
13 12 10 A A
G 18 ±0.1
CTR CTR CTR
H
2
J
TYP OD
K
L
OE
M
2
N TYP
OF
2 TYP 1.0 MAX

including package bow.
10 CTR
Bottom side saw fiducials may or
14 ±0.1 may not be covered with soldermask.
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Package Dimensions
Figure 7: 100-Ball VBGA – 12mm x 18mm (Package Code: H1)
Seating
plane
A 0.63 ±0.05
0.12 A
100X Ø0.45
Solder ball material: 12 ±0.1
SAC305 (96.5% Sn,
3% Ag, 0.5% Cu).
Dimensions apply to Ball A1 ID Ball A1 ID
10 9 8 7 6 5 4 3 2 1
solder balls post-reflow
on Ø0.4 SMD ball pads.
A
E
8
7 F
16 CTR J 18 ±0.1
K
N
1 TYP
P
1 TYP 1.0 MAX

1 TYP Bottom side 0.25 MIN
saw fiducials
9 CTR may or may not
be covered with soldermask.
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Package Dimensions
Figure 8: 100-Ball TBGA – 12mm x 18mm (Package Code: H2)
Seating
plane
A 0.73 ±0.05
0.12 A
100X Ø0.45
Solder ball material:
SAC305 (96.5% Sn, 12 ±0.1
3% Ag, 0.5% Cu).
Dimensions apply to Ball A1 ID Ball A1 ID
solder balls post-reflow 10 9 8 7 6 5 4 3 2 1
on Ø0.4 SMD ball pads.
A
E
8
7 F
16 CTR J 18 ±0.1
K
N
1 TYP
P
Bottom side 1 TYP 1.2 MAX

fiducials may 0.25 MIN
1 TYP
or may not be
covered with 9 CTR
soldermask.
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Package Dimensions
Figure 9: 100-Ball LBGA – 12mm x 18mm (Package Code: H3)
Seating
plane
A 0.98 ±0.05
0.12 A
100X Ø0.45
Solder ball material:
SAC305 (96.5% Sn,
12 ±0.1
3% Ag, 0.5% Cu).
Dimensions apply to
solder balls post- Ball A1 ID Ball A1 ID
10 9 8 7 6 5 4 3 2 1
reflow on Ø0.40 SMD
ball pads.
A
16 CTR 10 CTR J 18 ±0.1

K
T
1 TYP
U
1 TYP 1.4 MAX

9 CTR Bottom side 0.25 MIN
saw fiducials
may or may not
be covered with soldermask.
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Architecture
Architecture
These devices use NAND Flash electrical and command interfaces. Data, commands,
and addresses are multiplexed onto the same pins and received by I/O control circuits.
The commands received at the I/O control circuits are latched by a command register
and are transferred to control logic circuits for generating internal signals to control de-
vice operations. The addresses are latched by an address register and sent to a row
decoder to select a row address, or to a column decoder to select a column address.
Data is transferred to or from the NAND Flash memory array, byte by byte, through a
data register and a cache register.
The NAND Flash memory array is programmed and read using page-based operations
and is erased using block-based operations. During normal page operations, the data
and cache registers act as a single register. During cache operations, the data and cache
registers operate independently to increase data throughput.
The status register reports the status of die (LUN) operations.
Figure 10: NAND Flash Die (LUN) Functional Block Diagram
Vcc Vss Vccq Vssq
Async Sync
DQ[7:0] DQ[7:0] I/O Address register

control
N/A DQS
Status register
Command register
CE# CE#
CLE CLE Column decode
Column Decode
ALE ALE Control

Decode
RowDecode
WE# CLK logic

NANDFlash
NAND Flash
RE# W/R#
array Array
(2 planes)
WP# WP#
Row
R/B# R/B# Data register

Data Register
Cache register
Cache Register
Notes: 1. N/A: This signal is tri-stated when the asynchronous interface is active.
2. Some devices do not include the synchronous interface.
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Device and Array Organization

Figure 11: Device Organization for Single-Die Package (TSOP/BGA)
Package
Async Sync
CE# CE# Target 1
CLE CLE LUN 1
ALE ALE R/B#
WE# CLK
RE# W/R#
DQ[7:0] DQ[7:0]
N/A DQS
WP# WP#
Figure 12: Device Organization for Two-Die Package (TSOP)
Async Sync Package
CE# CE# Target 1

CLE CLE LUN 1
ALE ALE R/B#
WE# CLK
RE# W/R#
DQ[7:0] DQ[7:0]
N/A DQS
WP# WP#
CE2# CE2# Target 2

CLE CLE LUN 1
ALE ALE R/B2#
WE# CLK
RE# W/R#
DQ[7:0] DQ[7:0]
N/A DQS
WP# WP#
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Figure 13: Device Organization for Two-Die Package (BGA/LGA)
Async Sync Package
CE# CE# Target 1

CLE-1 CLE-1 LUN 1
ALE-1 ALE-1 R/B#
WE#-1 CLK-1
RE#-1 W/R#-1
DQ[7:0]-1 DQ[7:0]-1
N/A DQS-1
WP#-1 WP#-1
CE2# CE2# Target 2

CLE-2 CLE-2 LUN 1
ALE-2 ALE-2 R/B2#
WE#-2 CLK-2
RE#-2 W/R#-2
DQ[7:0]-2 DQ[7:0]-2
N/A DQS-2
WP#-2 WP#-2
Note: 1. LGA devices do not support the synchronous interface.
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Figure 14: Device Organization for Four-Die Package (TSOP)
Async Sync Package
CE# CE# Target 1

CLE CLE LUN 1 LUN 2
ALE ALE R/B#
WE# CLK
RE# W/R#
DQ[7:0] DQ[7:0]
N/A DQS
WP# WP#
CE2# CE2# Target 2

CLE CLE LUN 1 LUN 2
ALE ALE R/B2#
WE# CLK
RE# W/R#
DQ[7:0] DQ[7:0]
N/A DQS
WP# WP#
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Figure 15: Device Organization for Four-Die Package with CE# and CE2# (BGA/LGA)
Package
Async Sync
CE# CE# Target 1
CLE-1 CLE-1 LUN 1 LUN 2
ALE-1 ALE-1 R/B#
WE#-1 CLK-1
RE#-1 W/R#-1
DQ[7:0]-1 DQ[7:0]-1
N/A DQS-1
WP#-1 WP#-1
CE2# CE2# Target 2

ALE-2 ALE-2 R/B2#
WE#-2 CLK-2
RE#-2 W/R#-2
DQ[7:0]-2 DQ[7:0]-2
N/A DQS-2
WP#-2 WP#-2
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Figure 16: Device Organization for Four-Die Package with CE#, CE2#, CE3#, and CE4# (BGA/LGA)
Package
Async Sync
CE# CE# Target 1
CLE-1 CLE-1 LUN 1

ALE-1 ALE-1 R/B#
WE#-1 CLK-1
RE#-1 W/R#-1
DQ[7:0]-1 DQ[7:0]-1
N/A DQS-1
WP#-1 WP#-1
CE2# CE2# Target 2
CLE-2 CLE-2 LUN 1

ALE-2 ALE-2 R/B2#
WE#-2 CLK-2
RE#-2 W/R#-2
DQ[7:0]-2 DQ[7:0]-2
N/A DQS-2
WP#-2 WP#-2
CE3# CE3# Target 3
CLE-1 CLE-1 LUN 1

ALE-1 ALE-1 R/B3#
WE#-1 CLK-1
RE#-1 W/R#-1
DQ[7:0]-1 DQ[7:0]-1
N/A DQS-1
WP#-1 WP#-1
CE4# CE4# Target 4
CLE-2 CLE-2 LUN 1

ALE-2 ALE-2 R/B4#
WE#-2 CLK-2
RE#-2 W/R#-2
DQ[7:0]-2 DQ[7:0]-2
N/A DQS-2
WP#-2 WP#-2
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Figure 17: Device Organization for Eight-Die Package (BGA/LGA)
Package
Async Sync
CE# CE# Target 1

ALE-1 ALE-1 R/B#
WE#-1 CLK-1
RE#-1 W/R#-1
DQ[7:0]-1 DQ[7:0]-1
N/A DQS-1
WP#-1 WP#-1
CE2# CE2# Target 2

ALE-2 ALE-2 R/B2#
WE#-2 CLK-2
RE#-2 W/R#-2
DQ[7:0]-2 DQ[7:0]-2
N/A DQS-2
WP#-2 WP#-2
CE3# CE3# Target 3

ALE-1 ALE-1 R/B3#
WE#-1 CLK-1
RE#-1 W/R#-1
DQ[7:0]-1 DQ[7:0]-1
N/A DQS-1
WP#-1 WP#-1
CE4# CE4# Target 4

ALE-2 ALE-2 R/B4#
WE#-2 CLK-2
RE#-2 W/R#-2
DQ[7:0]-2 DQ[7:0]-2
N/A DQS-2
WP#-2 WP#-2
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Figure 18: Array Organization per Logical Unit (LUN)
Logical Unit (LUN)
8640 bytes 8640 bytes

DQ7
Cache Registers 8192 448 8192 448 DQ0
Data Registers 8192 448 8192 448
1 page = (8K + 448 bytes)
2048 blocks per plane 1 block = (8K + 448) bytes x 256 pages
= (2048K + 112K) bytes
1 Block 1 Block 1 Block
4096 blocks per LUN
1 plane = (2048K + 112K) bytes x 2048 blocks
= 34,560Mb
1 LUN = 34,560Mb x 2 planes

= 69,120Mb
Plane 0 Plane 1
(0, 2, 4, ..., 4094) (1, 3, 5, ..., 4095)
Table 2: Array Addressing for Logical Unit (LUN)
Cycle DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0

First CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA02
Second LOW LOW CA133 CA12 CA11 CA10 CA9 CA8
Third PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0
Fourth BA15 BA14 BA13 BA12 BA11 BA10 BA9 BA84
Fifth LOW LOW LOW LA05 BA19 BA18 BA17 BA16
Notes: 1. CAx = column address, PAx = page address, BAx = block address, LAx = LUN address; the
page address, block address, and LUN address are collectively called the row address.
2. When using the synchronous interface, CA0 is forced to 0 internally; one data cycle al-
ways returns one even byte and one odd byte.
3. Column addresses 8640 (21C0h) through 16,383 (3FFFh) are invalid, out of bounds, do
not exist in the device, and cannot be addressed.
4. BA[8] is the plane-select bit:
Plane 0: BA[8] = 0
Plane 1: BA[8] = 1
5. LA0 is the LUN-select bit. It is present only when two LUNs are shared on the target;
otherwise, it should be held LOW.
LUN 0: LA0 = 0
LUN 1: LA0 = 1
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Bus Operation – Asynchronous Interface

The asynchronous interface is active when the NAND Flash device powers on. The I/O
bus, DQ[7:0], is multiplexed sharing data I/O, addresses, and commands. The DQS sig-
nal, if present, is tri-stated when the asynchronous interface is active.
Asynchronous interface bus modes are summarized below.
Table 3: Asynchronous Interface Mode Selection
Mode CE# CLE ALE WE# RE# DQS DQx WP# Notes
Standby H X X X X X X 0V/VCCQ 2 2
Bus idle L X X H H X X X
Command input L H L H X input H
Address input L L H H X input H
Data input L L L H X input H
Data output L L L H X output X
Write protect X X X X X X X L
Notes: 1. DQS is tri-stated when the asynchronous interface is active.

2. WP# should be biased to CMOS LOW or HIGH for standby.
3. Mode selection settings for this table: H = Logic level HIGH; L = Logic level LOW; X = VIH
or VIL.
Asynchronous Enable/Standby
A chip enable (CE#) signal is used to enable or disable a target. When CE# is driven
LOW, all of the signals for that target are enabled. With CE# LOW, the target can accept
commands, addresses, and data I/O. There may be more than one target in a NAND
Flash package. Each target is controlled by its own chip enable; the first target (Target 0)
is controlled by CE#; the second target (if present) is controlled by CE2#, etc.
A target is disabled when CE# is driven HIGH, even when the target is busy. When disa-
bled, all of the target's signals are disabled except CE#, WP#, and R/B#. This functionali-
ty is also known as CE# "Don't Care". While the target is disabled, other devices can
utilize the disabled NAND signals that are shared with the NAND Flash.
A target enters low-power standby when it is disabled and is not busy. If the target is
busy when it is disabled, the target enters standby after all of the die (LUNs) complete
their operations. Standby helps reduce power consumption.
Asynchronous Bus Idle

A target's bus is idle when CE# is LOW, WE# is HIGH, and RE# is HIGH.
During bus idle, all of the signals are enabled except DQS, which is not used when the
asynchronous interface is active. No commands, addresses, and data are latched into
the target; no data is output.
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Asynchronous Commands
An asynchronous command is written from DQ[7:0] to the command register on the
rising edge of WE# when CE# is LOW, ALE is LOW, CLE is HIGH, and RE# is HIGH.
Commands are typically ignored by die (LUNs) that are busy (RDY = 0); however, some
commands, including READ STATUS (70h) and READ STATUS ENHANCED (78h), are
accepted by die (LUNs) even when they are busy.
Figure 19: Asynchronous Command Latch Cycle
CLE
tCLS tCLH
tCS tCH
CE#
tWP
WE#
tALS tALH
ALE
tDS tDH
DQx COMMAND
Don’t Care
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Asynchronous Addresses
An asynchronous address is written from DQ[7:0] to the address register on the rising
edge of WE# when CE# is LOW, ALE is HIGH, CLE is LOW, and RE# is HIGH.
Bits that are not part of the address space must be LOW (see Device and Array Organiza-
tion). The number of cycles required for each command varies. Refer to the command
descriptions to determine addressing requirements (see Command Definitions).
Addresses are typically ignored by die (LUNs) that are busy (RDY = 0); however, some
addresses are accepted by die (LUNs) even when they are busy; for example, address
cycles that follow the READ STATUS ENHANCED (78h) command.
Figure 20: Asynchronous Address Latch Cycle
CLE
tCLS
tCS
CE#
tWC
tWP tWH
WE#
tALS
tALH
ALE
tDS tDH
DQx Col Col Row Row Row

add 1 add 2 add 1 add 2 add 3
Don’t Care Undefined
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Asynchronous Data Input

Data is written from DQ[7:0] to the cache register of the selected die (LUN) on the rising
edge of WE# when CE# is LOW, ALE is LOW, CLE is LOW, and RE# is HIGH.
Data input is ignored by die (LUNs) that are not selected or are busy (RDY = 0).
Figure 21: Asynchronous Data Input Cycles
CLE
tCLH
CE#
tALS tCH
ALE
tWC
tWP tWP tWP
WE#
tWH
tDS tDH tDS tDH tDS tDH
DQx DIN M DIN M+1 DIN N
Don’t Care
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Asynchronous Data Output

Data can be output from a die (LUN) if it is in a READY state. Data output is supported
following a READ operation from the NAND Flash array. Data is output from the cache
register of the selected die (LUN) to DQ[7:0] on the falling edge of RE# when CE# is
LOW, ALE is LOW, CLE is LOW, and WE# is HIGH.
If the host controller is using a tRC of 30ns or greater, the host can latch the data on the
rising edge of RE# (see Figure 22 for proper timing). If the host controller is using a tRC
of less than 30ns, the host can latch the data on the next falling edge of RE# (see Fig-
ure 23 (page 32) for extended data output (EDO) timing).
Using the READ STATUS ENHANCED (78h) command prevents data contention follow-
ing an interleaved die (multi-LUN) operation. After issuing the READ STATUS EN-
HANCED (78h) command, to enable data output, issue the READ MODE (00h) command.
Data output requests are typically ignored by a die (LUN) that is busy (RDY = 0); howev-
er, it is possible to output data from the status register even when a die (LUN) is busy by
first issuing the READ STATUS (70h) or READ STATUS ENHANCED (78h) command.
Figure 22: Asynchronous Data Output Cycles
tCEA
CE#
tCHZ
tREA tREA tREA
tRP tREH tCOH
RE#
tRHZ tRHZ
tRHOH
DQx DOUT DOUT DOUT
tRR tRC
RDY
Don’t Care
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Figure 23: Asynchronous Data Output Cycles (EDO Mode)
CE#
tRC tCHZ
tRP tREH tCOH
RE#
tREA tREA tRHZ
tCEA tRLOH tRHOH
DQx DOUT DOUT DOUT
tRR
RDY
Don’t Care
Write Protect
The write protect# (WP#) signal enables or disables PROGRAM and ERASE operations
to a target. When WP# is LOW, PROGRAM and ERASE operations are disabled. When
WP# is HIGH, PROGRAM and ERASE operations are enabled.
It is recommended that the host drive WP# LOW during power-on until Vcc and Vccq
are stable to prevent inadvertent PROGRAM and ERASE operations (see Device Initiali-
zation (page 45) for additional details).
WP# must be transitioned only when the target is not busy and prior to beginning a
command sequence. After a command sequence is complete and the target is ready,
WP# can be transitioned. After WP# is transitioned, the host must wait tWW before issu-
ing a new command.
The WP# signal is always an active input, even when CE# is HIGH. This signal should
not be multiplexed with other signals.
Ready/Busy#
The ready/busy# (R/B#) signal provides a hardware method of indicating whether a tar-
get is ready or busy. A target is busy when one or more of its die (LUNs) are busy
(RDY = 0). A target is ready when all of its die (LUNs) are ready (RDY = 1). Because each
die (LUN) contains a status register, it is possible to determine the independent status
of each die (LUN) by polling its status register instead of using the R/B# signal (see Sta-
tus Operations for details regarding die (LUN) status).
This signal requires a pull-up resistor, Rp, for proper operation. R/B# is HIGH when the
target is ready, and transitions LOW when the target is busy. The signal's open-drain
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driver enables multiple R/B# outputs to be OR-tied. Typically, R/B# is connected to an

interrupt pin on the system controller (see Figure 24 (page 33)).
The combination of Rp and capacitive loading of the R/B# circuit determines the rise
time of the R/B# signal. The actual value used for Rp depends on the system timing re-
quirements. Large values of Rp cause R/B# to be delayed significantly. Between the 10-
to 90-percent points on the R/B# waveform, the rise time is approximately two time
constants (TC).
TC = R × C
Where R = Rp (resistance of pull-up resistor), and C = total capacitive load.
The fall time of the R/B# signal is determined mainly by the output impedance of the
R/B# signal and the total load capacitance. Approximate Rp values using a circuit load
of 100pF are provided in Figure 29 (page 36).
The minimum value for Rp is determined by the output drive capability of the R/B#
signal, the output voltage swing, and Vccq.
Vcc (MAX) - Vol (MAX)

Rp =
IOL + Σil
Where Σil is the sum of the input currents of all devices tied to the R/B# pin.
Figure 24: READ/BUSY# Open Drain

VCCQ
Rp
VCC
To controller
R/B#
Open drain output
IOL
VSS
Device
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Figure 25: tFall and tRise (VCCQ = 2.7-3.6V)

3.50
3.00
2.50 tFall tRise

2.00
V
1.50
1.00
0.50
0.00
–1 0 2 4 0 2 4 6
TC VCCQ 3.3V
Notes: 1. tFALL is VOH(DC) to VOL(AC) and tRISE is VOL(DC) to VOH(AC).

2. tRise dependent on external capacitance and resistive loading and output transistor im-
pedance.
3. tRise primarily dependent on external pull-up resistor and external capacitive loading.
4. tFall = 10ns at 3.3V
5. See TC values in Figure 29 (page 36) for approximate Rp value and TC.
Figure 26: tFall and tRise (VCCQ = 1.7-1.95V)

3.50
3.00
2.50
tFall tRise
2.00
V
1.50
1.00
0.50
0.00
-1 0 2 4 0 2 4 6
TC VCCQ 1.8V
1. tFALL is VOH(DC) to VOL(AC) and tRISE is VOL(DC) to VOH(AC).

Notes:
2. tRise is primarily dependent on external pull-up resistor and external capacitive loading.
3. tFall ≈ 7ns at 1.8V.
4. See TC values in Figure 29 (page 36) for TC and approximate Rp value.
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Figure 27: IOL vs Rp (VCCQ = 2.7-3.6V)

3.50
3.00
2.50
2.00
I (mA)
1.50
1.00
0.50
0.00
0 2000 400 0 6000 8000 10,000 12,000
Rp (Ω)
IOL at Vccq (MAX)
Figure 28: IOL vs Rp (VCCQ = 1.7-1.95V)

3.50
3.00
2.50
2.00
I (mA)
1.50
1.00
0.50
0.00
0 2000 4000 6000 8000 10,000 12,000
Rp (Ω)
IOL at Vccq (MAX)
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Figure 29: TC vs Rp
1200
1000
800
T(ns)
600
400
200
0
0 2000 4000 6000 8000 10,000 12,000
Rp (Ω) Iol at VCCQ (MAX)
RC = TC
C = 100pF
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Bus Operation – Synchronous Interface

These NAND Flash devices have two interfaces—a synchronous interface for fast data
I/O transfer and an asynchronous interface that is backward compatible with existing
NAND Flash devices.
The NAND Flash command protocol for both the asynchronous and synchronous inter-
faces is identical. However, there are some differences between the asynchronous and
synchronous interfaces when issuing command, address, and data I/O cycles using the
NAND Flash signals.
When the synchronous interface is activated on a target (see Activating Interfaces), the
target is capable of high-speed DDR data transfers. Existing signals are redefined for high-
speed DDR I/O. The WE# signal becomes CLK. DQS is enabled. The RE# signal becomes
W/R#. CLK provides a clock reference to the NAND Flash device.
DQS is a bidirectional data strobe. During data output, DQS is driven by the NAND
Flash device. During data input, DQS is controlled by the host controller while input-
ting data on DQ[7:0].
The direction of DQS and DQ[7:0] is controlled by the W/R# signal. When the W/R# sig-
nal is latched HIGH, the controller is driving the DQ bus and DQS. When the W/R# is
latched LOW, the NAND Flash is driving the DQ bus and DQS.
The synchronous interface bus modes are summarized below.
Table 4: Synchronous Interface Mode Selection
Mode CE# CLE ALE CLK W/R# DQS DQ[7:0] WP# Notes
Standby H X X X X X X 0V/VCCQ 1, 2
Bus idle L L L H X X X
Bus driv- L L L L output output X

ing
Command L H L H X input H 3
input
Address L L H H X input H 3
input
Data input L H H H input H 4
Data out- L H H L See Note 5 output X 5

put
Write pro- X X X X X X X L
tect
Undefined L L H L output output X
Undefined L H L L output output X
Notes: 1. CLK can be stopped when the target is disabled, even when R/B# is LOW.
2. WP# should be biased to CMOS LOW or HIGH for standby.
3. Commands and addresses are latched on the rising edge of CLK.
4. During data input to the device, DQS is the “clock” that latches the data in the cache
register.
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5. During data output from the NAND Flash device, DQS is an output generated from CLK
after tDQSCK delay.
6. Mode selection settings for this table: H = Logic level HIGH; L = Logic level LOW; X = VIH
or VIL.
Synchronous Enable/Standby
In addition to the description found in Asynchronous Enable/Standby (page 27), the
following requirements also apply when the synchronous interface is active.
Before enabling a target, CLK must be running and ALE and CLE must be LOW. When
CE# is driven LOW, all of the signals for the selected target are enabled. The target is not
enabled until tCS completes; the target's bus is then idle.
Prior to disabling a target, the target's bus must be idle. A target is disabled when CE# is
driven HIGH, even when it is busy. All of the target's signals are disabled except CE#,
WP#, and R/B#. After the target is disabled, CLK can be stopped.
A target enters low-power standby when it is disabled and is not busy. If the target is
busy when it is disabled, the target enters standby after all of the die (LUNs) complete
their operations.
Synchronous Bus Idle/Driving

A target's bus is idle or driving when CLK is running, CE# is LOW, ALE is LOW, and CLE
is LOW.
The bus is idle when W/R# transitions HIGH and is latched by CLK. During the bus idle
mode, all signals are enabled; DQS and DQ[7:0] are inputs. No commands, addresses,
or data are latched into the target; no data is output. When entering the bus idle mode,
the host must wait a minimum of tCAD before changing the bus mode. In the bus idle
mode, the only valid bus modes supported are: bus driving, command, address, and
DDR data input.
The bus is driving when W/R# transitions LOW and is latched by CLK. During the bus
driving mode, all signals are enabled; DQS is LOW and DQ[7:0] is driven LOW or HIGH,
but no valid data is output. Following the bus driving mode, the only valid bus modes
supported are bus idle and DDR data output.
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Figure 30: Synchronous Bus Idle/Driving Behavior
CE#
CLE
ALE
CLK
tCALS tCALS
W/R#
tDQSD tDQSHZ
DQS
DQ[7:0]
Bus idle Bus driving Bus idle
Undefined (driven by NAND)
Note: 1. Only the selected die (LUN) drives DQS and DQ[7:0]. During an interleaved die (multi-
LUN) operation, the host must use the READ STATUS ENHANCED (78h) to prevent data
output contention.
Synchronous Commands
A command is written from DQ[7:0] to the command register on the rising edge of CLK
when CE# is LOW, ALE is LOW, CLE is HIGH, and W/R# is HIGH.
After a command is latched—and prior to issuing the next command, address, or
data I/O—the bus must go to bus idle mode on the next rising edge of CLK, except
when the clock period, tCK, is greater than tCAD.
Commands are typically ignored by die (LUNs) that are busy (RDY = 0); however, some
commands, such as READ STATUS (70h) and READ STATUS ENHANCED (78h), are ac-
cepted by die (LUNs), even when they are busy.
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Figure 31: Synchronous Command Cycle

tCS tCH
CE#
tCALS tCALS tCALH

CLE
tCALS tCALH
tCALS tCAD tCALH

ALE
tCKL tCKH
CLK
tCK
tCAD starts here1
W/R#
tCALS tCALH
tDQSHZ
DQS
tCAS tCAH
DQ[7:0] Command
Undefined Don’t Care
Note: 1. When CE# remains LOW, tCAD begins at the rising edge of the clock from which the
command cycle is latched for subsequent command, address, data input, or data output
cycle(s).
Synchronous Addresses
A synchronous address is written from DQ[7:0] to the address register on the rising edge
of CLK when CE# is LOW, ALE is HIGH, CLE is LOW, and W/R# is HIGH.
After an address is latched—and prior to issuing the next command, address, or data I/O
—the bus must go to bus idle mode on the next rising edge of CLK, except when the
clock period, tCK, is greater than tCAD.
Bits not part of the address space must be LOW (see Device and Array Organization).
The number of address cycles required for each command varies. Refer to the com-
mand descriptions to determine addressing requirements.
Addresses are typically ignored by die (LUNs) that are busy (RDY = 0); however, some
addresses such as address cycles that follow the READ STATUS ENHANCED (78h) com-
mand, are accepted by die (LUNs), even when they are busy.
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Figure 32: Synchronous Address Cycle

tCS tCH
CE#
tCALS tCALH
CLE
tCALS tCAD tCALS tCALH
ALE
tCALS tCALH
tCKL tCKH
CLK
tCK tCAD starts here1
W/R#
tCALS tDQSHZ tCALH
DQS
tCAS tCAH
DQ[7:0] Address
Undefined Don’t Care
Note: 1. When CE# remains LOW, tCAD begins at the rising edge of the clock from which the
command cycle is latched for subsequent command, address, data input, or data output
cycle(s).
Synchronous DDR Data Input

To enter the DDR data input mode, the following conditions must be met:
• CLK is running
• CE# is LOW
• W/R# is HIGH
tCAD is met
•
• DQS is LOW
• ALE and CLE are HIGH on the rising edge of CLK
Upon entering the DDR data input mode after tDQSS, data is written from DQ[7:0] to
the cache register on each and every rising and falling edge of DQS (center-aligned)
when CLK is running and the DQS to CLK skew meets tDSH and tDSS, CE# is LOW,
W/R# is HIGH, and ALE and CLE are HIGH on the rising edge of CLK.
To exit DDR data input mode, the following conditions must be met:
• CLK is running and the DQS to CLK skew meets tDSH and tDSS
• CE# is LOW
• W/R# is HIGH
• ALE and CLE are latched LOW on the rising edge of CLK
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• The final two data bytes of the data input sequence are written to DQ[7:0] to the
cache register on the rising and falling edges of DQS after the last cycle in the data
input sequence in which ALE and CLE are latched HIGH.
• DQS is held LOW for tWPST (after the final falling edge of DQS)
Following tWPST, the bus enters bus idle mode and tCAD begins on the next rising edge
of CLK. After tCAD starts, the host can disable the target if desired.
Data input is ignored by die (LUNs) that are not selected or are busy.
Figure 33: Synchronous DDR Data Input Cycles
tCS tCH
CE#
tCALS tCALS tCALH
CLE
tCALS tCALH
tCALS tCAD tCALS
tCALH
ALE
tCKL tCKH tCALS tCALH
CLK
tCK tCAD
starts
here1
W/R#
tDQSS tDSH tDSS tDSH tDSH tDSS tDSH tDSS
DQS
tWPRE tDQSH tDQSL tDQSH tDQSL tDQSH tWPST
DQ[7:0] D0 D1 D2 D3 DN-2 DN-1 DN

tDS tDS
tDH tDH
Don’t Care
Notes: 1. When CE# remains LOW, tCAD begins at the first rising edge of the clock after tWPST
completes.
2. tDSH (MIN) generally occurs during tDQSS (MIN).
3. tDSS (MIN) generally occurs during tDQSS (MAX).
Synchronous DDR Data Output

Data can be output from a die (LUN) if it is ready. Data output is supported following a
READ operation from the NAND Flash array.
To enter the DDR data output mode, the following conditions must be met:
• CLK is running
• CE# is LOW
• The host has released the DQ[7:0] bus and DQS
• W/R# is latched LOW on the rising edge of CLK to enable the selected die (LUN) to
take ownership of the DQ[7:0] bus and DQS within tWRCK
• tCAD is met
• ALE and CLE are HIGH on the rising edge of CLK
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Upon entering the DDR data output mode, DQS will toggle HIGH and LOW with a delay
of tDQSCK from the respective rising and falling edges of CLK. DQ[7:0] will output data
edge-aligned to the rising and falling edges of DQS, with the first transition delayed by
no more than tAC.
DDR data output mode continues as long as CLK is running, CE# is LOW, W/R# is LOW,
and ALE and CLE are HIGH on the rising edge of CLK.
To exit DDR data output mode, the following conditions must be met:
• CLK is running
• CE# is LOW
• W/R# is LOW
• ALE and CLE are latched LOW on the rising edge of CLK
The final two data bytes are output on DQ[7:0] on the final rising and falling edges of
DQS. The final rising and falling edges of DQS occur tDQSCK after the last cycle in the
data output sequence in which ALE and CLE are latched HIGH. After tCKWR, the bus
enters bus idle mode and tCAD begins on the next rising edge of CLK. Once tCAD starts
the host can disable the target if desired.
Data output requests are typically ignored by a die (LUN) that is busy (RDY = 0); howev-
er, it is possible to output data from the status register even when a die (LUN) is busy by
issuing the READ STATUS (70h) or READ STATUS ENHANCED (78h) command.
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Figure 34: Synchronous DDR Data Output Cycles
tCS tCH
CE#
tCALS tCALS tCALH
CLE
tCALS tCALH
tCALS tCAD tCALS tCALH
ALE
tCALS tCALH
tCKL tCKH
CLK tHP tHP tHP tHP tHP tHP
tCK tDQSCK tCKWR

tCAD starts
tDQSCK tDQSCK here1
tDQSCK tDQSCK
tCALS tWRCK tDQSCK
W/R#
tDQSD tCALS tDQSHZ
DQS
tAC tDVW tDVW tDVW tDVW tDVW
DQ[7:0] D0 D1 D2 DN-2 DN-1 DN
tDQSQ tDQSQ tDQSQ tDQSQ

tQH tQH tQH tQH
Undefined (driven by NAND) Don’t Care Data Transitioning
Notes: 1. When CE# remains LOW, tCAD begins at the rising edge of the clock after tCKWR for
subsequent command or data output cycle(s).
2. See Figure 31 (page 40) for details of W/R# behavior.
3. tAC is the DQ output window relative to CLK and is the long-term component of DQ skew.
4. For W/R# transitioning HIGH, DQ[7:0] and DQS go to tri-state.
5. For W/R# transitioning LOW, DQ[7:0] drives current state and DQS goes LOW.
6. After final data output, DQ[7:0] is driven until W/R# goes HIGH, but is not valid.
Write Protect
See Write Protect (page 32).
Ready/Busy#
See Ready/Busy# (page 32).
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Device Initialization
Device Initialization
Some NAND Flash devices do not support VCCQ. For these devices all references to VCCQ
are replaced with VCC.
Micron NAND Flash devices are designed to prevent data corruption during power tran-
sitions. VCC is internally monitored. (The WP# signal supports additional hardware
protection during power transitions.) When ramping VCC and VCCQ, use the following
procedure to initialize the device:
1. Ramp VCC.
2. Ramp VCCQ. VCCQ must not exceed VCC.
3. The host must wait for R/B# to be valid and HIGH before issuing RESET (FFh) to
any target (see Figure 35). The R/B# signal becomes valid when 50µs has elapsed
since the beginning the VCC ramp, and 10µs has elapsed since VCCQ reaches VCCQ
(MIN) and VCC reaches VCC (MIN).
4. If not monitoring R/B#, the host must wait at least 100µs after VCCQ reaches VCCQ
(MIN) and VCC reaches VCC (MIN). If monitoring
R/B#, the host must wait until R/B# is HIGH.
5. The asynchronous interface is active by default for each target. Each LUN draws
less than an average of 10mA (IST) measured over intervals of 1ms until the RESET
(FFh) command is issued.
6. The RESET (FFh) command must be the first command issued to all targets (CE#s)
after the NAND Flash device is powered on. Each target will be busy for tPOR after
a RESET command is issued. The RESET busy time can be monitored by polling
R/B# or issuing the READ STATUS (70h) command to poll the status register.
7. The device is now initialized and ready for normal operation.
At power-down, VCCQ must go LOW, either before, or simultaneously with, VCC going
LOW.
Figure 35: R/B# Power-On Behavior
50µs (MIN)
Vccq = Vccq (MIN)

Vccq
10µs
(MAX)
Vcc = Vcc (MIN)
Vcc
> 0µs
R/B#
Vcc ramp 100µs (MAX) Reset (FFh)

starts is issued
Invalid
Note: 1. Disregard VCCQ for devices that use only VCC.
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Activating Interfaces
After performing the steps under Device Initialization (page 45), the asynchronous inter-
face is active for all targets on the device.
Each target's interface is independent of other targets, so the host is responsible for
changing the interface for each target.
If the host and NAND Flash device, through error, are no longer using the same inter-
face, then steps under Activating the Asynchronous Interface are performed to re-
synchronize the interfaces.
Activating the Asynchronous Interface

To activate the asynchronous NAND interface, once the synchronous interface is active,
the following steps are repeated for each target:
1. The host pulls CE# HIGH, disables its input to CLK, and enables its asynchronous
interface.
2. The host pulls CE# LOW and issues the RESET (FFh) command, using an asynchro-
nous command cycle.
3. R/B# goes LOW for tRST.
4. After tITC, and during tRST, the device enters the asynchronous NAND interface.
READ STATUS (70h) and READ STATUS ENHANCED (78h) are the only com-
mands that can be issued.
5. After tRST, R/B# goes HIGH. Timing mode feature address (01h), subfeature param-
eter P1 is set to 00h, indicating that the asynchronous NAND interface is active
and that the device is set to timing mode 0.
For further details, see Reset Operations.
Activating the Synchronous Interface

To activate the synchronous NAND Flash interface, the following steps are repeated for
each target:
1. Issue the SET FEATURES (EFh) command.
2. Write address 01h, which selects the timing mode.
3. Write P1 with 1Xh, where "X" is the timing mode used in the synchronous inter-
face (see Configuration Operations).
4. Write P2–P4 as 00h-00h-00h.
5. R/B# goes LOW for tITC. The host should pull CE# HIGH. During tITC, the host
should not issue any type of command, including status commands, to the NAND
Flash device.
6. After tITC, R/B# goes HIGH and the synchronous interface is enabled. Before pull-
ing CE# LOW, the host should enable the clock.
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Figure 36: Activating the Synchronous Interface
CE# may CE# may

transition HIGH transition LOW
A B C
Cycle type CMD ADDR DIN DIN DIN DIN

tADL
DQ[7:0] EFh 01h TM P2 P3 P4

tWB tITC
R/B#
tCAD 100ns
Note: 1. TM = Timing mode.
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Command Definitions
Command Definitions
Table 5: Command Set
Number of
Valid Data Valid While Valid While
Command Address Input Command Selected LUN Other LUNs
Command Cycle #1 Cycles Cycles Cycle #2 is Busy1 are Busy2 Notes
Reset Operations
RESET FFh 0 – – Yes Yes
SYNCHRONOUS RESET FCh 0 – – Yes Yes
RESET LUN FAh 3 – – Yes Yes
Identification Operations
READ ID 90h 1 – – 3
READ PARAMETER PAGE ECh 1 – –
READ UNIQUE ID EDh 1 – –
Configuration Operations
GET FEATURES EEh 1 – – 3
SET FEATURES EFh 1 4 – 4
Status Operations
READ STATUS 70h 0 – – Yes
READ STATUS ENHANCED 78h 3 – – Yes Yes
Column Address Operations
CHANGE READ COLUMN 05h 2 – E0h Yes
CHANGE READ COLUMN 06h 5 – E0h Yes
ENHANCED
CHANGE WRITE COLUMN 85h 2 Optional – Yes
CHANGE ROW ADDRESS 85h 5 Optional – Yes 5
Read Operations
READ MODE 00h 0 – – Yes
READ PAGE 00h 5 – 30h Yes 6
READ PAGE MULTI- 00h 5 – 32h Yes
PLANE
READ PAGE CACHE 31h 0 – – Yes 7
SEQUENTIAL
READ PAGE CACHE 00h 5 – 31h Yes 6,7
RANDOM
READ PAGE CACHE LAST 3Fh 0 – – Yes 7
Program Operations
PROGRAM PAGE 80h 5 Yes 10h Yes
PROGRAM PAGE 80h 5 Yes 11h Yes
MULTI-PLANE
PROGRAM PAGE CACHE 80h 5 Yes 15h Yes 8
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Command Definitions
Table 5: Command Set (Continued)
Number of
Valid Data Valid While Valid While
Command Address Input Command Selected LUN Other LUNs
Command Cycle #1 Cycles Cycles Cycle #2 is Busy1 are Busy2 Notes
Erase Operations
ERASE BLOCK 60h 3 – D0h Yes
ERASE BLOCK 60h 3 – D1h Yes
MULTI-PLANE
Copyback Operations
COPYBACK READ 00h 5 – 35h Yes 6
COPYBACK PROGRAM 85h 5 Optional 10h Yes
COPYBACK PROGRAM 85h 5 Optional 11h Yes
MULTI-PLANE
Notes: 1. Busy means RDY = 0.

2. These commands can be used for interleaved die (multi-LUN) operations (see Interleaved
Die (Multi-LUN) Operations (page 108)).
3. The READ ID (90h) and GET FEATURES (EEh) output identical data on rising and falling
DQS edges.
4. The SET FEATURES (EFh) command requires data transition prior to the rising edge of
CLK, with identical data for the rising and falling edges.
5. Command cycle #2 of 11h is conditional. See CHANGE ROW ADDRESS (85h) for more de-
tails.
6. This command can be preceded by up to one READ PAGE MULTI-PLANE (00h-32h) com-
mand to accommodate a maximum simultaneous two-plane array operation.
7. Issuing a READ PAGE CACHE-series (31h, 00h-31h, 00h-32h, 3Fh) command when the ar-
ray is busy (RDY = 1, ARDY = 0) is supported if the previous command was a READ PAGE
(00h-30h) or READ PAGE CACHE-series command; otherwise, it is prohibited.
8. Issuing a PROGRAM PAGE CACHE (80h-15h) command when the array is busy (RDY = 1,
ARDY = 0) is supported if the previous command was a PROGRAM PAGE CACHE
(80h-15h) command; otherwise, it is prohibited.
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Reset Operations
Reset Operations
RESET (FFh)
The RESET (FFh) command is used to put a target into a known condition and to abort
command sequences in progress. This command is accepted by all die (LUNs), even
when they are busy.
When FFh is written to the command register, the target goes busy for tRST. During
tRST, the selected target (CE#) discontinues all array operations on all die (LUNs). All
pending single- and multi-plane operations are cancelled. If this command is issued
while a PROGRAM or ERASE operation is occurring on one or more die (LUNs), the data
may be partially programmed or erased and is invalid. The command register is cleared
and ready for the next command. The data register and cache register contents are invalid.
RESET must be issued as the first command to each target following power-up (see De-
vice Initialization (page 45)). Use of the READ STATUS ENHANCED (78h) command is
prohibited during the power-on RESET. To determine when the target is ready, use
READ STATUS (70h).
If the RESET (FFh) command is issued when the synchronous interface is enabled, the
target's interface is changed to the asynchronous interface and the timing mode is set
to 0. The RESET (FFh) command can be issued asynchronously when the synchronous
interface is active, meaning that CLK does not need to be continuously running when
CE# is transitioned LOW and FFh is latched on the rising edge of CLK. After this com-
mand is latched, the host should not issue any commands during tITC. After tITC, and
during or after tRST, the host can poll each LUN's status register.
If the RESET (FFh) command is issued when the asynchronous interface is active, the
target's asynchronous timing mode remains unchanged. During or after tRST, the host
can poll each LUN's status register.
Figure 37: RESET (FFh) Operation
Cycle type Command
DQ[7:0] FFh
tWB tRST
R/B#
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Reset Operations
SYNCHRONOUS RESET (FCh)

When the synchronous interface is active, the SYNCHRONOUS RESET (FCh) command
is used to put a target into a known condition and to abort command sequences in pro-
gress. This command is accepted by all die (LUNs), even when they are BUSY.
When FCh is written to the command register, the target goes busy for tRST. During
tRST, the selected target (CE#) discontinues all array operations on all die (LUNs). All
pending single- and multi-plane operations are cancelled. If this command is issued
while a PROGRAM or ERASE operation is occurring on one or more die (LUNs), the data
may be partially programmed or erased and is invalid. The command register is cleared
and ready for the next command. The data register and cache register contents are inva-
lid and the synchronous interface remains active.
During or after tRST, the host can poll each LUN's status register.
SYNCHRONOUS RESET is only accepted while the synchronous interface is active. Its
use is prohibited when the asynchronous interface is active.
Figure 38: SYNCHRONOUS RESET (FCh) Operation
Cycle type Command
DQ[7:0] FCh
tWB tRST
R/B#
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Reset Operations
RESET LUN (FAh)

The RESET LUN (FAh) command is used to put a particular LUN on a target into a
known condition and to abort command sequences in progress. This command is ac-
cepted by only the LUN addressed by the RESET LUN (FAh) command, even when that
LUN is busy.
When FAh is written to the command register, the addressed LUN goes busy for tRST.
During tRST, the selected LUN discontinues all array operations. All pending single-
and multi-plane operations are canceled. If this command is issued while a PROGRAM
or ERASE operation is occurring on the addressed LUN, the data may be partially pro-
grammed or erased and is invalid. The command register is cleared and ready for the
next command. The data register and cache register contents are invalid.
If the RESET LUN (FAh) command is issued when the synchronous interface is enabled,
the targets's interface remains in synchronous mode.
If the RESET LUN (FAh) command is issued when the asynchronous interface is ena-
bled, the target's interface remains in asynchronous mode.
During or after tRST, the host can poll each LUN's status register.
The RESET LUN (FAh) command is prohibited when not in the default array operation
mode.
The RESET LUN (FAh) command can only be issued to a target (CE#) after the RESET
(FFh) command has been issued as the first command to a target following power-up.
Figure 39: RESET LUN (FAh) Operation
Cycle type Command Address Address Address
DQ[7:0] FAh R1 R2 R3
tWB tRST
R/B#
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READ ID (90h)
The READ ID (90h) command is used to read identifier codes programmed into the tar-
get. This command is accepted by the target only when all die (LUNs) on the target are
idle.
Writing 90h to the command register puts the target in read ID mode. The target stays
in this mode until another valid command is issued.
When the 90h command is followed by a 00h address cycle, the target returns a 5-byte
identifier code that includes the manufacturer ID, device configuration, and part-specif-
ic information.
When the 90h command is followed by a 20h address cycle, the target returns the 4-byte
ONFI identifier code.
After the 90h and address cycle are written to the target, the host enables data output
mode to read the identifier information. When the asynchronous interface is active, one
data byte is output per RE# toggle. When the synchronous interface is active, one data
byte is output per rising edge of DQS when ALE and CLE are HIGH; the data byte on the
falling edge of DQS is identical to the data byte output on the previous rising edge of DQS.
Figure 40: READ ID (90h) with 00h Address Operation
Cycle type Command Address DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT
tWHR
DQ[7:0] 90h 00h Byte 0 Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 Byte 7
Note: 1. See the READ ID Parameter tables for byte definitions.
Figure 41: READ ID (90h) with 20h Address Operation
Cycle type Command Address DOUT DOUT DOUT DOUT

tWHR
DQ[7:0] 90h 20h 4Fh 4Eh 46h 49h
Note: 1. See the READ ID Parameter tables for byte definitions.
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READ ID Parameter Tables
Table 6: Read ID Parameters for Address 00h
Device Byte 0 Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 Byte 7

MT29F64G08CBAAA 2Ch 88h 04h 4Bh A9h 00h 00h 00h
MT29F64G08CBAAB 2Ch 88h 04h 4Bh A9h 00h 00h 00h
MT29F64G08CBCAB 2Ch 88h 04h 4Bh A9h 00h 00h 00h
MT29F128G08CEAAA 2Ch 88h 04h 4Bh A9h 00h 00h 00h
MT29F128G08CECAB 2Ch 88h 04h 4Bh A9h 00h 00h 00h
MT29F128G08CFAAA 2Ch 88h 04h 4Bh A9h 00h 00h 00h
MT29F128G08CFAAB 2Ch 88h 04h 4Bh A9h 00h 00h 00h
MT29F256G08CJAAA 2Ch A8h 05h CBh A9h 00h 00h 00h
MT29F256G08CJAAB 2Ch A8h 05h CBh A9h 00h 00h 00h
MT29F256G08CKAAA 2Ch A8h 05h CBh A9h 00h 00h 00h
MT29F256G08CKCAB 2Ch A8h 05h CBh A9h 00h 00h 00h
MT29F256G08CMAAA 2Ch 88h 04h 4Bh A9h 00h 00h 00h
MT29F256G08CMCAB 2Ch 88h 04h 4Bh A9h 00h 00h 00h
MT29F512G08CUAAA 2Ch A8h 05h CBh A9h 00h 00h 00h
MT29F512G08CUCAB 2Ch A8h 05h CBh A9h 00h 00h 00h
Note: 1. h = hexadecimal.
Table 7: Read ID Parameters for Address 20h
Device Byte 0 Byte 1 Byte 2 Byte 3 Byte 4

All 4Fh 4Eh 46h 49h XXh
Notes: 1. h = hexadecimal.
2. XXh = Undefined.
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READ PARAMETER PAGE (ECh)

The READ PARAMETER PAGE (ECh) command is used to read the ONFI parameter
page programmed into the target. This command is accepted by the target only when
all die (LUNs) on the target are idle.
Writing ECh to the command register puts the target in read parameter page mode. The
target stays in this mode until another valid command is issued.
When the ECh command is followed by an 00h address cycle, the target goes busy for
tR. If the READ STATUS (70h) command is used to monitor for command completion,
the READ MODE (00h) command must be used to re-enable data output mode. Use of
the READ STATUS ENHANCED (78h) command is prohibited while the target is busy
and during data output.
After tR completes, the host enables data output mode to read the parameter page.
When the asynchronous interface is active, one data byte is output per RE# toggle.
When the synchronous interface is active, one data byte is output for each rising or fall-
ing edge of DQS.
A minimum of three copies of the parameter page are stored in the device. Each param-
eter page is 256 bytes. If desired, the CHANGE READ COLUMN (05h-E0h) command
can be used to change the location of data output. Use of the CHANGE READ COLUMN
ENHANCED (06h-E0h) command is prohibited.
The READ PARAMETER PAGE (ECh) output data can be used by the host to configure
its internal settings to properly use the NAND Flash device. Parameter page data is stat-
ic per part, however the value can be changed through the product cycle of NAND
Flash. The host should interpret the data and configure itself accordingly.
Figure 42: READ PARAMETER (ECh) Operation
Cycle type Command Address DOUT DOUT DOUT DOUT DOUT DOUT
DQ[7:0] ECh 00h P00 P10 … P01 P11 …

tWB tR tRR
R/B#
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Parameter Page Data Structure Tables
Table 8: Parameter Page Data Structure
Byte Description Device Values

Revision information and features block
0–3 Parameter page signature – 4Fh, 4Eh, 46h, 49h
Byte 0: 4Fh, “O”
Byte 1: 4Eh, “N”
Byte 2: 46h, “F”
Byte 3: 49h, “I”
4–5 Revision number – 1Eh, 00h
Bit[15:5]: Reserved (0)
Bit 4: 1 = supports ONFI version 2.2
Bit 3: 1 = supports ONFI verion 2.1
Bit 0: Reserved (0)
6–7 Features supported MT29F64G08CBAAA D8h, 01h
Bit[15:9]: Reserved (0) MT29F128G08CEAAA
Bit 8: 1 = supports program page register clear enhance-
MT29F128G08CFAAA
ment
Bit 7: 1 = supports extended parameter page MT29F256G08CMAAA
Bit 6: 1 = supports interleaved (multi-plane) read opera- MT29F256G08CJAAA DAh, 01h
tions MT29F256G08CKAAA
Bit 5: 1 = supports synchronous interface
MT29F512G08CUAAA
Bit 4: 1 = supports odd-to-even page copyback
Bit 3: 1 = supports interleaved (multi-plane) program MT29F64G08CBAAB F8h, 01h
and erase operations MT29F64G08CBCAB
Bit 2: 1 = supports non-sequential page programming MT29F128G08CECAB
Bit 1: 1 = supports multiple LUN operations
MT29F128G08CFAAB
Bit 0: 1 = supports 16-bit data bus width
MT29F256G08CMCAB
MT29F256G08CJAAB FAh, 01h
MT29F256G08CKCAB
MT29F512G08CUCAB
8–9 Optional commands supported – FFh, 03h
Bit 9: 1 = supports Reset LUN command
Bit 8: 1 = supports small data move
Bit 7: 1 = supports CHANGE ROW ADDRESS
Bit 6: 1 = supports CHANGE READ COLUMN ENHANCED
Bit 5: 1 = supports READ UNIQUE ID
Bit 4: 1 = supports COPYBACK
Bit 3: 1 = supports READ STATUS ENHANCED
Bit 2: 1 = supports GET FEATURES and SET FEATURES
Bit 1: 1 = supports read cache commands
Bit 0: 1 = supports PROGRAM PAGE CACHE
10–11 Reserved (0) – All 00h
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Table 8: Parameter Page Data Structure (Continued)

12–13 Extended parameter page length – 03h, 00h
14 Number of parameter pages – 03h
Manufacturer information block
32–43 Device manufacturer (12 ASCII characters) – 4Dh, 49h, 43h, 52h, 4Fh,
Micron 4Eh, 20h, 20h, 20h, 20h,
20h, 20h
44–63 Device model (20 ASCII characters) MT29F64G08CBAAAWP 4Dh, 54h, 32h, 39h,
46h, 36h, 34h, 47h, 30h,
38h, 43h, 42h, 41h, 41h,
41h, 57h, 50h, 20h, 20h,
20h
MT29F64G08CBAABWP 4Dh, 54h, 32h, 39h,
46h, 36h, 34h, 47h, 30h,
38h, 43h, 42h, 41h, 41h,
42h, 57h, 50h, 20h, 20h,
20h
MT29F128G08CFAAAWP 4Dh, 54h, 32h, 39h,
46h, 31h, 32h, 38h, 47h,
30h, 38h, 43h, 46h, 41h,
41h, 41h, 57h, 50h, 20h,
20h
MT29F128G08CFAABWP 4Dh, 54h, 32h, 39h,
46h, 31h, 32h, 38h, 47h,
30h, 38h, 43h, 46h, 41h,
41h, 42h, 57h, 50h, 20h,
20h
MT29F256G08CJAAAWP 4Dh, 54h, 32h, 39h,
46h, 32h, 35h, 36h, 47h,
30h, 38h, 43h, 4Ah,
41h, 41h, 41h, 57h, 50h,
20h, 20h
MT29F256G08CJAABWP 4Dh, 54h, 32h, 39h,
46h, 32h, 35h, 36h, 47h,
30h, 38h, 43h, 4Ah,
41h, 41h, 42h, 57h, 50h,
20h, 20h
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44–63 Device model (20 ASCII characters) MT29F128G08CEAAAC5 4Dh, 54h, 32h, 39h,
46h, 31h, 32h, 38h, 47h,
30h, 38h, 43h, 45h, 41h,
41h, 41h, 43h, 35h, 20h,
20h
MT29F256G08CKAAAC5 4Dh, 54h, 32h, 39h,
46h, 32h, 35h, 36h, 47h,
30h, 38h, 43h, 4Bh, 41h,
41h, 41h, 43h, 35h, 20h,
20h
MT29F256G08CMAAAC5 4Dh, 54h, 32h, 39h,
46h, 32h, 35h, 36h, 47h,
30h, 38h, 43h, 4Dh,
41h, 41h, 41h, 43h, 35h,
20h, 20h
MT29F512G08CUAAAC5 4Dh, 54h, 32h, 39h,
46h, 35h, 31h, 32h, 47h,
30h, 38h, 43h, 55h, 41h,
41h, 41h, 43h, 35h, 20h,
20h
MT29F64G08CBCABH1 4Dh, 54h, 32h, 39h,
46h, 36h, 34h, 47h, 30h,
38h, 43h, 42h, 43h, 41h,
42h, 48h, 31h, 20h, 20h,
20h
MT29F128G08CECABH1 4Dh, 54h, 32h, 39h,
46h, 31h, 32h, 38h, 47h,
30h, 38h, 43h, 45h, 43h,
41h, 42h, 48h, 31h, 20h,
20h
MT29F256G08CKCABH2 4Dh, 54h, 32h, 39h,
46h, 32h, 35h, 36h, 47h,
30h, 38h, 43h, 4Bh, 43h,
41h, 42h, 48h, 32h, 20h,
20h
MT29F256G08CMCABH2 4Dh, 54h, 32h, 39h,
46h, 32h, 35h, 36h, 47h,
30h, 38h, 43h, 4Dh,
43h, 41h, 42h, 48h, 32h,
20h, 20h
MT29F512G08CUCABH3 4Dh, 54h, 32h, 39h,
46h, 35h, 31h, 32h, 47h,
30h, 38h, 43h, 55h, 43h,
41h, 42h, 48h, 33h, 20h,
20h
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64 JEDEC manufacturer ID – 2Ch
65–66 Date code – 00h, 00h
Memory organization block
80–83 Number of data bytes per page – 00h, 20h, 00h, 00h
84–85 Number of spare bytes per page – C0h, 01h
92–95 Number of pages per block – 00h, 01h, 00h, 00h
96–99 Number of blocks per LUN – 00h, 10h, 00h, 00h
100 Number of LUNs per chip enable MT29F64G08CBAAA 01h
MT29F64G08CBAAB
MT29F64G08CBCAB
MT29F128G08CEAAA
MT29F128G08CECAB
MT29F128G08CFAAA
MT29F128G08CFAAB
MT29F256G08CMAAA
MT29F256G08CMCAB
MT29F256G08CJAAA 02h
MT29F256G08CJAAB
MT29F256G08CKAAA
MT29F256G08CKCAB
MT29F512G08CUAAA
MT29F512G08CUCAB
101 Number of address cycles – 23h
Bit[7:4]: Column address cycles
Bit[3:0]: Row address cycles
102 Number of bits per cell – 02h
103–104 Bad blocks maximum per LUN – 64h, 00h
105–106 Block endurance – 03h, 03h
107 Guaranteed valid blocks at beginning of target – 01h
108–109 Block endurance for guaranteed valid blocks – 00h, 00h
110 Number of programs per page – 01h
111 Reserved (0) – 00h
112 Number of bits ECC correctability – FFh
113 Number of interleaved address bits – 01h
Bit[3:0]: Number of interleaved address bits
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114 Interleaved operation attributes – 1Eh
Bit 5: Reserved
Bit 4: 1 = supports read cache
Bit 3: Address restrictions for cache operations
Bit 2: 1 = supports program cache
Bit 1: 1 = no block address restrictions
Bit 0: Overlapped/concurrent interleaving support
Electrical parameters block
128 I/O pin capacitance per chip enable MT29F64G08CBAAAWP 06h
MT29F64G08CBAABWP
MT29F128G08CFAAAWP 05h
MT29F128G08CFAABWP
MT29F256G08CJAAAWP 09h
MT29F256G08CJAABWP
MT29F128G08CEAAAC5 08h
MT29F256G08CKAAAC5 0Ah
MT29F256G08CMAAAC5 05h
MT29F512G08CUAAAC5 08h
MT29F64G08CBCABH1 06h
MT29F128G08CECABH1 06h
MT29F256G08CKCABH2 0Ah
MT29F256G08CMCABH2 05h
MT29F512G08CUCABH3 08h
129–130 Timing mode support – 3Fh, 00h
Bit 5: 1 = supports timing mode 5
Bit 0: 1 = supports timing mode 0, shall be 1
tPROG
133–134 Maximum PROGRAM PAGE time (µs) – 28h, 0Ah
tBERS
135–136 Maximum BLOCK ERASE time (µs) – 10h, 27h
tR
137–138 Maximum PAGE READ time (µs) – 4Bh, 00h
tCCS
139–140 Minimum change column setup time (ns) – C8h, 00h
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141–142 Source synchronous timing mode support MT29F64G08CBAAAWP 00h, 00h
Bit[15:6]: Reserved (0) MT29F128G08CFAAAWP
MT29F256G08CJAAAWP
Bit 3: 1 = supports timing mode 3 MT29F128G08CEAAAC5
Bit 2: 1 = supports timing mode 2 MT29F256G08CKAAAC5
Bit 1: 1 = supports timing mode 1 MT29F256G08CMAAAC5
MT29F512G08CUAAAC5
MT29F64G08CBAABWP 1Fh, 00h
MT29F128G08CFAABWP
MT29F256G08CJAABWP
MT29F64G08CBCABH1 3Fh, 00h
MT29F128G08CECABH1
MT29F256G08CKCABH2
MT29F256G08CMCABH2
MT29F512G08CUCABH3
143 Source synchronous features MT29F64G08CBAAAWP 00h
Bit[7:3]: Reserved (0) MT29F128G08CFAAAWP
Bit 2: 1 = devices support CLK stopped for data input
MT29F256G08CJAAAWP
Bit 1: 1 = typical capacitance values present
Bit 0: 0 = use tCAD MIN value MT29F128G08CEAAAC5
MT29F256G08CKAAAC5
MT29F256G08CMAAAC5
MT29F512G08CUAAAC5
MT29F64G08CBAABWP 02h
MT29F128G08CFAABWP
MT29F256G08CJAABWP
MT29F64G08CBCABH1
MT29F128G08CECABH1
MT29F256G08CKCABH2
MT29F256G08CMCABH2
MT29F512G08CUCABH3
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144–145 CLK input pin capacitance, typical MT29F64G08CBAAAWP 00h, 00h
MT29F128G08CFAAAWP
MT29F256G08CJAAAWP
MT29F128G08CEAAAC5
MT29F256G08CKAAAC5
MT29F256G08CMAAAC5
MT29F512G08CUAAAC5
MT29F64G08CBAABWP 27h, 00h
MT29F128G08CFAABWP 21h, 00h
MT29F256G08CJAABWP 38h, 00h
MT29F64G08CBCABH1 30h, 00h
MT29F128G08CECABH1
MT29F256G08CKCABH2 49h, 00h
MT29F256G08CMCABH2 24h, 00h
MT29F512G08CUCABH3 3Ch, 00h
146–147 I/O pin capacitance, typical MT29F64G08CBAAAWP 00h, 00h
MT29F128G08CFAAAWP
MT29F256G08CJAAAWP
MT29F128G08CEAAAC5
MT29F256G08CKAAAC5
MT29F256G08CMAAAC5
MT29F512G08CUAAAC5
MT29F64G08CBAABWP 2Eh, 00h
MT29F256G08CJAABWP 49h, 00h
MT29F64G08CBCABH1 2Ch, 00h
MT29F128G08CECABH1
MT29F256G08CKCABH2 4Ch, 00h
MT29F512G08CUCABH3 43h, 00h
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148–149 Input capacitance, typical MT29F64G08CBAAAWP 00h, 00h
MT29F128G08CFAAAWP
MT29F256G08CJAAAWP
MT29F128G08CEAAAC5
MT29F256G08CKAAAC5
MT29F256G08CMAAAC5
MT29F512G08CUAAAC5
MT29F64G08CBAABWP 2Dh, 00h
MT29F256G08CJAABWP 3Dh, 00h
MT29F64G08CBCABH1 25h, 00h
MT29F128G08CECABH1
MT29F256G08CKCABH2 40h, 00h
MT29F512G08CUCABH3 37h, 00h
150 Input pin capacitance, maximum MT29F64G08CBAAAWP 08h
MT29F64G08CBAABWP
MT29F128G08CFAAAWP 05h
MT29F128G08CFAABWP
MT29F256G08CJAAAWP 07h
MT29F256G08CJAABWP
MT29F128G08CEAAAC5 08h
MT29F256G08CKAAAC5 0Ah
MT29F256G08CMAAAC5 05h
MT29F512G08CUAAAC5 07h
MT29F64G08CBCABH1 05h
MT29F128G08CECABH1
MT29F256G08CKCABH2 08h
MT29F256G08CMCABH2 04h
MT29F512G08CUCABH3 07h
151 Driver strength support – 07h
Bit 2: 1 = Supports overdrive (2 drive strength)
Bit 1: 1 = Supports overdrive (1 drive strength)
Bit 0: 1 = Supports driver strength settings
tR maximum interleaved (multi-plane) page read time (µs)
152–153 – 4Bh, 00h
tADL program page register clear enhancement value (ns)
154-155 – 46h, 00h
Vendor block
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164–165 Vendor-specific revision number – 01h, 00h
166 TWO-PLANE PAGE READ support – 01h
Bit 0: 1 = Support for TWO-PLANE PAGE READ
167 Read cache support – 00h
Bit 0: 0 = Does not support Micron-specific read cache
function
168 READ UNIQUE ID support – 00h
Bit 0: 0 = Does not support Micron-specific READ
UNIQUE ID
169 Programmable DQ output impedance support – 00h
Bit 0: 0 = No support for programmable DQ output impe-
dance by B8h command
170 Number of programmable DQ output impedance settings – 04h
Bit [2:0] = Number of programmable DQ output impe-
dance settings
171 Programmable DQ output impedance feature address – 10h
Bit[7:0] = Programmable DQ output impedance feature
address
172 Programmable R/B# pull-down strength support – 01h
Bit 0: 1 = Support programmable R/B# pull-down strength
173 Programmable R/B# pull-down strength feature address – 81h
Bit[7:0] = Feature address used with programmable R/B#
pull-down strength
174 Number of programmable R/B# pull-down strength set- – 04h
tings
Bit[2:0] = Number of programmable R/B# pull-down
strength settings
175 OTP mode support – 02h
Bit 1: 1 = Supports Get/Set Features command set
Bit 0: 0 = Does not support A5h/A0h/AFh OTP command
set
176 OTP page start – 02h
Bit[7:0] = Page where OTP page space begins
177 OTP DATA PROTECT address – 01h
Bit[7:0] = Page address to use when issuing OTP DATA
PROTECT command
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178 Number of OTP pages – 1Eh
Bit[4:0] = Number of OTP pages
179 OTP Feature Address – 90h
253 Parameter page revision MT29F64G08CBAABWP 04h
MT29F128G08CFAABWP
MT29F256G08CJAABWP
MT29F64G08CBAAAWP 05h
MT29F128G08CFAAAWP
MT29F256G08CJAAAWP
MT29F128G08CEAAAC5
MT29F256G08CKAAAC5
MT29F256G08CMAAAC5
MT29F512G08CUAAAC5
MT29F64G08CBCABH1
MT29F128G08CECABH1
MT29F256G08CKCABH2
MT29F256G08CMCABH2
MT29F512G08CUCABH3
254–255 Integrity CRC MT29F64G08CBAAAWP 39h, 13h
MT29F64G08CBAABWP EFh, 82h
MT29F128G08CFAAAWP 1Bh, F3h
MT29F128G08CFAABWP 77h, DFh
MT29F256G08CJAAAWP E5h, F8h
MT29F256G08CJAABWP EFh, 82h
MT29F128G08CEAAAC5 0Eh, 79h
MT29F256G08CKAAAC5 8Ah, 02h
MT29F256G08CMAAAC5 24h, 07h
MT29F512G08CUAAAC5 0Eh, 22h
MT29F64G08CBCABH1 7Eh, C7h
MT29F128G08CECABH1 B8h, 2Ch
MT29F256G08CKCABH2 A1h, 3Ch
MT29F256G08CMCABH2 35h, D6h
MT29F512G08CUCABH3 1Dh, 1Ch
Redundant parameter pages
256–511 Value of bytes 0–255 – See bytes 0–255
512–767 Value of bytes 0–255 – See bytes 0–255
Extended parameter pages
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768–769 Extended parameter page Integrity CRC – BCh, 71h
770-773 Extended parameter page signature – 45h, 50h, 50h, 53h
Byte 0: 45h, “E”
Byte 1: 50h, “P”
Byte 2: 50h, “P”
Byte 3: 53h, “S”
774-783 Reserved (0) – All 00h
784 Section 0 type – 02h
785 Section 0 length – 01h
800 Number of bits ECC correctability – 18h
801 ECC codeword size – 0Ah
802-803 Bad blocks maximum per LUN – 64h, 00h
804-805 Block endurance – 03h, 03h
816-863 Value of bytes 768-815 – See bytes 768-815
864-911 Value of bytes 768-815 – See bytes 768-815
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READ UNIQUE ID (EDh)

The READ UNIQUE ID (EDh) command is used to read a unique identifier programmed
into the target. This command is accepted by the target only when all die (LUNs) on the
target are idle.
Writing EDh to the command register puts the target in read unique ID mode. The tar-
get stays in this mode until another valid command is issued.
When the EDh command is followed by a 00h address cycle, the target goes busy for tR.
If the READ STATUS (70h) command is used to monitor for command completion, the
READ MODE (00h) command must be used to re-enable data output mode.
After tR completes, the host enables data output mode to read the unique ID. When the
asynchronous interface is active, one data byte is output per RE# toggle. When the syn-
chronous interface is active, two data bytes are output, one byte for each rising or
falling edge of DQS.
Sixteen copies of the unique ID data are stored in the device. Each copy is 32 bytes. The
first 16 bytes of a 32-byte copy are unique data, and the second 16 bytes are the comple-
ment of the first 16 bytes. The host should XOR the first 16 bytes with the second 16
bytes. If the result is 16 bytes of FFh, then that copy of the unique ID data is correct. In
the event that a non-FFh result is returned, the host can repeat the XOR operation on a
subsequent copy of the unique ID data. If desired, the CHANGE READ COLUMN (05h-
E0h) command can be used to change the data output location. Use of the CHANGE
READ COLUMN ENHANCED (06h-E0h) command is prohibited.
Figure 43: READ UNIQUE ID (EDh) Operation
Cycle type Command Address DOUT DOUT DOUT DOUT DOUT DOUT
DQ[7:0] EDh 00h U00 U10 … U01 U11 …

tWB tR tRR
R/B#
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The SET FEATURES (EFh) and GET FEATURES (EEh) commands are used to modify the
target's default power-on behavior. These commands use a one-byte feature address to
determine which subfeature parameters will be read or modified. Each feature address
(in the 00h to FFh range) is defined in Table 9. The SET FEATURES (EFh) command
writes subfeature parameters (P1-P4) to the specified feature address. The GET FEA-
TURES command reads the subfeature parameters (P1-P4) at the specified feature
address.
Unless otherwise specifed, the values of the feature addresses do not change when RE-
SET (FFh, FCh) is issued by the host.
Table 9: Feature Address Definitions
Feature Address Definition

00h Reserved
01h Timing mode
02h–0Fh Reserved
10h Programmable output drive strength
11h–7Fh Reserved
80h Programmable output drive strength
81h Programmable RB# pull-down strength
82h–8Fh Reserved
90h Array operation mode
91h–FFh Reserved
SET FEATURES (EFh)

The SET FEATURES (EFh) command writes the subfeature parameters (P1-P4) to the
specified feature address to enable or disable target-specific features. This command is
accepted by the target only when all die (LUNs) on the target are idle.
Writing EFh to the command register puts the target in the set features mode. The tar-
get stays in this mode until another command is issued.
The EFh command is followed by a valid feature address as specified in Table 9. The
host waits for tADL before the subfeature parameters are input. When the asynchro-
nous interface is active, one subfeature parameter is latched per rising edge of WE#.
When the synchronous interface is active, one subfeature parameter is latched per ris-
ing edge of DQS. The data on the falling edge of DQS should be identical to the
subfeature parameter input on the previous rising edge of DQS. The device is not re-
quired to wait for the repeated data byte before beginning internal actions.
After all four subfeature parameters are input, the target goes busy for tFEAT. The READ
STATUS (70h) command can be used to monitor for command completion.
Feature address 01h (timing mode) operation is unique. If SET FEATURES is used to
modify the interface type, the target will be busy for tITC. See Activating Interfaces
(page 46) for details.
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Figure 44: SET FEATURES (EFh) Operation
Cycle type Command Address DIN DIN DIN DIN

tADL
DQ[7:0] EFh FA P1 P2 P3 P4
tWB tFEAT
R/B#
GET FEATURES (EEh)

The GET FEATURES (EEh) command reads the subfeature parameters (P1-P4) from the
specified feature address. This command is accepted by the target only when all die
(LUNs) on the target are idle.
Writing EEh to the command register puts the target in get features mode. The target
stays in this mode until another valid command is issued.
When the EEh command is followed by a feature address, the target goes busy for
tFEAT. If the READ STATUS (70h) command is used to monitor for command comple-
tion, the READ MODE (00h) command must be used to re-enable data output mode.
During and prior to data output, use of the READ STATUS ENHANCED (78h) command
is prohibited.
After tFEAT completes, the host enables data output mode to read the subfeature param-
eters. When the asynchronous interface is active, one data byte is output per RE#
toggle. When the synchronous interface is active, one subfeature parameter is output
per DQS toggle on rising or falling edge of DQS.
Figure 45: GET FEATURES (EEh) Operation
Cycle type Command Address DOUT DOUT DOUT DOUT
DQ[7:0] EEh FA P1 P2 P3 P4
tWB tFEAT tRR
R/B#
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Table 10: Feature Address 01h: Timing Mode
Subfeature
Parameter Options DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 Value Notes
P1
Timing mode Mode 0 (default) 0 0 0 0 x0h 1, 2
Mode 1 0 0 0 1 x1h
Mode 2 0 0 1 0 x2h
Mode 3 0 0 1 1 x3h
Mode 4 0 1 0 0 x4h
Mode 5 0 1 0 1 x5h
Data interface Asynchronous 0 0 0xh 1
(default)
Synchronous DDR 0 1 1xh
Reserved 1 x 2xh
Program clear Program com- 0 0b
mand clears all
cache registers on
a target (default)
Program com- 1 1b
mand clears only
addressed LUN
cache register on a
target
Reserved 0 0b
P2
Reserved 0 0 0 0 0 0 0 0 00h
P3
Reserved 0 0 0 0 0 0 0 0 00h
P4
Reserved 0 0 0 0 0 0 0 0 00h
Notes: 1. Asynchronous timing mode 0 is the default, power-on value.

2. If the synchronous interface is active, a RESET (FFh) command will change the timing
mode and data interface bits of feature address 01h to their default values. If the asyn-
chronous interface is active, a RESET (FFh) command will not change the values of the
timing mode or data interface bits to their default valued.
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Table 11: Feature Addresses 10h and 80h: Programmable Output Drive Strength
Subfeature Pa-
rameter Options DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 Value Notes
P1
Output drive Overdrive 2 0 0 00h 1
strength Overdrive 1 0 1 01h
Nominal (de- 1 0 02h
fault)
Underdrive 1 1 03h
Reserved 0 0 0 0 0 0 00h
P2
Reserved 0 0 0 0 0 0 0 0 00h
P3
Reserved 0 0 0 0 0 0 0 0 00h
P4
Reserved 0 0 0 0 0 0 0 0 00h
Note: 1. See Output Drive Strength Impedance Values (VCCQ = 2.7–3.6V) table for details.
Table 12: Feature Addresses 81h: Programmable R/B# Pull-Down Strength
Subfeature Pa-
P1
R/B# pull-down Full (default) 0 0 00h 1
strength Three-quarter 0 1 01h
One-half 1 0 02h
One-quarter 1 1 03h
Reserved 0 0 0 0 0 0 00h
P2
Reserved 0 0 0 0 0 0 0 0 00h
P3
Reserved 0 0 0 0 0 0 0 0 00h
P4
Reserved 0 0 0 0 0 0 0 0 00h
Note: 1. This feature address is used to change the default R/B# pull-down strength. Its strength
should be selected based on the expected loading of R/B#. Full strength is the default,
power-on value.
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Table 13: Feature Addresses 90h: Array Operation Mode
Subfeature Pa-
P1
Array Operation Normal (de- 0 00h
Mode fault)
OTP Block 1 01h 1
Reserved 0 0 0 0 0 0 0 00h
P2
Reserved 0 0 0 0 0 0 0 0 00h
P3
Reserved 0 0 0 0 0 0 0 0 00h
P4
Reserved 0 0 0 0 0 0 0 0 00h
Notes: 1. See One-Time Programmable (OTP) Operations for details.

2. A RESET (FFh) command will cause the bits of the array operation mode to change to
their default values.
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Status Operations
Status Operations
Each die (LUN) provides its status independently of other die (LUNs) on the same tar-
get through its 8-bit status register.
After the READ STATUS (70h) or READ STATUS ENHANCED (78h) command is issued,
status register output is enabled. The contents of the status register are returned on
DQ[7:0] for each data output request.
When the asynchronous interface is active and status register output is enabled,
changes in the status register are seen on DQ[7:0] as long as CE# and RE# are LOW; it is
not necessary to toggle RE# to see the status register update.
When the synchronous interface is active and status register output is enabled, changes
in the status register are seen on DQ[7:0] as long as CE# and W/R# are LOW and ALE
and CLE are HIGH. DQS also toggles while ALE and CLE are HIGH.
While monitoring the status register to determine when a data transfer from the Flash
array to the data register (tR) is complete, the host must issue the READ MODE (00h)
command to disable the status register and enable data output (see READ MODE (00h)
(page 83)).
The READ STATUS (70h) command returns the status of the most recently selected die
(LUN). To prevent data contention during or following an interleaved die (multi-LUN)
operation, the host must enable only one die (LUN) for status output by using the READ
STATUS ENHANCED (78h) command (see Interleaved Die (Multi-LUN) Operations
(page 108)).
Table 14: Status Register Definition
Independent
SR Bit Definition per Plane1 Description
7 WP# – Write Protect:
0 = Protected
1 = Not protected
In the normal array mode, this bit indicates the value of the WP# signal. In
OTP mode this bit is set to 0 if a PROGRAM OTP PAGE operation is attemp-
ted and the OTP area is protected.
6 RDY – Ready/Busy I/O:
0 = Busy
1 = Ready
This bit indicates that the selected die (LUN) is not available to accept new
commands, address, or data I/O cycles with the exception of RESET (FFh),
SYNCHRONOUS RESET (FCh), READ STATUS (70h), and READ STATUS EN-
HANCED (78h). This bit applies only to the selected die (LUN).
5 ARDY – Ready/Busy Array:
0 = Busy
1 = Ready
This bit goes LOW (busy) when an array operation is occurring on any
plane of the selected die (LUN). It goes HIGH when all array operations on
the selected die (LUN) finish. This bit applies only to the selected die (LUN).
4 – – Reserved (0)
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Status Operations
Table 14: Status Register Definition (Continued)
Independent
SR Bit Definition per Plane1 Description
1 FAILC Yes Pass/Fail (N–1):
0 = Pass
1 = Fail
This bit is set if the previous operation on the selected die (LUN) failed. This
bit is valid only when RDY (SR bit 6) is 1. It applies to PROGRAM-, and COPY-
BACK PROGRAM-series operations (80h-10h, 80h-15h, 85h-10h). This bit is
not valid following an ERASE-series or READ-series operation.
0 FAIL Yes Pass/Fail (N):
0 = Pass
1 = Fail
This bit is set if the most recently finished operation on the selected die
(LUN) failed. This bit is valid only when ARDY (SR bit 5) is 1. It applies to
PROGRAM-, ERASE-, and COPYBACK PROGRAM-series operations (80h-10h,
80h-15h, 60h-D0h, 85h-10h). This bit is not valid following a READ-series
operation.
Note: 1. After a multi-plane operation begins, the FAILC and FAIL bits are ORed together for the
active planes when the READ STATUS (70h) command is issued. After the READ STATUS
ENHANCED (78h) command is issued, the FAILC and FAIL bits reflect the status of the
plane selected.
READ STATUS (70h)

The READ STATUS (70h) command returns the status of the last-selected die (LUN) on
a target. This command is accepted by the last-selected die (LUN) even when it is busy
(RDY = 0).
If there is only one die (LUN) per target, the READ STATUS (70h) command can be used
to return status following any NAND command.
In devices that have more than one die (LUN) per target, during and following inter-
leaved die (multi-LUN) operations, the READ STATUS ENHANCED (78h) command
must be used to select the die (LUN) that should report status. In this situation, using
the READ STATUS (70h) command will result in bus contention, as two or more die
(LUNs) could respond until the next operation is issued. The READ STATUS (70h) com-
mand can be used following all single die (LUN) operations.
If following a multi-plane operation, regardless of the number of LUNs per target, the
READ STATUS (70h) command indicates an error occurred (FAIL = 1), use the READ
STATUS ENHANCED (78h) command—once for each plane—to determine which plane
operation failed.
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Status Operations
Figure 46: READ STATUS (70h) Operation
Cycle type Command DOUT

tWHR
DQ[7:0] 70h SR
READ STATUS ENHANCED (78h)

The READ STATUS ENHANCED (78h) command returns the status of the addressed die
(LUN) on a target even when it is busy (RDY = 0). This command is accepted by all die
(LUNs), even when they are BUSY (RDY = 0).
Writing 78h to the command register, followed by three row address cycles containing
the page, block, and LUN addresses, puts the selected die (LUN) into read status mode.
The selected die (LUN) stays in this mode until another valid command is issued. Die
(LUNs) that are not addressed are deselected to avoid bus contention.
The selected LUN's status is returned when the host requests data output. The RDY and
ARDY bits of the status register are shared for all of the planes of the selected die (LUN).
The FAILC and FAIL bits are specific to the plane specified in the row address.
The READ STATUS ENHANCED (78h) command also enables the selected die (LUN) for
data output. To begin data output following a READ-series operation after the selected
die (LUN) is ready (RDY = 1), issue the READ MODE (00h) command, then begin data
output. If the host needs to change the cache register that will output data, use the
CHANGE READ COLUMN ENHANCED (06h-E0h) command after the die (LUN) is
ready (see CHANGE READ COLUMN ENHANCED (06h-E0h)).
Use of the READ STATUS ENHANCED (78h) command is prohibited during the power-
on RESET (FFh) command and when OTP mode is enabled. It is also prohibited follow-
ing some of the other reset, identification, and configuration operations. See individual
operations for specific details.
Figure 47: READ STATUS ENHANCED (78h) Operation
Cycle type Command Address Address Address Dout

tWHR
DQx 78h R1 R2 R3 SR
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The column address operations affect how data is input to and output from the cache
registers within the selected die (LUNs). These features provide host flexibility for man-
aging data, especially when the host internal buffer is smaller than the number of data
bytes or words in the cache register.
When the asynchronous interface is active, column address operations can address any
byte in the selected cache register.
When the synchronous interface is active, column address operations are aligned to
word boundaries (CA0 is forced to 0), because as data is transferred on DQ[7:0] in two-
byte units.
CHANGE READ COLUMN (05h-E0h)

The CHANGE READ COLUMN (05h-E0h) command changes the column address of the
selected cache register and enables data output from the last selected die (LUN). This
command is accepted by the selected die (LUN) when it is ready (RDY = 1; ARDY = 1). It
is also accepted by the selected die (LUN) during CACHE READ operations
(RDY = 1; ARDY = 0).
Writing 05h to the command register, followed by two column address cycles contain-
ing the column address, followed by the E0h command, puts the selected die (LUN)
into data output mode. After the E0h command cycle is issued, the host must wait at
least tCCS before requesting data output. The selected die (LUN) stays in data output
mode until another valid command is issued.
In devices with more than one die (LUN) per target, during and following interleaved
die (multi-LUN) operations, the READ STATUS ENHANCED (78h) command must be
issued prior to issuing the CHANGE READ COLUMN (05h-E0h). In this situation, using
the CHANGE READ COLUMN (05h-E0h) command without the READ STATUS EN-
HANCED (78h) command will result in bus contention, as two or more die (LUNs)
could output data.
Figure 48: CHANGE READ COLUMN (05h-E0h) Operation
Cycle type DOUT DOUT Command Address Address Command DOUT DOUT DOUT
tRHW tCCS
DQ[7:0] Dn Dn + 1 05h C1 C2 E0h Dk Dk + 1 Dk + 2
SR[6]
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CHANGE READ COLUMN ENHANCED (06h-E0h)

The CHANGE READ COLUMN ENHANCED (06h-E0h) command enables data output
on the addressed die’s (LUN’s) cache register at the specified column address. This com-
mand is accepted by a die (LUN) when it is ready (RDY = 1; ARDY = 1).
Writing 06h to the command register, followed by two column address cycles and three
row address cycles, followed by E0h, enables data output mode on the address LUN’s
cache register at the specified column address. After the E0h command cycle is issued,
the host must wait at least tCCS before requesting data output. The selected die (LUN)
stays in data output mode until another valid command is issued.
Following a multi-plane read page operation, the CHANGE READ COLUMN EN-
HANCED (06h-E0h) command is used to select the cache register to be enabled for data
output. After data output is complete on the selected plane, the command can be is-
sued again to begin data output on another plane.
In devices with more than one die (LUN) per target, after all of the die (LUNs) on the
target are ready (RDY = 1), the CHANGE READ COLUMN ENHANCED (06h-E0h) com-
mand can be used following an interleaved die (multi-LUN) read operation. Die (LUNs)
that are not addressed are deselected to avoid bus contention.
In devices with more than one die (LUN) per target, during interleaved die (multi-LUN)
operations where more than one or more die (LUNs) are busy (RDY = 1; ARDY = 0 or
RDY = 0; ARDY = 0), the READ STATUS ENHANCED (78h) command must be issued to
the die (LUN) to be selected prior to issuing the CHANGE READ COLUMN ENHANCED
(06h-E0h). In this situation, using the CHANGE READ COLUMN ENHANCED (06h-E0h)
command without the READ STATUS ENHANCED (78h) command will result in bus
contention, as two or more die (LUNs) could output data.
If there is a need to update the column address without selecting a new cache register
or LUN, the CHANGE READ COLUMN (05h-E0h) command can be used instead.
Figure 49: CHANGE READ COLUMN ENHANCED (06h-E0h) Operation
Cycle
Dout Dout Command Address Address Address Address Address Command Dout Dout Dout
type
tRHW tCCS
DQ[7:0] Dn Dn + 1 06h C1 C2 R1 R2 R3 E0h Dk Dk + 1 Dk + 2
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CHANGE WRITE COLUMN (85h)

The CHANGE WRITE COLUMN (85h) command changes the column address of the se-
lected cache register and enables data input on the last-selected die (LUN). This com-
mand is accepted by the selected die (LUN) when it is ready (RDY = 1; ARDY = 1). It is
also accepted by the selected die (LUN) during cache program operations
(RDY = 1; ARDY = 0).
Writing 85h to the command register, followed by two column address cycles contain-
ing the column address, puts the selected die (LUN) into data input mode. After the
second address cycle is issued, the host must wait at least tCCS before inputting data.
The selected die (LUN) stays in data input mode until another valid command is issued.
Though data input mode is enabled, data input from the host is optional. Data input
begins at the column address specified.
The CHANGE WRITE COLUMN (85h) command is allowed after the required address
cycles are specified, but prior to the final command cycle (10h, 11h, 15h) of the follow-
ing commands while data input is permitted: PROGRAM PAGE (80h-10h), PROGRAM
PAGE MULTI-PLANE (80h-11h), PROGRAM PAGE CACHE (80h-15h), COPYBACK PRO-
GRAM (85h-10h), and COPYBACK PROGRAM MULTI-PLANE (85h-11h).
In devices that have more than one die (LUN) per target, the CHANGE WRITE COL-
UMN (85h) command can be used with other commands that support interleaved die
(multi-LUN) operations.
Figure 50: CHANGE WRITE COLUMN (85h) Operation
As defined for PAGE As defined for PAGE

(CACHE) PROGRAM (CACHE) PROGRAM
Cycle type DIN DIN Command Address Address DIN DIN DIN
tCCS
DQ[7:0] Dn Dn + 1 85h C1 C2 Dk Dk + 1 Dk + 2
RDY
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CHANGE ROW ADDRESS (85h)

The CHANGE ROW ADDRESS (85h) command changes the row address (block and
page) where the cache register contents will be programmed in the NAND Flash array.
It also changes the column address of the selected cache register and enables data input
on the specified die (LUN). This command is accepted by the selected die (LUN) when
it is ready (RDY = 1; ARDY = 1). It is also accepted by the selected die (LUN) during
cache programming operations (RDY = 1; ARDY = 0).
Write 85h to the command register. Then write two column address cycles and three
row address cycles. This updates the page and block destination of the selected plane
for the addressed LUN and puts the cache register into data input mode. After the fifth
address cycle is issued the host must wait at least tCCS before inputting data. The selec-
ted LUN stays in data input mode until another valid command is issued. Though data
input mode is enabled, data input from the host is optional. Data input begins at the
column address specified.
The CHANGE ROW ADDRESS (85h) command is allowed after the required address cy-
cles are specified, but prior to the final command cycle (10h, 11h, 15h) of the following
commands while data input is permitted: PROGRAM PAGE (80h-10h), PROGRAM PAGE
MULTI-PLANE (80h-11h), PROGRAM PAGE CACHE (80h-15h), COPYBACK PROGRAM
(85h-10h), and COPYBACK PROGRAM MULTI-PLANE (85h-11h). When used with these
commands, the LUN address and plane select bits are required to be identical to the
LUN address and plane select bits originally specified.
The CHANGE ROW ADDRESS (85h) command enables the host to modify the original
page and block address for the data in the cache register to a new page and block address.
In devices that have more than one die (LUN) per target, the CHANGE ROW ADDRESS
(85h) command can be used with other commands that support interleaved die (multi-
LUN) operations.
The CHANGE ROW ADDRESS (85h) command can be used with the CHANGE READ
COLUMN (05h-E0h) or CHANGE READ COLUMN ENHANCED (06h-E0h) commands
to read and modify cache register contents in small sections prior to programming
cache register contents to the NAND Flash array. This capability can reduce the amount
of buffer memory used in the host controller.
To modify the cache register contents in small sections, first issue a PAGE READ
(00h-30h) or COPYBACK READ (00h-35h) operation. When data output is enabled, the
host can output a portion of the cache register contents. To modify the cache register
contents, issue the 85h command, the column and row addresses, and input the new
data. The host can re-enable data output by issuing the 11h command, waiting tDBSY,
and then issuing the CHANGE READ COLUMN (05h-E0h) or CHANGE READ COLUMN
ENHANCED (06h-E0h) command. It is possible toggle between data output and data
input multiple times. After the final CHANGE ROW ADDRESS (85h) operation is com-
plete, issue the 10h command to program the cache register to the NAND Flash array.
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Figure 51: CHANGE ROW ADDRESS (85h) Operation
As defined for PAGE As defined for PAGE

(CACHE) PROGRAM (CACHE) PROGRAM
Cycle type DIN DIN Command Address Address Address Address Address DIN DIN DIN
tCCS
DQ[7:0] Dn Dn + 1 85h C1 C2 R1 R2 R3 Dk Dk + 1 Dk + 2
RDY
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Read Operations
Read Operations
Read operations are used to copy data from the NAND Flash array of one or more of the
planes to their respective cache registers and to enable data output from the cache reg-
isters to the host through the DQ bus.
Read Operations
The READ PAGE (00h-30h) command, when issued by itself, reads one page from the
NAND Flash array to its cache register and enables data output for that cache register.
During data output the following commands can be used to read and modify the data
in the cache registers: CHANGE READ COLUMN (05h-E0h) and CHANGE ROW AD-
DRESS (85h).
Read Cache Operations
To increase data throughput, the READ PAGE CACHE-series (31h, 00h-31h) commands
can be used to output data from the cache register while concurrently copying a page
from the NAND Flash array to the data register.
To begin a read page cache sequence, begin by reading a page from the NAND Flash
array to its corresponding cache register using the READ PAGE (00h-30h) command.
R/B# goes LOW during tR and the selected die (LUN) is busy (RDY = 0, ARDY = 0). After
tR (R/B# is HIGH and RDY = 1, ARDY = 1), issue either of these commands:
• READ PAGE CACHE SEQUENTIAL (31h)—copies the next sequential page from the
NAND Flash array to the data register
• READ PAGE CACHE RANDOM (00h-31h)—copies the page specified in this com-
mand from the NAND Flash array (any plane) to its corresponding data register
After the READ PAGE CACHE-series (31h, 00h-31h) command has been issued, R/B#
goes LOW on the target, and RDY = 0 and ARDY = 0 on the die (LUN) for tRCBSY while
the next page begins copying data from the array to the data register. After tRCBSY,
R/B# goes HIGH and the die’s (LUN’s) status register bits indicate the device is busy
with a cache operation (RDY = 1, ARDY = 0). The cache register becomes available and
the page requested in the READ PAGE CACHE operation is transferred to the data regis-
ter. At this point, data can be output from the cache register, beginning at column
address 0. The CHANGE READ COLUMN (05h-E0h) command can be used to change
the column address of the data output by the die (LUN).
After outputting the desired number of bytes from the cache register, either an addition-
al READ PAGE CACHE-series (31h, 00h-31h) operation can be started or the READ
PAGE CACHE LAST (3Fh) command can be issued.
If the READ PAGE CACHE LAST (3Fh) command is issued, R/B# goes LOW on the tar-
get, and RDY = 0 and ARDY = 0 on the die (LUN) for tRCBSY while the data register is
copied into the cache register. After tRCBSY, R/B# goes HIGH and RDY = 1 and
ARDY = 1, indicating that the cache register is available and that the die (LUN) is ready.
Data can then be output from the cache register, beginning at column address 0. The
CHANGE READ COLUMN (05h-E0h) command can be used to change the column ad-
dress of the data being output.
For READ PAGE CACHE-series (31h, 00h-31h, 3Fh), during the die (LUN) busy time,
tRCBSY, when RDY = 0 and ARDY = 0, the only valid commands are status operations
(70h, 78h) and RESET (FFh, FCh). When RDY = 1 and ARDY = 0, the only valid com-
mands during READ PAGE CACHE-series (31h, 00h-31h) operations are status opera-
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Read Operations
tions (70h, 78h), READ MODE (00h), READ PAGE CACHE-series (31h, 00h-31h),
CHANGE READ COLUMN (05h-E0h), and RESET (FFh, FCh).
Multi-Plane Read Operations
Multi-plane read page operations improve data throughput by copying data from more
than one plane simultaneously to the specified cache registers. This is done by prepend-
ing one or more READ PAGE MULTI-PLANE (00h-32h) commands in front of the READ
PAGE (00h-30h) command.
When the die (LUN) is ready, the CHANGE READ COLUMN ENHANCED (06h-E0h) com-
mand determines which plane outputs data. During data output, the following com-
mands can be used to read and modify the data in the cache registers: CHANGE READ
COLUMN (05h-E0h) and CHANGE ROW ADDRESS (85h). See Multi-Plane Operations
for details.
Multi-Plane Read Cache Operations
Multi-plane read cache operations can be used to output data from more than one
cache register while concurrently copying one or more pages from the NAND Flash ar-
ray to the data register. This is done by prepending READ PAGE MULTI-PLANE
(00h-32h) commands in front of the PAGE READ CACHE RANDOM (00h-31h) command.
To begin a multi-plane read page cache sequence, begin by issuing a MULTI-PLANE
READ PAGE operation using the READ PAGE MULTI-PLANE (00h-32h) and READ PAGE
(00h-30h) commands. R/B# goes LOW during tR and the selected die (LUN) is busy
(RDY = 0, ARDY = 0). After tR (R/B# is HIGH and RDY = 1, ARDY = 1), issue either of
these commands:
• READ PAGE CACHE SEQUENTIAL (31h)—copies the next sequential page from the
previously addressed planes from the NAND Flash array to the data registers.
• READ PAGE MULTI-PLANE (00h-32h) commands, if desired, followed by the READ
PAGE CACHE RANDOM (00h-31h) command—copies the pages specified from the
NAND Flash array to the corresponding data registers.
After the READ PAGE CACHE-series (31h, 00h-31h) command has been issued, R/B#
goes LOW on the target, and RDY = 0 and ARDY = 0 on the die (LUN) for tRCBSY while
the next pages begin copying data from the array to the data registers. After tRCBSY,
R/B# goes HIGH and the LUN’s status register bits indicate the device is busy with a
cache operation (RDY = 1, ARDY = 0). The cache registers become available and the pa-
ges requested in the READ PAGE CACHE operation are transferred to the data registers.
Issue the CHANGE READ COLUMN ENHANCED (06h-E0h) command to determine
which cache register will output data. After data is output, the CHANGE READ COL-
UMN ENHANCED (06h-E0h) command can be used to output data from other cache
registers. After a cache register has been selected, the CHANGE READ COLUMN (05h-
E0h) command can be used to change the column address of the data output.
After outputting data from the cache registers, either an additional MULTI-PLANE
READ CACHE-series (31h, 00h-31h) operation can be started or the READ PAGE CACHE
LAST (3Fh) command can be issued.
If the READ PAGE CACHE LAST (3Fh) command is issued, R/B# goes LOW on the tar-
get, and RDY = 0 and ARDY = 0 on the die (LUN) for tRCBSY while the data registers are
copied into the cache registers. After tRCBSY, R/B# goes HIGH and RDY = 1 and ARDY =
1, indicating that the cache registers are available and that the die (LUN) is ready. Issue
the CHANGE READ COLUMN ENHANCED (06h-E0h) command to determine which
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Read Operations
cache register will output data. After data is output, the CHANGE READ COLUMN EN-
HANCED (06h-E0h) command can be used to output data from other cache registers.
After a cache register has been selected, the CHANGE READ COLUMN (05h-E0h) com-
mand can be used to change the column address of the data output.
For READ PAGE CACHE-series (31h, 00h-31h, 3Fh), during the die (LUN) busy time,
tRCBSY, when RDY = 0 and ARDY = 0, the only valid commands are status operations
(70h, 78h) and RESET (FFh, FCh). When RDY = 1 and ARDY = 0, the only valid com-
mands during READ PAGE CACHE-series (31h, 00h-31h) operations are status opera-
tions (70h, 78h), READ MODE (00h), multi-plane read cache-series (31h, 00h-32h,
00h-31h), CHANGE READ COLUMN (05h-E0h, 06h-E0h), and RESET (FFh, FCh).
See Multi-Plane Operations for additional multi-plane addressing requirements.
READ MODE (00h)

The READ MODE (00h) command disables status output and enables data output for
the last-selected die (LUN) and cache register after a READ operation (00h-30h,
00h-35h) has been monitored with a status operation (70h, 78h). This command is ac-
cepted by the die (LUN) when it is ready (RDY = 1, ARDY = 1). It is also accepted by the
die (LUN) during READ PAGE CACHE (31h, 3Fh, 00h-31h) operations
(RDY = 1 and ARDY = 0).
must be used to select only one die (LUN) prior to issuing the READ MODE (00h) com-
mand. This prevents bus contention.
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Read Operations
READ PAGE (00h-30h)

The READ PAGE (00h–30h) command copies a page from the NAND Flash array to its
respective cache register and enables data output. This command is accepted by the die
(LUN) when it is ready (RDY = 1, ARDY = 1).
To read a page from the NAND Flash array, write the 00h command to the command
register, the write five address cycles to the address registers, and conclude with the 30h
command. The selected die (LUN) will go busy (RDY = 0, ARDY = 0) for tR as data is
transferred.
To determine the progress of the data transfer, the host can monitor the target's R/B#
signal or, alternatively, the status operations (70h, 78h) can be used. If the status opera-
tions are used to monitor the LUN's status, when the die (LUN) is ready
(RDY = 1, ARDY = 1), the host disables status output and enables data output by issuing
the READ MODE (00h) command. When the host requests data output, output begins
at the column address specified.
During data output the CHANGE READ COLUMN (05h-E0h) command can be issued.
leaved die (multi-LUN) operations the READ STATUS ENHANCED (78h) command
must be used to select only one die (LUN) prior to the issue of the READ MODE (00h)
command. This prevents bus contention.
The READ PAGE (00h-30h) command is used as the final command of a multi-plane
read operation. It is preceded by one or more READ PAGE MULTI-PLANE (00h-32h)
commands. Data is transferred from the NAND Flash array for all of the addressed
planes to their respective cache registers. When the die (LUN) is ready
(RDY = 1, ARDY = 1), data output is enabled for the cache register linked to the plane
addressed in the READ PAGE (00h-30h) command. When the host requests data output,
output begins at the column address last specified in the READ PAGE (00h-30h) com-
mand. The CHANGE READ COLUMN ENHANCED (06h-E0h) command is used to
enable data output in the other cache registers. See Multi-Plane Operations for addition-
al multi-plane addressing requirements.
Figure 52: READ PAGE (00h-30h) Operation
Cycle type Command Address Address Address Address Address Command DOUT DOUT DOUT
DQ[7:0] 00h C1 C2 R1 R2 R3 30h Dn Dn+1 Dn+2

tWB tR tRR
RDY
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Read Operations
READ PAGE CACHE SEQUENTIAL (31h)

The READ PAGE CACHE SEQUENTIAL (31h) command reads the next sequential page
within a block into the data register while the previous page is output from the cache
register. This command is accepted by the die (LUN) when it is ready
(RDY = 1, ARDY = 1). It is also accepted by the die (LUN) during READ PAGE CACHE
(31h, 00h-31h) operations (RDY = 1 and ARDY = 0).
To issue this command, write 31h to the command register. After this command is is-
sued, R/B# goes LOW and the die (LUN) is busy (RDY = 0, ARDY = 0) for tRCBSY. After
tRCBSY, R/B# goes HIGH and the die (LUN) is busy with a cache operation
(RDY = 1, ARDY = 0), indicating that the cache register is available and that the specified
page is copying from the NAND Flash array to the data register. At this point, data can
be output from the cache register beginning at column address 0. The CHANGE READ
COLUMN (05h-E0h) command can be used to change the column address of the data
being output from the cache register.
The READ PAGE CACHE SEQUENTIAL (31h) command can be used to cross block boun-
daries. If the READ PAGE CACHE SEQUENTIAL (31h) command is issued after the last
page of a block is read into the data register, the next page read will be the next logical
block in the plane which the 31h command was issued. Do not issue the READ PAGE
CACHE SEQUENTIAL (31h) to cross die (LUN) boundaries. Instead, issue the READ
PAGE CACHE LAST (3Fh) command.
If the READ PAGE CACHE SEQUENTIAL (31h) command is issued after a MULTI-
PLANE READ PAGE operation (00h-32h, 00h-30h), the next sequential pages are read
into the data registers while the previous pages can be output from the cache registers.
After the die (LUN) is ready (RDY = 1, ARDY = 0), the CHANGE READ COLUMN EN-
HANCED (06h-E0h) command is used to select which cache register outputs data.
Figure 53: READ PAGE CACHE SEQUENTIAL (31h) Operation
Cycle type Command Address x5 Command Command DOUT DOUT DOUT Command DOUT
DQ[7:0] 00h Page Address M 30h 31h D0 … Dn 31h D0

tWB tR tWB tRCBSY tRR tWB tRCBSY tRR
RDY
Page M Page M+1
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Read Operations
READ PAGE CACHE RANDOM (00h-31h)

The READ PAGE CACHE RANDOM (00h-31h) command reads the specified block and
page into the data register while the previous page is output from the cache register.
This command is accepted by the die (LUN) when it is ready (RDY = 1, ARDY = 1). It is
also accepted by the die (LUN) during READ PAGE CACHE (31h, 00h-31h) operations
(RDY = 1 and ARDY = 0).
To issue this command, write 00h to the command register, then write five address cy-
cles to the address register, and conclude by writing 31h to the command register. The
column address in the address specified is ignored. The die (LUN) address must match
the same die (LUN) address as the previous READ PAGE (00h-30h) command or, if ap-
plicable, the previous READ PAGE CACHE RANDOM (00h-31h) command. There is no
restriction on the plane address.
After this command is issued, R/B# goes LOW and the die (LUN) is busy
(RDY = 0, ARDY = 0) for tRCBSY. After tRCBSY, R/B# goes HIGH and the die (LUN) is
busy with a cache operation (RDY = 1, ARDY = 0), indicating that the cache register is
available and that the specified page is copying from the NAND Flash array to the data
register. At this point, data can be output from the cache register beginning at column
address 0. The CHANGE READ COLUMN (05h-E0h) command can be used to change
the column address of the data being output from the cache register.
leaved die (multi-LUN) operations the READ STATUS ENHANCED (78h) command
followed by the READ MODE (00h) command must be used to select only one die
(LUN) and prevent bus contention.
If a MULTI-PLANE CACHE RANDOM (00h-32h, 00h-31h) command is issued after a
MULTI-PLANE READ PAGE operation (00h-32h, 00h-30h), then the addressed pages
are read into the data registers while the previous pages can be output from the cache
registers. After the die (LUN) is ready (RDY = 1, ARDY = 0), the CHANGE READ COL-
UMN ENHANCED (06h-E0h) command is used to select which cache register outputs
data.
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Read Operations
Figure 54: READ PAGE CACHE RANDOM (00h-31h) Operation
Cycle type Command Address x5 Command Command Address x5 Command DOUT DOUT DOUT Command
DQ[7:0] 00h Page Address M 30h 00h Page Address N 31h D0 … Dn 00h
tWB tR tWB tRCBSY tRR
RDY
Page M
1
Cycle type DOUT Command Address x5 Command DOUT
DQ[7:0] Dn 00h Page Address P 31h D0

tWB tRCBSY tRR
RDY
Page N
1
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Read Operations
READ PAGE CACHE LAST (3Fh)

The READ PAGE CACHE LAST (3Fh) command ends the read page cache sequence and
copies a page from the data register to the cache register. This command is accepted by
the die (LUN) when it is ready (RDY = 1, ARDY = 1). It is also accepted by the die (LUN)
during READ PAGE CACHE (31h, 00h-31h) operations (RDY = 1 and ARDY = 0).
To issue the READ PAGE CACHE LAST (3Fh) command, write 3Fh to the command reg-
ister. After this command is issued, R/B# goes LOW and the die (LUN) is busy
(RDY = 0, ARDY = 0) for tRCBSY. After tRCBSY, R/B# goes HIGH and the die (LUN) is
ready (RDY = 1, ARDY = 1). At this point, data can be output from the cache register,
beginning at column address 0. The CHANGE READ COLUMN (05h-E0h) command
can be used to change the column address of the data being output from the cache register.
In devices that have more than one LUN per target, during and following interleaved
die (multi-LUN) operations the READ STATUS ENHANCED (78h) command followed
by the READ MODE (00h) command must be used to select only one die (LUN) and
prevent bus contention.
If the READ PAGE CACHE LAST (3Fh) command is issued after a MULTI-PLANE READ
PAGE CACHE operation (31h; 00h-32h, 00h-30h), the die (LUN) goes busy until the pa-
ges are copied from the data registers to the cache registers. After the die (LUN) is ready
(RDY = 1, ARDY = 1), the CHANGE READ COLUMN ENHANCED (06h-E0h) command is
used to select which cache register outputs data.
Figure 55: READ PAGE CACHE LAST (3Fh) Operation
As defined for
READ PAGE CACHE
(SEQUENTIAL OR RANDOM)
Cycle type Command DOUT DOUT DOUT Command DOUT DOUT DOUT
DQ[7:0] 31h D0 … Dn 3Fh D0 … Dn

tWB tRCBSY tRR tWB tRCBSY tRR
RDY
Page Address N Page N
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Read Operations
READ PAGE MULTI-PLANE (00h-32h)

The READ PAGE MULTI-PLANE (00h-32h) command queues a plane to transfer data
from the NAND flash array to its cache register. This command can be issued one or
more times. Each time a new plane address is specified, that plane is also queued for
data transfer. The READ PAGE (00h-30h) command is issued to select the final plane
and to begin the read operation for all previously queued planes. All queued planes will
transfer data from the NAND Flash array to their cache registers.
To issue the READ PAGE MULTI-PLANE (00h-32h) command, write 00h to the com-
mand register, then write five address cycles to the address register, and conclude by
writing 32h to the command register. The column address in the address specified is
ignored.
After this command is issued, R/B# goes LOW and the die (LUN) is busy
(RDY = 0, ARDY = 0) for tDBSY. After tDBSY, R/B# goes HIGH and the die (LUN) is ready
(RDY = 1, ARDY = 1). At this point, the die (LUN) and block are queued for data transfer
from the array to the cache register for the addressed plane. During tDBSY, the only val-
id commands are status operations (70h, 78h) and reset commands (FFh, FCh). Follow-
ing tDBSY, to continue the MULTI-PLANE READ operation, the only valid commands
are status operations (70h, 78h), READ PAGE MULTI-PLANE (00h-32h), READ PAGE
(00h-30h), and READ PAGE CACHE RANDOM (00h-31h).
Additional READ PAGE MULTI-PLANE (00h-32h) commands can be issued to queue
additional planes for data transfer.
If the READ PAGE (00h-30h) command is used as the final command of a MULTI-
PLANE READ operation, data is transferred from the NAND Flash array for all of the
addressed planes to their respective cache registers. When the die (LUN) is ready
(RDY = 1, ARDY = 1), data output is enabled for the cache register linked to the last even
plane addressed. When the host requests data output, it begins at the column address
specified in the READ PAGE (00h-30h) command. To enable data output in the other
cache registers, use the CHANGE READ COLUMN ENHANCED (06h-E0h) command.
Additionally, the CHANGE READ COLUMN (05h-E0h) command can be used to change
the column address within the currently selected plane.
If the READ PAGE CACHE SEQUENTIAL (31h) is used as the final command of a MULTI-
PLANE READ CACHE operation, data is copied from the previously read operation from
each plane to each cache register and then data is transferred from the NAND Flash
array for all previously addressed planes to their respective data registers. When the die
(LUN) is ready (RDY = 1, ARDY = 0), data output is enabled. The CHANGE READ COL-
UMN ENHANCED (06h-E0h) command is used to determine which cache register
outputs data first. To enable data output in the other cache registers, use the CHANGE
READ COLUMN ENHANCED (06h-E0h) command. Additionally, the CHANGE READ
COLUMN (05h-E0h) command can be used to change the column address within the
currently selected plane.
If the READ PAGE CACHE RANDOM (00h-31h) command is used as the final command
of a MULTI-PLANE READ CACHE operation, data is copied from the previously read
operation from the data register to the cache register and then data is transferred from
the NAND Flash array for all of the addressed planes to their respective data registers.
When the die (LUN) is ready (RDY = 1, ARDY = 0), data output is enabled. The CHANGE
READ COLUMN ENHANCED (06h-E0h) command is used to determine which cache
register outputs data first. To enable data output in the other cache registers, use the
CHANGE READ COLUMN ENHANCED (06h-E0h) command. Additionally, the
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Read Operations
CHANGE READ COLUMN (05h-E0h) command can be used to change the column ad-
dress within the currently selected plane.
See Multi-Plane Operations for additional multi-plane addressing requirements.
Figure 56: READ PAGE MULTI-PLANE (00h-32h) Operation
Cycle type Command Address Address Address Address Address Command Command Address Address
DQ[7:0] 00h C1 C2 R1 R2 R3 32h 00h C1 ...
tWB tDBSY
RDY
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Program Operations
Program Operations
Program operations are used to move data from the cache or data registers to the
NAND array of one or more planes. During a program operation the contents of the
cache and/or data registers are modified by the internal control logic.
Within a block, pages must be programmed sequentially from the least significant page
address to the most significant page address (i.e. 0, 1, 2, 3, …). Programming pages out
of order within a block is prohibited.
Program Operations
The PROGRAM PAGE (80h-10h) command, when not preceded by the PROGRAM PAGE
MULTI-PLANE (80h-11h) command, programs one page from the cache register to the
NAND Flash array. When the die (LUN) is ready (RDY = 1, ARDY = 1), the host should
check the FAIL bit to verify that the operation has completed successfully.
Program Cache Operations
The PROGRAM PAGE CACHE (80h-15h) command can be used to improve program op-
eration system performance. When this command is issued, the die (LUN) goes busy
(RDY = 0, ARDY = 0) while the cache register contents are copied to the data register,
and the die (LUN) is busy with a program cache operation (RDY = 1, ARDY = 0). While
the contents of the data register are moved to the NAND Flash array, the cache register
is available for an additional PROGRAM PAGE CACHE (80h-15h) or PROGRAM PAGE
(80h-10h) command.
For PROGRAM PAGE CACHE-series (80h-15h) operations, during the die (LUN) busy
times, tCBSY and tLPROG, when RDY = 0 and ARDY = 0, the only valid commands are
status operations (70h, 78h) and reset (FFh, FCh). When RDY = 1 and ARDY = 0, the only
valid commands during PROGRAM PAGE CACHE-series (80h-15h) operations are sta-
tus operations (70h, 78h), PROGRAM PAGE CACHE (80h-15h), PROGRAM PAGE
(80h-10h), CHANGE WRITE COLUMN (85h), CHANGE ROW ADDRESS (85h), and reset
(FFh, FCh).
Multi-Plane Program Operations
The PROGRAM PAGE MULTI-PLANE (80h-11h) command can be used to improve pro-
gram operation system performance by enabling multiple pages to be moved from the
cache registers to different planes of the NAND Flash array. This is done by prepending
one or more PROGRAM PAGE MULTI-PLANE (80h-11h) commands in front of the PRO-
GRAM PAGE (80h-10h) command. See Multi-Plane Operations for details.
Multi-Plane Program Cache Operations
The PROGRAM PAGE MULTI-PLANE (80h-11h) command can be used to improve pro-
gram cache operation system performance by enabling multiple pages to be moved
from the cache registers to the data registers and, while the pages are being transferred
from the data registers to different planes of the NAND Flash array, free the cache regis-
ters to receive data input from the host. This is done by prepending one or more
PROGRAM PAGE MULTI-PLANE (80h-11h) commands in front of the PROGRAM PAGE
CACHE (80h-15h) command. See Multi-Plane Operations for details.
PROGRAM PAGE (80h-10h)

The PROGRAM PAGE (80h-10h) command enables the host to input data to a cache
register, and moves the data from the cache register to the specified block and page ad-
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Program Operations
dress in the array of the selected die (LUN). This command is accepted by the die (LUN)
when it is ready (RDY = 1, ARDY = 1). It is also accepted by the die (LUN) when it is busy
with a PROGRAM PAGE CACHE (80h-15h) operation (RDY = 1, ARDY = 0).
To input a page to the cache register and move it to the NAND array at the block and
page address specified, write 80h to the command register. Unless this command has
been preceded by a PROGRAM PAGE MULTI-PLANE (80h-11h) command, issuing the
80h to the command register clears all of the cache registers' contents on the selected
target. Then write five address cycles containing the column address and row address.
Data input cycles follow. Serial data is input beginning at the column address specified.
At any time during the data input cycle the CHANGE WRITE COLUMN (85h) and
CHANGE ROW ADDRESS (85h) commands may be issued. When data input is com-
plete, write 10h to the command register. The selected LUN will go busy
(RDY = 0, ARDY = 0) for tPROG as data is transferred.
signal or, alternatively, the status operations (70h, 78h) may be used. When the die
(LUN) is ready (RDY = 1, ARDY = 1), the host should check the status of the FAIL bit.
must be used to select only one die (LUN) for status output. Use of the READ STATUS
(70h) command could cause more than one die (LUN) to respond, resulting in bus con-
tention.
The PROGRAM PAGE (80h-10h) command is used as the final command of a multi-
plane program operation. It is preceded by one or more PROGRAM PAGE MULTI-
PLANE (80h-11h) commands. Data is transferred from the cache registers for all of the
addressed planes to the NAND array. The host should check the status of the operation
by using the status operations (70h, 78h). See Multi-Plane Operations for multi-plane
addressing requirements.
Figure 57: PROGRAM PAGE (80h-10h) Operation
Cycle type Command Address Address Address Address Address DIN DIN DIN DIN Command Command DOUT
tADL
DQ[7:0] 80h C1 C2 R1 R2 R3 D0 D1 … Dn 10h 70h Status

tWB tPROG
RDY
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Program Operations
PROGRAM PAGE CACHE (80h-15h)

The PROGRAM PAGE CACHE (80h-15h) command enables the host to input data to a
cache register; copies the data from the cache register to the data register; then moves
the data register contents to the specified block and page address in the array of the
selected die (LUN). After the data is copied to the data register, the cache register is avail-
able for additional PROGRAM PAGE CACHE (80h-15h) or PROGRAM PAGE (80h-10h)
commands. The PROGRAM PAGE CACHE (80h-15h) command is accepted by the die
(LUN) when it is ready (RDY =1, ARDY = 1). It is also accepted by the die (LUN) when
busy with a PROGRAM PAGE CACHE (80h-15h) operation (RDY = 1, ARDY = 0).
To input a page to the cache register to move it to the NAND array at the block and page
address specified, write 80h to the command register. Unless this command has been
preceded by a PROGRAM PAGE MULTI-PLANE (80h-11h) command, issuing the 80h to
the command register clears all of the cache registers' contents on the selected target.
Then write five address cycles containing the column address and row address. Data
input cycles follow. Serial data is input beginning at the column address specified. At
any time during the data input cycle the CHANGE WRITE COLUMN (85h) and
CHANGE ROW ADDRESS (85h) commands may be issued. When data input is com-
plete, write 15h to the command register. The selected LUN will go busy
(RDY = 0, ARDY = 0) for tCBSY to allow the data register to become available from a
previous program cache operation, to copy data from the cache register to the data reg-
ister, and then to begin moving the data register contents to the specified page and
block address.
To determine the progress of tCBSY, the host can monitor the target's R/B# signal or,
alternatively, the status operations (70h, 78h) can be used. When the LUN’s status
shows that it is busy with a PROGRAM CACHE operation (RDY = 1, ARDY = 0), the host
should check the status of the FAILC bit to see if a previous cache operation was successful.
If, after tCBSY, the host wants to wait for the program cache operation to complete, with-
out issuing the PROGRAM PAGE (80h-10h) command, the host should monitor ARDY
until it is 1. The host should then check the status of the FAIL and FAILC bits.
In devices with more than one die (LUN) per target, during and following interleaved
die (multi-LUN) operations, the READ STATUS ENHANCED (78h) command must be
used to select only one die (LUN) for status output. Use of the READ STATUS (70h) com-
mand could cause more than one die (LUN) to respond, resulting in bus contention.
The PROGRAM PAGE CACHE (80h-15h) command is used as the final command of a
multi-plane program cache operation. It is preceded by one or more PROGRAM PAGE
MULTI-PLANE (80h-11h) commands. Data for all of the addressed planes is transferred
from the cache registers to the corresponding data registers, then moved to the NAND
Flash array. The host should check the status of the operation by using the status opera-
tions (70h, 78h). See Multi-Plane Operations for multi-plane addressing requirements.
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Program Operations
Figure 58: PROGRAM PAGE CACHE (80h–15h) Operation (Start)
Cycle type Command Address Address Address Address Address Din Din Din Din Command
tADL
DQ[7:0] 80h C1 C2 R1 R2 R3 D0 D1 … Dn 15h

tWB tCBSY
RDY
tADL
DQ[7:0]
80h C1 C2 R1 R2 R3 D0 D1 … Dn 15h
tWB tCBSY
RDY
Figure 59: PROGRAM PAGE CACHE (80h–15h) Operation (End)
As defined for
PAGE CACHE PROGRAM
tADL
DQ[7:0] 80h C1 C2 R1 R2 R3 D0 D1 … Dn 15h

tWB tCBSY
RDY
tADL
DQ[7:0] 80h C1 C2 R1 R2 R3 D0 D1 … Dn 10h

tWB tLPROG
RDY
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Program Operations
PROGRAM PAGE MULTI-PLANE (80h-11h)

The PROGRAM PAGE MULTI-PLANE (80h-11h) command enables the host to input da-
ta to the addressed plane's cache register and queue the cache register to ultimately be
moved to the NAND Flash array. This command can be issued one or more times. Each
time a new plane address is specified that plane is also queued for data transfer. To in-
put data for the final plane and to begin the program operation for all previously
queued planes, issue either the PROGRAM PAGE (80h-10h) command or the PROGRAM
PAGE CACHE (80h-15h) command. All of the queued planes will move the data to the
NAND Flash array. This command is accepted by the die (LUN) when it is ready
(RDY = 1).
To input a page to the cache register and queue it to be moved to the NAND Flash array
at the block and page address specified, write 80h to the command register. Unless this
command has been preceded by an 11h command, issuing the 80h to the command
register clears all of the cache registers' contents on the selected target. Write five ad-
dress cycles containing the column address and row address; data input cycles follow.
Serial data is input beginning at the column address specified. At any time during the
data input cycle, the CHANGE WRITE COLUMN (85h) and CHANGE ROW ADDRESS
(85h) commands can be issued. When data input is complete, write 11h to the com-
mand register. The selected die (LUN) will go busy (RDY = 0, ARDY = 0) for tDBSY.
To determine the progress of tDBSY, the host can monitor the target's R/B# signal or,
alternatively, the status operations (70h, 78h) can be used. When the LUN's status
shows that it is ready (RDY = 1), additional PROGRAM PAGE MULTI-PLANE (80h-11h)
commands can be issued to queue additional planes for data transfer. Alternatively, the
PROGRAM PAGE (80h-10h) or PROGRAM PAGE CACHE (80h-15h) commands can be
issued.
When the PROGRAM PAGE (80h-10h) command is used as the final command of a multi-
plane program operation, data is transferred from the cache registers to the NAND
Flash array for all of the addressed planes during tPROG. When the die (LUN) is ready
(RDY = 1, ARDY = 1), the host should check the status of the FAIL bit for each of the
planes to verify that programming completed successfully.
When the PROGRAM PAGE CACHE (80h-15h) command is used as the final command
of a MULTI-PLANE PROGRAM CACHE operation, data is transferred from the cache
registers to the data registers after the previous array operations finish. The data is then
moved from the data registers to the NAND Flash array for all of the addressed planes.
This occurs during tCBSY. After tCBSY, the host should check the status of the FAILC bit
for each of the planes from the previous program cache operation, if any, to verify that
programming completed successfully.
For the PROGRAM PAGE MULTI-PLANE (80h-11h), PROGRAM PAGE (80h-10h), and
PROGRAM PAGE CACHE (80h-15h) commands, see Multi-Plane Operations for multi-
plane addressing requirements.
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Program Operations
Figure 60: PROGRAM PAGE MULTI-PLANE (80h–11h) Operation
Cycle type Command Address Address Address Address Address DIN DIN DIN Command Command Address
tADL
DQ[7:0] 80h C1 C2 R1 R2 R3 D0 … Dn 11h 80h ...
tWB tDBSY
RDY
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Erase Operations
Erase Operations
Erase operations are used to clear the contents of a block in the NAND Flash array to
prepare its pages for program operations.
Erase Operations
The ERASE BLOCK (60h-D0h) command, when not preceded by the ERASE BLOCK MUL-
TI-PLANE (60h-D1h) command, erases one block in the NAND Flash array. When the
die (LUN) is ready (RDY = 1, ARDY = 1), the host should check the FAIL bit to verify that
this operation completed successfully.
MULTI-PLANE ERASE Operations
The ERASE BLOCK MULTI-PLANE (60h-D1h) command can be used to further system
performance of erase operations by allowing more than one block to be erased in the
NAND array. This is done by prepending one or more ERASE BLOCK MULTI-PLANE (60h-
D1h) commands in front of the ERASE BLOCK (60h-D0h) command. See Multi-Plane
Operations for details.
ERASE BLOCK (60h-D0h)

The ERASE BLOCK (60h-D0h) command erases the specified block in the NAND Flash
array. This command is accepted by the die (LUN) when it is ready (RDY = 1, ARDY = 1).
To erase a block, write 60h to the command register. Then write three address cycles
containing the row address; the page address is ignored. Conclude by writing D0h to
the command register. The selected die (LUN) will go busy (RDY = 0, ARDY = 0) for
tBERS while the block is erased.
To determine the progress of an ERASE operation, the host can monitor the target's R/
B# signal, or alternatively, the status operations (70h, 78h) can be used. When the die
(LUN) is ready (RDY = 1, ARDY = 1) the host should check the status of the FAIL bit.
must be used to select only one die (LUN) for status output. Use of the READ STATUS
(70h) command could cause more than one die (LUN) to respond, resulting in bus con-
tention.
The ERASE BLOCK (60h-D0h) command is used as the final command of a MULTI-
PLANE ERASE operation. It is preceded by one or more ERASE BLOCK MULTI-PLANE
(60h-D1h) commands. All of blocks in the addressed planes are erased. The host should
check the status of the operation by using the status operations (70h, 78h). See Multi-
Plane Operations for multi-plane addressing requirements.
Figure 61: ERASE BLOCK (60h-D0h) Operation
Cycle type Command Address Address Address Command
DQ[7:0] 60h R1 R2 R3 D0h

tWB tBERS
SR[6]
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Erase Operations
ERASE BLOCK MULTI-PLANE (60h-D1h)

The ERASE BLOCK MULTI-PLANE (60h-D1h) command queues a block in the specified
plane to be erased in the NAND Flash array. This command can be issued one or more
times. Each time a new plane address is specified, that plane is also queued for a block
to be erased. To specify the final block to be erased and to begin the ERASE operation
for all previously queued planes, issue the ERASE BLOCK (60h-D0h) command. This
command is accepted by the die (LUN) when it is ready (RDY = 1, ARDY = 1).
To queue a block to be erased, write 60h to the command register, then write three ad-
dress cycles containing the row address; the page address is ignored. Conclude by
writing D1h to the command register. The selected die (LUN) will go busy (RDY = 0,
ARDY = 0) for tDBSY.
To determine the progress of tDBSY, the host can monitor the target's R/B# signal, or
alternatively, the status operations (70h, 78h) can be used. When the LUN's status
shows that it is ready (RDY = 1, ARDY = 1), additional ERASE BLOCK MULTI-PLANE (60h-
D1h) commands can be issued to queue additional planes for erase. Alternatively, the
ERASE BLOCK (60h-D0h) command can be issued to erase all of the queued blocks.
For multi-plane addressing requirements for the ERASE BLOCK MULTI-PLANE (60h-
D1h) and ERASE BLOCK (60h-D0h) commands, see Multi-Plane Operations.
Figure 62: ERASE BLOCK MULTI-PLANE (60h–D1h) Operation
Cycle type Command Address Address Address Command Command Address
DQ[7:0] 60h R1 R2 R3 D1h 60h ...

tWB tDBSY
RDY
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Copyback Operations
Copyback Operations
COPYBACK operations make it possible to transfer data within a plane from one page to
another using the cache register. This is particularly useful for block management and
wear leveling.
The COPYBACK operation is a two-step process consisting of a COPYBACK READ
(00h-35h) and a COPYBACK PROGRAM (85h-10h) command. To move data from one
page to another on the same plane, first issue the COPYBACK READ (00h-35h) com-
mand. When the die (LUN) is ready (RDY = 1, ARDY = 1), the host can transfer the data
to a new page by issuing the COPYBACK PROGRAM (85h-10h) command. When the die
(LUN) is again ready (RDY = 1, ARDY = 1), the host should check the FAIL bit to verify
that this operation completed successfully.
To prevent bit errors from accumulating over multiple COPYBACK operations, it is rec-
ommended that the host read the data out of the cache register after the COPYBACK
READ (00h-35h) completes prior to issuing the COPYBACK PROGRAM (85h-10h) com-
mand. The CHANGE READ COLUMN (05h-E0h) command can be used to change the
column address. The host should check the data for ECC errors and correct them. When
the COPYBACK PROGRAM (85h-10h) command is issued, any corrected data can be in-
put. The CHANGE ROW ADDRESS (85h) command can be used to change the column
address.
It is not possible to use the COPYBACK operation to move data from one plane to anoth-
er or from one die (LUN) to another. Instead, use a READ PAGE (00h-30h) or COPY-
BACK READ (00h-35h) command to read the data out of the NAND, and then use a
PROGRAM PAGE (80h-10h) command with data input to program the data to a new
plane or die (LUN).
Between the COPYBACK READ (00h-35h) and COPYBACK PROGRAM (85h-10h) com-
mands, the following commands are supported: status operations (70h, 78h), and
column address operations (05h-E0h, 06h-E0h, 85h). Reset operations (FFh, FCh) can
be issued after COPYBACK READ (00h-35h), but the contents of the cache registers on
the target are not valid.
In devices which have more than one die (LUN) per target, once the COPYBACK READ
(00h-35h) is issued, interleaved die (multi-LUN) operations are prohibited until after
the COPYBACK PROGRAM (85h-10h) command is issued.
Multi-Plane Copyback Operations
Multi-plane copyback read operations improve read data throughput by copying data
simultaneously from more than one plane to the specified cache registers. This is done
by prepending one or more READ PAGE MULTI-PLANE (00h-32h) commands in front
of the COPYBACK READ (00h-35h) command.
The COPYBACK PROGRAM MULTI-PLANE (85h-11h) command can be used to further
system performance of COPYBACK PROGRAM operations by enabling movement of
multiple pages from the cache registers to different planes of the NAND Flash array.
This is done by prepending one or more COPYBACK PROGRAM (85h-11h) commands
in front of the COPYBACK PROGRAM (85h-10h) command. See Multi-Plane Operations
for details.
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Copyback Operations
COPYBACK READ (00h-35h)

The COPYBACK READ (00h-35h) command is functionally identical to the READ PAGE
(00h-30h) command, except that 35h is written to the command register instead of 30h.
See READ PAGE (00h-30h) (page 84) for further details.
Though it is not required, it is recommended that the host read the data out of the de-
vice to verify the data prior to issuing the COPYBACK PROGRAM (85h-10h) command
to prevent the propagation of data errors.
Figure 63: COPYBACK READ (00h-35h) Operation
DQ[7:0] 00h C1 C2 R1 R2 R3 35h Dn Dn+1 Dn+2

tWB tR tRR
RDY
Figure 64: COPYBACK READ (00h–35h) with CHANGE READ COLUMN (05h–E0h) Operation
DQ[7:0] 00h C1 C2 R1 R2 R3 35h D0 … Dj + n

tWB tR tRR
RDY
Cycle type Command Address Address Command DOUT DOUT DOUT

tCCS
DQ[7:0] 05h C1 C2 E0h Dk Dk + 1 Dk + 2
RDY
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Copyback Operations
COPYBACK PROGRAM (85h–10h)

The COPYBACK PROGRAM (85h-10h) command is functionally identical to the PRO-
GRAM PAGE (80h-10h) command, except that when 85h is written to the command
register, cache register contents are not cleared. See PROGRAM PAGE (80h-10h) for fur-
ther details.
Figure 65: COPYBACK PROGRAM (85h–10h) Operation
Cycle type Command Address Address Address Address Address Command
DQ[7:0] 85h C1 C2 R1 R2 R3 10h

tWB tPROG
RDY
Figure 66: COPYBACK PROGRAM (85h-10h) with CHANGE WRITE COLUMN (85h) Operation
Cycle type Command Address Address Address Address Address DIN DIN
tADL
DQ[7:0] 85h C1 C2 R1 R2 R3 Di Di + 1
RDY
Cycle type Command Address Address DIN DIN DIN Command

tCCS
DQ[7:0] 85h C1 C2 Dj Dj + 1 Dj + 2 10h

tWB tPROG
RDY
COPYBACK READ MULTI-PLANE (00h-32h)

The COPYBACK READ MULTI-PLANE (00h-32h) command is functionally identical to
the READ PAGE MULTI-PLANE (00h-32h) command, except that the 35h command is
written as the final command. The complete command sequence for the COPYBACK
READ PAGE MULTI-PLANE is 00h-32h-00h-35h. See READ PAGE MULTI-PLANE
(00h-32h) (page 89) for further details.
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Copyback Operations
COPYBACK PROGRAM MULTI-PLANE (85h-11h)

The COPYBACK PROGRAM MULTI-PLANE (85h-11h) command is functionally identi-
cal to the PROGRAM PAGE MULTI-PLANE (80h-11h) command, except that when 85h
is written to the command register, cache register contents are not cleared. See PRO-
GRAM PAGE MULTI-PLANE (80h-11h) for further details.
Figure 67: COPYBACK PROGRAM MULTI-PLANE (85h-11h) Operation
Cycle type Command Address Address Address Address Address DIN DIN DIN Command Command Address
tADL
DQ[7:0] 85h C1 C2 R1 R2 R3 D0 … Dn 11h 85h ...

tWB tDBSY
RDY
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One-Time Programmable (OTP) Operations

This Micron NAND Flash device offers a protected, one-time programmable NAND
Flash memory area. Each target has a an OTP area with a range of OTP pages (see Ta-
ble 15 (page 104)); the entire range is guaranteed to be good. Customers can use the
OTP area in any way they desire; typical uses include programming serial numbers or
other data for permanent storage.
The OTP area leaves the factory in an erased state (all bits are 1). Programming an OTP
page changes bits that are 1 to 0, but cannot change bits that are 0 to 1. The OTP area
cannot be erased, even if it is not protected. Protecting the OTP area prevents further
programming of the pages in the OTP area.
Enabling the OTP Operation Mode
The OTP area is accessible while the OTP operation mode is enabled. To enable OTP
operation mode, issue the SET FEATURES (EFh) command to feature address 90h and
write 01h to P1, followed by three cycles of 00h to P2 through P4.
When the target is in OTP operation mode, all subsequent PAGE READ (00h-30h) and
PROGRAM PAGE (80h-10h) commands are applied to the OTP area.
ERASE commands are not valid while the target is in OTP operation mode.
Programming OTP Pages
Each page in the OTP area is programming using tthe PROGRAM OTP PAGE (80h-10h)
command. Each page can be programmed more than once, in sections, up to the maxi-
mum number allowed (see NOP in Table 15 (page 104)). The pages in the OTP area
must be programmed in ascending order.
If the host issues a PAGE PROGRAM (80h-10h) command to an address beyond the max-
imum page-address range, the target will be busy for tOBSY and the WP# status register
bit will be 0, meaning that the page is write-protected.
Protecting the OTP Area
To protect the OTP area, issue the OTP PROTECT (80h-10h) command to the OTP Pro-
tect Page. When the OTP area is protected it cannot be programmed further. It is not
possible to unprotect the OTP area after it has been protected.
Reading OTP Pages
To read pages in the OTP area, whether the OTP area is protected or not, issue the PAGE
READ (00h-30h) command.
If the host issues the PAGE READ (00h-30h) command to an address beyond the maxi-
mum page-address range, the data output will not be valid. To determine whether the
target is busy during an OTP operation, either monitor R/B# or use the READ STATUS
(70h) command. Use of the READ STATUS ENHANCED (78h) command is prohibited
while the OTP operation is in progress.
Returning to Normal Array Operation Mode
To exit OTP operation mode and return to normal array operation mode, issue the SET
FEATURES (EFh) command to feature address 90h and write 00h to P1 through P4.
If the RESET (FFh) command is issued while in OTP operation mode, the target will exit
OTP operation mode and enter normal operating mode. If the synchronous interface is
active, the target will exit OTP operation and enable the asynchronous interface.
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If the SYNCHRONOUS RESET (FCh) command is issued while in the OTP operation
mode, the target will exit OTP operation mode and the synchronous interface remains
active.
Table 15: OTP Area Details
Description Value
Number of OTP pages 30
OTP protect page address 01h
OTP start page address 02h
Number of partial page programs (NOP) to each OTP page 4
PROGRAM OTP PAGE (80h-10h)

The PROGRAM OTP PAGE (80h-10h) command is used to write data to the pages within
the OTP area. To program data in the OTP area, the target must be in OTP operation mode.
To use the PROGRAM OTP PAGE (80h-10h) command, issue the 80h command. Issue
five address cycles including the column address, the page address within the OTP page
range, and a block address of 0. Next, write the data to the cache register using data
input cycles. After data input is complete, issue the 10h command.
R/B# goes LOW for the duration of the array programming time, tPROG. The READ STA-
TUS (70h) command is the only valid command for reading status in OTP operation
mode. The RDY bit of the status register will reflect the state of R/B#. Use of the READ
STATUS ENHANCED (78h) command is prohibited.
When the target is ready, read the FAIL bit of the status register to determine whether
the operation passed or failed (see Status Operations).
The PROGRAM OTP PAGE (80h-10h) command also accepts the CHANGE WRITE COL-
UMN (85h) command during data input.
If a PROGRAM PAGE command is issued to the OTP area after the area has been protec-
ted, then R/B# goes LOW for tOBSY. After tOBSY, the status register is set to 60h.
Figure 68: PROGRAM OTP PAGE (80h-10h) Operation
Cycle type Command Address Address Address Address Address Din Din Din Command Command Dout
tADL tWHR
DQ[7:0] 80h C1 C2 OTP Page 00h 00h D1 … Dn 10h 70h Status

tWB tPROG
R/B#
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Figure 69: PROGRAM OTP PAGE (80h-10h) with CHANGE WRITE COLUMN (85h) Operation
Cycle type Command Address Address Address Address Address Din Din Din Command
tADL
DQ[7:0] 80h C1 C2 OTP Page 00h 00h Dn … Dm 85h
R/B#
Cycle type Command Address Address Din Din Din Command Command Dout
tCCS tWHR
DQ[7:0] 85h C1 C2 Dp … Dr 10h 70h Status

tWB tPROG
R/B#
PROTECT OTP AREA (80h-10h)

The PROTECT OTP AREA (80h-10h) command is used to prevent further programming
of the pages in the OTP area. The protect the OTP area, the target must be in OTP opera-
tion mode.
To protect all data in the OTP area, issue the 80h command. Issue five address cycles
including the column address, OTP protect page address and block address; the column
and block addresses are fixed to 0. Next, write 00h data for the first byte location and
issue the 10h command.
R/B# goes LOW for the duration of the array programming time, tPROG. The READ STA-
TUS (70h) command is the only valid command for reading status in OTP operation
mode. The RDY bit of the status register will reflect the state of R/B#. Use of the READ
STATUS ENHANCED (78h) command is prohibited.
When the target is ready, read the FAIL bit of the status register to determine if the oper-
ation passed or failed (see Status Operations).
If the PROTECT OTP AREA (80h-10h) command is issued after the OTP area has already
been protected, R/B# goes LOW for tOBSY. After tOBSY, the status register is set to 60h.
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Figure 70: PROTECT OTP AREA (80h-10h) Operation
Cycle type Command Address Address Address Address Address Din Command Command Dout
tADL tWHR
DQ[7:0] 80h 00h 00h 01h 00h 00h 00h 10h 70h Status
tWB tPROG
R/B#
Note: 1. OTP data is protected following a status confirmation.
READ OTP PAGE (00h-30h)

The READ OTP PAGE (00h-30h) command is used to read data from the pages in the
OTP area. To read data in the OTP area, the target must be in OTP operation mode.
To use the READ OTP PAGE (00h-30h) command, issue the 00h command. Issue five
address cycles including the column address, the page address within the OTP page
range, and a block address of 0. Next, issue the 30h command. The selected die (LUN)
will go busy (RDY = 0, ARDY = 0) for tR as data is transferred.
signal, or alternatively the READ STATUS (70h) command can be used. If the status op-
erations are used to monitor the die’s (LUN's) status, when the die (LUN) is ready (RDY
= 1, ARDY = 1) the host disables status output and enables data output by issuing the
READ MODE (00h) command. When the host requests data output, it begins at the col-
umn address specified.
Additional pages within the OTP area can be read by repeating the READ OTP PAGE
(00h-30h) command.
The READ OTP PAGE (00h-30h) command is compatible with the CHANGE READ COL-
UMN (05h-E0h) command. Use of the READ STATUS ENHANCED (78h) and CHANGE
READ COLUMN ENHANCED (06h-E0h) commands are prohibited.
Figure 71: READ OTP PAGE (00h-30h) Operation
Cycle type Command Address Address Address Address Address Command Dout Dout Dout
DQ[7:0] 00h C1 C2 OTP Page 00h 00h 30h Dn Dn+1 Dn+2

tWB tR tRR
R/B#
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Multi-Plane Operations
Multi-Plane Operations
Each NAND Flash logical unit (LUN) is divided into multiple physical planes. Each
plane contains a cache register and a data register independent of the other planes. The
planes are addressed via the low-order block address bits. Specific details are provided
in Device and Array Organization.
Multi-plane operations make better use of the NAND Flash arrays on these physical
planes by performing concurrent READ, PROGRAM, or ERASE operations on multiple
planes, significantly improving system performance. Multi-plane operations must be of
the same type across the planes; for example, it is not possible to perform a PROGRAM
operation on one plane with an ERASE operation on another.
When issuing MULTI-PLANE PROGRAM or ERASE operations, use the READ STATUS
(70h) command and check whether the previous operation(s) failed. If the READ STA-
TUS (70h) command indicates that an error occurred (FAIL = 1 and/or FAILC = 1), use
the READ STATUS ENHANCED (78h) command—time for each plane—to determine
which plane operation failed.
Multi-Plane Addressing
Multi-plane commands require an address per operational plane. For a given multi-
plane operation, these addresses are subject to the following requirements:
• The LUN address bit(s) must be identical for all of the issued addresses.
• The plane select bit, BA[8], must be different for each issued address.
• The page address bits, PA[7:0], must be identical for each issued address.
The READ STATUS (70h) command should be used following MULTI-PLANE PRO-
GRAM PAGE and ERASE BLOCK operations on a single die (LUN).
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Interleaved Die (Multi-LUN) Operations
Interleaved Die (Multi-LUN) Operations

In devices that have more than one die (LUN) per target, it is possible to improve per-
formance by interleaving operations between the die (LUNs). An interleaved die (multi-
LUN) operation is one that is issued to an idle die (LUN) (RDY = 1) while another die
(LUN) is busy (RDY = 0).
Interleaved die (multi-LUN) operations are prohibited following RESET (FFh, FCh), iden-
tification (90h, ECh, EDh), and configuration (EEh, EFh) operations until ARDY =1 for
all of the die (LUNs) on the target.
During an interleaved die (multi-LUN) operation, there are two methods to determine
operation completion. The R/B# signal indicates when all of the die (LUNs) have finish-
ed their operations. R/B# remains LOW while any die (LUN) is busy. When R/B# goes
HIGH, all of the die (LUNs) are idle and the operations are complete. Alternatively, the
READ STATUS ENHANCED (78h) command can report the status of each die (LUN) in-
dividually.
If a die (LUN) is performing a cache operation, like PROGRAM PAGE CACHE (80h-15h),
then the die (LUN) is able to accept the data for another cache operation when status
register bit 6 is 1. All operations, including cache operations, are complete on a die
when status register bit 5 is 1.
Use the READ STATUS ENHANCED (78h) command to monitor status for the ad-
dressed die (LUN). When multi-plane commands are used with interleaved die (multi-
LUN) operations, the multi-plane commands must also meet the requirements, see Multi-
Plane Operations for details. After the READ STATUS ENHANCED (78h) command has
been issued, the READ STATUS (70h) command may be issued for the previously ad-
dressed die (LUN).
See Command Definitions for the list of commands that can be issued while other die
(LUNs) are busy.
During an interleaved die (multi-LUN) operation that involves a PROGRAM-series
(80h-10h, 80h-15h, 80h-11h) operation and a READ operation, the PROGRAM-series op-
eration must be issued before the READ-series operation. The data from the READ-
series operation must be output to the host before the next PROGRAM-series operation
is issued. This is because the 80h command clears the cache register contents of all
cache registers on all planes.
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Error Management
Error Management
Each NAND Flash die (LUN) is specified to have a minimum number of valid blocks
(NVB) of the total available blocks. This means the die (LUNs) could have blocks that
are invalid when shipped from the factory. An invalid block is one that contains at least
one page that has more bad bits than can be corrected by the minimum required ECC.
Additional blocks can develop with use. However, the total number of available blocks
per die (LUN) will not fall below NVB during the endurance life of the product.
Although NAND Flash memory devices could contain bad blocks, they can be used
quite reliably in systems that provide bad-block management and error-correction algo-
rithms. This type of software environment ensures data integrity.
Internal circuitry isolates each block from other blocks, so the presence of a bad block
does not affect the operation of the rest of the NAND Flash array.
NAND Flash devices are shipped from the factory erased. The factory identifies invalid
blocks before shipping by attempting to program the bad-block mark into every loca-
tion in the first page of each invalid block. It may not be possible to program every
location with the bad-block mark. However, the first spare area location in each bad
block is guaranteed to contain the bad-block mark. This method is compliant with ON-
FI Factory Defect Mapping requirements. See the following table for the first spare area
location and the bad-block mark.
System software should check the first spare area location on the first page of each
block prior to performing any PROGRAM or ERASE operations on the NAND Flash de-
vice. A bad block table can then be created, enabling system software to map around
these areas. Factory testing is performed under worst-case conditions. Because invalid
blocks could be marginal, it may not be possible to recover this information if the block
is erased.
Over time, some memory locations may fail to program or erase properly. In order to
ensure that data is stored properly over the life of the NAND Flash device, the following
precautions are required:
• Always check status after a PROGRAM or ERASE operation
• Under typical conditions, use the minimum required ECC (see table below)
• Use bad-block management and wear-leveling algorithms
The first block (physical block address 00h) for each CE# is guaranteed to be valid with
ECC when shipped from the factory.
Table 16: Error Management Details
Description Requirement
Minimum number of valid blocks (NVB) per LUN 3996
Total available blocks per LUN 4096
First spare area location Byte 8192
Bad-block mark 00h
Minimum required ECC 24-bit ECC per 1080 bytes of data
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Shared Pages
Shared Pages
In MLC NAND Flash devices, each memory cell contains two bits of data. These bits are
distributed across two NAND pages. Pages within a NAND block that share the same
NAND memory cells are referred to as shared pages. If any program operation is inter-
rupted (for example, power loss or reset), data in previously programmed shared pages
can also be corrupted.
Table 17: Shared Pages
Shared Pages Shared Pages

0 4 126 132
1 5 127 133
2 8 130 136
3 9 131 137
6 12 134 140
7 13 135 141
10 16 138 144
11 17 139 145
14 20 142 148
15 21 143 149
18 24 146 152
19 25 147 153
22 28 150 156
23 29 151 157
26 32 154 160
27 33 155 161
30 36 158 164
31 37 159 165
34 40 162 168
35 41 163 169
38 44 166 172
39 45 167 173
42 48 170 176
43 49 171 177
46 52 174 180
47 53 175 181
50 56 178 184
51 57 179 185
54 60 182 188
55 61 183 189
58 64 186 192
59 65 187 193
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Shared Pages
Table 17: Shared Pages (Continued)
Shared Pages Shared Pages

62 68 190 196
63 69 191 197
66 72 194 200
67 73 195 201
70 76 198 204
71 77 199 205
74 80 202 208
75 81 203 209
78 84 206 212
79 85 207 213
82 88 210 216
83 89 211 217
86 92 214 220
87 93 215 221
90 96 218 224
91 97 219 225
94 100 222 228
95 101 223 229
98 104 226 232
99 105 227 233
102 108 230 236
103 109 231 237
106 112 234 240
107 113 235 241
110 116 238 244
111 117 239 245
114 120 242 248
115 121 243 249
118 124 246 252
119 125 247 253
122 128 250 254
123 129 251 255
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Output Drive Impedance

Because NAND Flash is designed for use in systems that are typically point-to-point con-
nections, an option to control the drive strength of the output buffers is provided. Drive
strength should be selected based on the expected loading of the memory bus. There
are four supported settings for the output drivers: overdrive 2, overdrive 1, nominal,
and underdrive.
The nominal output drive strength setting is the power-on default value. The host can
select a different drive strength setting using the SET FEATURES (EFh) command.
The output impedance range from minimum to maximum covers process, voltage, and
temperature variations. Devices are not guaranteed to be at the nominal line.
Table 18: Output Drive Strength Test Conditions (VCCQ = 1.7–1.95V)
Range Process Voltage Temperature

Maximum Fast-Fast 1.95V –25°C
Nominal Typical-Typical 1.8V +25°C
Minimum Slow-Slow 1.7V +85°C
Table 19: Output Drive Strength Impedance Values (VCCQ = 1.7–1.95V)
Output
Strength Rpd/Rpu VOUT to VSSQ Minimum Nominal Maximum Unit
Overdrive 2 Rpd VCCQ × 0.2 7.5 13.5 34 ohms
VCCQ × 0.5 9 18 31 ohms
VCCQ × 0.8 11 23.5 44 ohms
Rpu VCCQ × 0.2 11 23.5 44 ohms
VCCQ × 0.5 9 18 31 ohms
VCCQ × 0.8 7.5 13.5 34 ohms
Overdrive 1 Rpd VCCQ × 0.2 10.5 19 47 ohms
VCCQ × 0.5 13 25 44 ohms
VCCQ × 0.8 16 32.5 61.5 ohms
Rpu VCCQ × 0.2 16 32.5 61.5 ohms
VCCQ × 0.5 13 25 44 ohms
VCCQ × 0.8 10.5 19 47 ohms
Nominal Rpd VCCQ × 0.2 15 27 66.5 ohms
VCCQ × 0.5 18 35 62.5 ohms
VCCQ × 0.8 22 52 88 ohms
Rpu VCCQ × 0.2 22 52 88 ohms
VCCQ × 0.5 18 35 62.5 ohms
VCCQ × 0.8 15 27 66.5 ohms
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Table 19: Output Drive Strength Impedance Values (VCCQ = 1.7–1.95V) (Con-
tinued)
Output
Underdrive Rpd VCCQ × 0.2 21.5 39 95 ohms
VCCQ × 0.5 26 50 90 ohms
VCCQ × 0.8 31.5 66.5 126.5 ohms
Rpu VCCQ × 0.2 31.5 66.5 126.5 ohms
VCCQ × 0.5 26 50 90 ohms
VCCQ × 0.8 21.5 39 95 ohms
Table 20: Output Drive Strength Conditions (VCCQ = 2.7–3.6V)
Range Process Voltage Temperature

Maximum Fast-Fast 3.6V –40°C
Nominal Typical-Typical 3.3V +25°C
Minimum Slow-Slow 2.7V +85°C
Table 21: Output Drive Strength Impedance Values (VCCQ = 2.7–3.6V)
Output
Overdrive 2 Rpd VCCQ X 0.2 7.0 16.2 28.7 ohms
VCCQ X 0.5 9.0 18.0 36.0 ohms
VCCQ X 0.8 11.8 21.0 50.0 ohms
Rpu VCCQ X 0.2 11.8 21.0 50.0 ohms
VCCQ X 0.5 9.0 18.0 36.0 ohms
VCCQ X 0.8 7.0 14.0 28.7 ohms
Overdrive 1 Rpd VCCQ X 0.2 9.3 22.3 40.0 ohms
VCCQ X 0.5 12.6 25.0 50.0 ohms
VCCQ X 0.8 16.3 29.0 68.0 ohms
Rpu VCCQ X 0.2 16.3 29.0 68.0 ohms
VCCQ X 0.5 12.6 25.0 50.0 ohms
VCCQ X 0.8 9.3 19.0 40.0 ohms
Nominal Rpd VCCQ X 0.2 12.8 32.0 58.0 ohms
VCCQ X 0.5 18.0 35.0 70.0 ohms
VCCQ X 0.8 23.0 40.0 95.0 ohms
Rpu VCCQ X 0.2 23.0 40.0 95.0 ohms
VCCQ X 0.5 18.0 35.0 70.0 ohms
VCCQ X 0.8 12.8 32.0 58.0 ohms
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Table 21: Output Drive Strength Impedance Values (VCCQ = 2.7–3.6V) (Contin-
ued)
Output
Underdrive Rpd VCCQ X 0.2 18.4 45.0 80.0 ohms
VCCQ X 0.5 25.0 50.0 100.0 ohms
VCCQ X 0.8 32.0 57.0 136.0 ohms
Rpu VCCQ X 0.2 32.0 57.0 136.0 ohms
VCCQ X 0.5 25.0 50.0 100.0 ohms
VCCQ X 0.8 18.4 45.0 80.0 ohms
Table 22: Pull-Up and Pull-Down Output Impedance Mismatch
Drive Strength Minimum Maximum Unit Notes

Overdrive 2 0 6.3 ohms 1, 2
Overdrive 1 0 8.8 ohms 1, 2
Nominal 0 12.3 ohms 1, 2
Underdrive 0 17.5 ohms 1, 2
Notes: 1. Mismatch is the absolute value between pull-up and pull-down impedances. Both are
measured at the same temperature and voltage.
2. Test conditions: VCCQ = VCCQ (MIN), VOUT = VCCQ × 0.5, TA = TOPER.
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AC Overshoot/Undershoot Specifications
AC Overshoot/Undershoot Specifications
The supported AC overshoot and undershoot area depends on the timing mode selec-
ted by the host.
Table 23: Overshoot/Undershoot Parameters
Timing Mode
Parameter 0 1 2 3 4 5 Unit
Maximum peak amplitude provided for 1 1 1 1 1 1 V
overshoot area
Maximum peak amplitude provided for 1 1 1 1 1 1 V
undershoot area
Maximum overshoot area above VCCQ 3 3 3 2.25 1.8 1.5 V-ns
Maximum undershoot area below VSSQ 3 3 3 2.25 1.8 1.5 V-ns
Figure 72: Overshoot

Volts (V)
Maximum amplitude
Overshoot area
VCCQ
Time (ns)
Figure 73: Undershoot

Volts (V)
Maximum amplitude
VSSQ
Undershoot area
Time (ns)
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Synchronous Input Slew Rate
Synchronous Input Slew Rate

Though all AC timing parameters are tested with a nominal input slew rate of 1 V/ns, it
is possible to run the device at a slower slew rate. The input slew rates shown below are
sampled, and not 100% tested. When using slew rates slower than the minimum values,
timing must be derated by the host.
Table 24: Test Conditions for Input Slew Rate
Parameter Value
Rising edge VIL(DC) To VIH(AC)
Falling edge VIH(DC) To VIL(AC)
Temperature range TA
Table 25: Input Slew Rate (VCCQ = 1.7–1.95V)
CLK/DQS Slew Rate Derating VIH(AC)/VIL(AC)= 540mV, VIH(DC)/VIL(DC)= 360mV

Command/
Address 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3
and DQ V/ns set hold set hold set hold set hold set hold set hold set hold set hold Unit
1 0 0 0 0 - - - - - - - - - - - - ps
0.9 0 0 0 0 0 0 - - - - - - - - - - ps
0.8 - - 0 0 0 0 0 0 - - - - - - - - ps
0.7 - - - - 0 0 0 0 0 0 - - - - - - ps
0.6 - - - - - - 0 0 0 0 0 0 - - - - ps
0.5 - - - - - - - - 0 0 0 0 180 180 - - ps
0.4 - - - - - - - - - - 180 180 360 360 660 660 ps
0.3 - - - - - - - - - - - - 660 660 920 920 ps
Table 26: Input Slew Rate (VCCQ= 2.7–3.6V)
CLK/DQS Slew Rate Derating VIH(AC)/VIL(AC)= 990mV, VIH(DC)/VIL(DC)= 660mV

Command/
Address 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3
and DQ V/ns set hold set hold set hold set hold set hold set hold set hold set hold Unit
1 0 0 0 0 - - - - - - - - - - - - ps
0.9 0 0 0 0 0 0 - - - - - - - - - - ps
0.8 - - 0 0 0 0 0 0 - - - - - - - - ps
0.7 - - - - 0 0 0 0 0 0 - - - - - - ps
0.6 - - - - - - 0 0 0 0 0 0 - - - - ps
0.5 - - - - - - - - 0 0 0 0 330 330 - - ps
0.4 - - - - - - - - - - 330 330 660 660 1210 1210 ps
0.3 - - - - - - - - - - - - 1210 1210 1760 1760 ps
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Output Slew Rate
Output Slew Rate

The output slew rate is tested using the following setup with only one die per DQ channel.
Table 27: Test Conditions for Output Slew Rate
Parameter Value
VOL(DC) 0.3 × VCCQ
VOH(DC) 0.7 × VCCQ
VOL(AC) 0.2 × VCCQ
VOH(AC) 0.8 × VCCQ
Rising edge (tRISE) VOL(DC) to VOH(AC)
Falling edge (tFALL) VOH(DC) to VOL(AC)
Output capacitive load (CLOAD) 5pF
Temperature range TA
Table 28: Output Slew Rate (VCCQ = 1.7–1.95V)
Output Drive Strength Min Max Unit

Overdrive 2 1 5.5 V/ns
Overdrive 1 0.85 5 V/ns
Nominal 0.75 4 V/ns
Underdrive 0.6 4 V/ns
Table 29: Output Slew Rate (VCCQ = 2.7–3.6V)
Output Drive Strength Min Max Unit

Overdrive 2 1.5 10.0 V/ns
Overdrive 1 1.5 9.0 V/ns
Nominal 1.2 7.0 V/ns
Underdrive 1.0 5.5 V/ns
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Electrical Specifications
Stresses greater than those listed can cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at these or any other condi-
tions above those indicated in the operational sections of this specification is not
guaranteed. Exposure to absolute maximum rating conditions for extended periods can
affect reliability.
Table 30: Absolute Maximum Ratings by Device
Parameter Symbol Min1 Max1 Unit

Voltage input VIN -0.6 4.6 V
VCC supply voltage VCC -0.6 4.6 V
VCCQ supply voltage VCCQ -0.6 4.6 V
Storage temperature TSTG -65 150 °C
Note: 1. Voltage on any pin relative to VSS.
Table 31: Recommended Operating Conditions
Parameter Symbol Min Typ Max Unit

Operating temperature Commercial TA 0 – 70 °C
Industrial –40 – +85
VCC supply voltage VCC 2.7 3.3 3.6 V
VCCQ supply voltage (1.8V) VCCQ 1.7 1.8 1.95 V
VCCQ supply voltage (3.3V) 2.7 3.3 3.6 V
VSS ground voltage VSS 0 0 0 V
Table 32: Valid Blocks per LUN
Parameter Symbol Min Max Unit Notes

Valid block number NVB 3996 4096 Blocks 1
Note: 1. Invalid blocks are block that contain one or more bad bits beyond ECC. The device may
contain bad blocks upon shipment. Additional bad blocks may develop over time; how-
ever, the total number of available blocks will not drop below NVB during the endur-
ance life of the device. Do not erase or program blocks marked invalid from the factory.
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Table 33: Capacitance: 100-Ball BGA Package

Notes 1 and 2 apply to entire table
Single Die/Dual
Die Package Quad Die Package Octal Die Package
Description Symbol Min Typ Max Min Typ Max Min Typ Max Unit Notes
Input capacitance CCK 3.8 4.8 5.8 5.8 7.3 8.8 9.9 11.9 13.9 pF 3
(CLK)
Input capacitance CIN 2.7 3.7 4.7 4.9 6.4 7.9 8.9 10.9 12.9 pF 3
(ALE, CLE, W/R#)
Input/output capaci- CIO 3.4 4.4 5.4 6.1 7.6 9.1 11.4 13.4 15.4 pF 3
tance
(DQ[7:0], DQS)
Input capacitance COTHER – – 5.8 – – 8.8 – – 13.9 pF
(CE#, WP#)
Delta clock capacitance DCCK – – 1.4 – – 1.7 – – 2 pF
Delta input capaci- DCIN – – 1.4 – – 1.7 – – 2 pF
tance
Delta input/output ca- DCIO – – 1.4 – – 1.7 – – 2 pF
pacitance
Notes: 1. Verified in device characterization; not 100% tested.

2. Test conditions: TA = 25ºC, ƒ = 100 MHz, VIN = 0V.
3. Values for CCK, CIN and CIO (TYP) are estimates.
Table 34: Capacitance: 48-Pin TSOP Package
Description Symbol Device Max Unit Notes

Input capacitance – ALE, CE#, CLE, RE#, CIN Single die package 8 pF 1
WE#, WP# Dual die package 10
Quad die package 14
Input/output capacitance – DQ[7:0], DQS CIO Single die package 6 pF 1
Dual die package 10
Quad die package 18
Note: 1. These parameters are verified in device characterization and are not 100% tested. Test
conditions: TC = 25°C; f = 1 MHz; Vin = 0V.
Table 35: Capacitance: 52-Pad LGA Package

Input capacitance – ALE, CE#, CLE, RE#, CIN Dual die package 8 pF 1
WE#, WP# Quad die package 10
Octal die package 14
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Electrical Specifications – DC Characteristics and Operating
Conditions (Asynchronous)
Table 35: Capacitance: 52-Pad LGA Package (Continued)

Input/output capacitance – DQ[7:0] CIO Dual die package 8 pF 1
Quad die package 10
Octal die package 16
Note: 1. These parameters are verified in device characterization and are not 100% tested. Test
conditions: TC = 25°C; f = 1 MHz; Vin = 0V.
Table 36: Test Conditions
Parameter Value Notes

Rising input transition VIL(DC) to VIH(AC) 1
Falling input transition VIH(DC) to VIL(AC) 1
Input rise and fall slew rates 1 V/ns –
Input and output timing levels VCCQ/2 –
Output load: Nominal output drive strength CL = 5pF 2, 3
Notes: 1. The receiver will effectively switch as a result of the signal crossing the AC input level; it
will remain in that status as long as the signal does not ring back above (below) the DC
input LOW (HIGH) level.
2. Transmission line delay is assumed to be very small.
3. This test setup applies to all package configurations.
Electrical Specifications – DC Characteristics and Operating Conditions

(Asynchronous)
Table 37: DC Characteristics and Operating Conditions (Asynchronous Interface)
Parameter Conditions Symbol Min1 Typ1 Max1 Unit

Array read current (active) – ICC1_A – 25 50 mA
Array program current (active) – ICC2_A – 25 50 mA
Erase current (active) – ICC3_A – 25 50 mA
tRC tRC
I/O burst read current = (MIN); IOUT= 0mA ICC4R_A – 8 10 mA
tWC tWC
I/O burst write current = (MIN) ICC4w_A – 8 10 mA
Bus idle current – ICC5_A – 3 5 mA
Current during first RESET – ICC6 – – 10 mA
command after power-on
Standby current - VCC CE# = VCCQ - 0.2V; ISB – 10 50 µA
WP# = 0V/VCCQ
Standby current - VCCQ CE# = VCCQ - 0.2V; ISBQ – 3 10 µA
WP# = 0V/VCCQ
tRISE
Staggered power-up current = 1ms; CLINE = 0.1uF IST – – 10 mA
Note: 1. All values are per die (LUN) unless otherwise specified.
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Electrical Specifications – DC Characteristics and Operating
Conditions (Synchronous)

(Synchronous)
Table 38: DC Characteristics and Operating Conditions (Synchronous Interface)
Parameter Conditions Symbol Min1 Typ1 Max1 Unit

tCK tCK
Array read current (active) CE# = VIL; = (MIN) ICC1_S – 25 50 mA
tCK tCK
Array program current (active) = (MIN) ICC2_S – 25 50 mA
tCK = tCK (MIN)
Erase current (active) ICC3_S – 25 50 mA
tCK tCK
I/O burst read current = (MIN); IOUT= 0mA ICC4R_S – 20 27 mA
tCK tCK
I/O burst write current = (MIN) ICC4W_S – 20 27 mA
tCK tCK
Bus idle current = (MIN) ICC5_S – 5 10 mA
Standby current - VCC CE# = VCCQ - 0.2V; ISB – 10 50 µA
WP# = 0V/VCCQ
Standby Current - VCCQ CE# = VCCQ - 0.2V; ISBQ – 3 10 µA
WP# = 0V/VCCQ
Note: 1. All values are per die (LUN) unless otherwise specified.

(VCCQ)
Table 39: DC Characteristics and Operating Conditions (3.3V VCCQ)
Parameter Condition Symbol Min Typ Max Unit Notes

AC input high voltage CE#, DQ[7:0], DQS, ALE, CLE, CLK VIH(AC) 0.8 × VCCQ – VCCQ + 0.3 V
AC input low voltage (WE#), W/R# (RE#), WP# VIL(AC) –0.3 – 0.2 × VCCQ V
DC input high voltage DQ[7:0], DQS, ALE, CLE, CLK VIH(DC) 0.7 × VCCQ – VCCQ + 0.3 V
DC input low voltage (WE#), W/R# (RE#) VIL(DC) –0.3 – 0.3 × VCCQ V
Input leakage current Any input VIN = 0V to VCCQ ILI – – ±10 µA
(all other pins under test = 0V)
Output leakage cur- DQ are disabled; VOUT = 0V to VCCQ ILO – – ±10 µA 1
rent
Output low current VOL = 0.4V IOL (R/B#) 8 10 – mA 2
(R/B#)
Notes: 1. All leakage currents are per die (LUN). Two die (LUNs) have a maximum leakage current
of ±20µA and four die (LUNs) have a maximum leakage current of ±40µA in the asynchro-
nous interface.
2. DC characteristics may need to be relaxed if R/B# pull-down strength is not set to full
strength. See Table 14 (page 73) for additional details.
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Electrical Specifications – AC Characteristics and Operating
Table 40: DC Characteristics and Operating Conditions (1.8V VCCQ)
Parameter Condition Symbol Min Typ Max Unit Notes

AC input high voltage CE#, DQ[7:0], DQS, ALE, CLE, CLK VIH(AC) 0.8 × VCCQ – VCCQ + 0.3 V
AC input low voltage (WE#), W/R# (R/E#), WP# VIL(AC) –0.3 – 0.2 × VCCQ V
DC input high voltage DQ[7:0], DQS, ALE, CLE, CLK VIH(DC) 0.7 × VCCQ – VCCQ + 0.3 V
DC input low voltage (WE#), W/R# (R/E#) VIL(DC) -0.3 – 0.3 × VCCQ V
Input leakage current Any input VIN = 0V to VCCQ ILI – – ±10 µA 1
(all other pins under test = 0V)
Output leakage current DQ are disabled; Vout = 0V to ILO – – ±10 µA 1
VCCQ
Output low current (R/B#) VOL = 0.2V IOL (R/B#) 3 4 – mA
Note: 1. All leakage currents are per die (LUN). Two die (LUNs) have a maximum leakage current
of ±20µA and four die (LUNs) have a maximum leakage current of ±40µA in the asynchro-
nous interface.
Electrical Specifications – AC Characteristics and Operating Conditions

(Asynchronous)
Table 41: AC Characteristics: Asynchronous Command, Address, and Data
Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Mode 5

Parameter Symbol Min Max Min Max Min Max Min Max Min Max Min Max Unit Notes
Clock period 100 50 35 30 25 20 ns
Frequency ≈10 ≈20 ≈28 ≈33 ≈40 ≈50 MHz
tADL
ALE to data start 200 – 100 – 100 – 100 – 70 – 70 – ns 1
tALH
ALE hold time 20 – 10 – 10 – 5 – 5 – 5 – ns
tALS
ALE setup time 50 – 25 – 15 – 10 – 10 – 10 – ns
tAR
ALE to RE# delay 25 – 10 – 10 – 10 – 10 – 10 – ns
tCEA
CE# access time – 100 – 45 – 30 – 25 – 25 – 25 ns
tCH
CE# hold time 20 – 10 – 10 – 5 – 5 – 5 – ns
tCHZ
CE# HIGH to output – 100 – 50 – 50 – 50 – 30 – 30 ns 2
High-Z
tCLH
CLE hold time 20 – 10 – 10 – 5 – 5 – 5 – ns
tCLR
CLE to RE# delay 20 – 10 – 10 – 10 – 10 – 10 – ns
tCLS
CLE setup time 50 – 25 – 15 – 10 – 10 – 10 – ns
tCOH
CE# HIGH to output 0 – 15 – 15 – 15 – 15 – 15 – ns
hold
tCS
CE# setup time 70 – 35 – 25 – 25 – 20 – 15 – ns
tDH
Data hold time 20 – 10 – 5 – 5 – 5 – 5 – ns
tDS
Data setup time 40 – 20 – 15 – 10 – 10 – 7 – ns
tIR
Output High-Z to 10 – 0 – 0 – 0 – 0 – 0 – ns
RE# LOW
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Table 41: AC Characteristics: Asynchronous Command, Address, and Data (Continued)

tRC
RE# cycle time 100 – 50 – 35 – 30 – 25 – 20 – ns
tREA
RE# access time – 40 – 30 – 25 – 20 – 20 – 16 ns 3
tREH
RE# HIGH hold time 30 – 15 – 15 – 10 – 10 – 7 – ns 3
tRHOH
RE# HIGH to output 0 – 15 – 15 – 15 – 15 – 15 – ns 3
hold
tRHW
RE# HIGH to WE# 200 – 100 – 100 – 100 – 100 – 100 – ns
LOW
tRHZ
RE# HIGH to output – 200 – 100 – 100 – 100 – 100 – 100 ns 2, 3
High-Z
tRLOH
RE# LOW to output 0 – 0 – 0 – 0 – 5 – 5 – ns 3
hold
tRP
RE# pulse width 50 – 25 – 17 – 15 – 12 – 10 – ns
tRR
Ready to RE# LOW 40 – 20 – 20 – 20 – 20 – 20 – ns
tWB
WE# HIGH to – 200 – 100 – 100 – 100 – 100 – 100 ns 4
R/B# LOW
tWC
WE# cycle time 100 – 45 – 35 – 30 – 25 – 20 – ns
tWH
WE# HIGH hold time 30 – 15 – 15 – 10 – 10 – 7 – ns
tWHR
WE# HIGH to RE# 120 – 80 – 80 – 60 – 60 – 60 – ns
LOW
tWP
WE# pulse width 50 – 25 – 17 – 15 – 12 – 10 – ns
tWW
WP# transition to 100 – 100 – 100 – 100 – 100 – 100 – ns
WE# LOW
Notes: 1. Timing for tADL begins in the address cycle, on the final rising edge of WE# and ends
with the first rising edge of WE# for data input.
2. Data transition is measured ±200mV from steady-steady voltage with load. This parame-
ter is sampled and not 100 percent tested.
3. AC characteristics may need to be relaxed if output drive strength is not set to at least
nominal.
4. Do not issue a new command during tWB, even if R/B# or RDY is ready.
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Electrical Specifications – AC Characteristics and Operating Conditions

(Synchronous)
Table 42: AC Characteristics: Synchronous Command, Address, and Data

Clock period 50 30 20 15 12 10 ns
Frequency ≈20 ≈33 ≈50 ≈67 ≈83 ≈100 MHz
Access window tAC 3 20 3 20 3 20 3 20 3 20 3 20 ns
of DQ[7:0] from
CLK
tADL
ALE to data 100 – 100 – 70 – 70 – 70 – 70 – ns
loading time
tCAD
Command, ad- 25 – 25 – 25 – 25 – 25 – 25 – ns 1
dress data delay
tCALH
ALE, CLE, W/R# 10 – 5 – 4 – 3 – 2.5 – 2 – ns
hold
tCALS
ALE, CLE, W/R# 10 – 5 – 4 – 3 – 2.5 – 2 – ns
setup
tCAH
DQ hold – com- 10 – 5 – 4 – 3 – 2.5 – 2 – ns
mand, address
tCAS
DQ setup – com- 10 – 5 – 4 – 3 – 2.5 – 2 – ns
mand, address
tCH
CE# hold 10 – 5 – 4 – 3 – 2.5 – 2 – ns
Average CLK cy- tCK (avg) 50 100 30 50 20 30 15 20 12 15 10 12 ns 3
cle time
Absolute CLK tCK (abs) tCK (abs) MIN = tCK (avg) + tJIT (per) MIN ns
cycle time, from tCK (abs) MAX = tCK (avg) + tJIT (per) MAX
rising edge to
rising edge
CLK cycle HIGH tCKH 0.43 0.57 0.43 0.57 0.43 0.57 0.43 0.57 0.43 0.57 0.43 0.57 tCK 4
(abs)
CLK cycle LOW tCKL 0.43 0.57 0.43 0.57 0.43 0.57 0.43 0.57 0.43 0.57 0.43 0.57 tCK 4
(abs)
Data output tCKWR tCKWR(MIN) = RoundUp[(tDQSCK(MAX) + tCK)/tCK] tCK
end to W/R#
HIGH
tCS
CE# setup 35 – 25 – 15 – 15 – 15 – 15 – ns
tDH
Data In hold 5 – 2.5 – 1.7 – 1.3 – 1.1 – 0.8 – ns
tDQSCK
Access window – 20 – 20 – 20 – 20 – 20 – 20 ns
of DQS from
CLK
tDQSD
DQS, DQ[7:0] – 18 – 18 – 18 – 18 – 18 – 18 ns
Driven by NAND
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Table 42: AC Characteristics: Synchronous Command, Address, and Data (Continued)

tDQSHZ
DQS, DQ[7:0] to – 20 – 20 – 20 – 20 – 20 – 20 ns 5
tri-state
DQS input high tDQSH 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tCK
pulse width
DQS input low tDQSL 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tCK
pulse width
tDQSQ
DQS-DQ skew – 5 – 2.5 – 1.7 – 1.3 – 1.0 – 0.85 ns
Data input tDQSS 0.75 1.25 0.75 1.25 0.75 1.25 0.75 1.25 0.75 1.25 0.75 1.25 tCK
tDS
Data In setup 5 – 3 – 2 – 1.5 – 1.1 – 0.8 – ns
tDSH tCK
DQS falling 0.2 – 0.2 – 0.2 – 0.2 – 0.2 – 0.2 –
edge from CLK
rising – hold
tDSS tCK
DQS falling to 0.2 – 0.2 – 0.2 – 0.2 – 0.2 – 0.2 –
CLK rising – set-
up
Data valid win- tDVW tDVW = tQH - tDQSQ ns
dow
Half clock peri- tHP tHP = Min(tCKH, tCKL) ns
od
The deviation tJIT (per) –0.7 0.7 –0.7 0.7 –0.7 0.7 –0.6 0.6 –0.6 0.6 –0.5 0.5 ns
of a given tCK
(abs) from a tCK
(avg)
DQ-DQS hold, tQH tQH = tHP - tQHS ns
DQS to first DQ
to go nonvalid,
per access
tQHS
Data hold skew – 6 – 3 – 2 – 1.5 – 1.2 – 1 ns
factor
tRHW
Data output to 100 – 100 – 100 – 100 – 100 – 100 ns
command, ad-
dress, or data in-
put
tRR
Ready to data 20 – 20 – 20 – 20 – 20 – 20 – ns
output
tWB
CLK HIGH to R/ – 100 – 100 – 100 – 100 – 100 – 100 ns
B# LOW
tWHR
Command cycle 80 – 80 – 80 – 80 – 80 – 80 – ns
to data output
tWPRE tCK
DQS write pre- 1.5 – 1.5 – 1.5 – 1.5 – 1.5 – 1.5 –
amble
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Table 42: AC Characteristics: Synchronous Command, Address, and Data (Continued)

tWPST tCK
DQS write post- 1.5 – 1.5 – 1.5 – 1.5 – 1.5 – 1.5 –
amble
tWRCK
W/R# LOW to 20 – 20 – 20 – 20 – 20 – 20 – ns
data output cy-
cle
tWW
WP# transition 100 – 100 – 100 – 100 – 100 – 100 – ns
to command cy-
cle
Notes: 1. Delay is from start of command to next command, address, or data cycle; start of ad-
dress to next command, address, or data cycle; and end of data to start of next com-
mand, address, or data cycle.
2. This value is specified in the parameter page.
3. tCK(avg) is the average clock period over any consecutive 200-cycle window.
4. tCKH(abs) and tCKL(abs) include static offset and duty cycle jitter.
5. tDQSHZ begins when W/R# is latched HIGH by CLK. This parameter is not referenced to a
specific voltage level; it specifies when the device outputs are no longer driving.
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Electrical Specifications – Array Characteristics
Electrical Specifications – Array Characteristics
Table 43: Array Characteristics
Parameter Symbol Typ Max Unit Notes

Number of partial page programs NOP – 1 Cycles 1
ERASE BLOCK operation time tBERS 3.8 10 ms
Cache busy tCBSY 35 2600 µs
tCCS
Change column setup time to data in/out or next command – 200 ns
Dummy busy time tDBSY 0.5 1 µs
Cache read busy time tRCBSY 3 75 µs
tFEAT
Busy time for SET FEATURES and GET FEATURES operations – 1 µs
tITC
Busy time for interface change – 1 µs 2
tLPROG
LAST PAGE PROGRAM operation time – – µs 3
tOBSY
Busy time for OTP DATA PROGRAM operation if OTP is protected – 40 µs
tPOR
Power-on reset time – 1 ms
PROGRAM PAGE operation time tPROG 1300 2600 µs
tR
READ PAGE operation time – 75 µs
tRST
Device reset time (Read/Program/Erase) – 5/10/500 µs 4
Notes: 1. The pages in the OTP Block have an NOP of 4.

2. tITC (MAX) is the busy time when the interface changes from asynchronous to synchro-
nous using the SET FEATURES (EFh) command or synchronous to asynchronous using the
RESET (FFh) command. During the tITC time, any command, including READ STATUS
(70h) and READ STATUS ENHANCED (78h), is prohibited.
3. tLPROG = tPROG (last page) + tPROG (last page - 1) - command load time (last page) -
address load time (last page) - data load time (last page).
4. If RESET command is issued when the target is READY, the target goes busy for a maxi-
mum of 5µs.
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Asynchronous Interface Timing Diagrams
Figure 74: RESET Operation
CLE
CE#
tWB
WE#
tRST
R/B#
DQ[7:0] FFh
RESET
command
Figure 75: RESET LUN Operation
tCS
CE#
tCLS tCLH
CLE
tWC
tWP tWP tWH tCH
WE#
tALH tALS tALH
ALE
tDS tDH tWB
DQ[7:0] FAh Row add 1 Row add 2 Row add 3
tRST
R/B#
Don’t Care
PDF: 09005aef83d2277a

Figure 76: READ STATUS Cycle
tCLR
CLE tCLS tCLH
tCS
CE#
tWP tCH
WE#
tCEA tCHZ
tWHR tRP tCOH
RE#
tRHZ
tRHOH
tDS tDH tIR tREA
DQ[7:0] Status
70h output
Don’t Care
Figure 77: READ STATUS ENHANCED Cycle
tCS
CE#
tCLS tCLH
CLE
tWC
tWP tWP tWH tCH
WE#
tCHZ
tCEA
tALH tALS tALH tAR tCOH
ALE
RE#
tRHZ
tDS tDH tWHR tRHOH

tREA
DQ[7:0] 78h Row add 1 Row add 2 Row add 3 Status output
Don’t Care
PDF: 09005aef83d2277a

Figure 78: READ PARAMETER PAGE
CLE
WE#
tWB
ALE
tRC
RE#
tRR
tRP
DQ[7:0] ECh 00h P00 P10 P2550 P01
tR
R/B#
Figure 79: READ PAGE
CLE
tCLR
CE#
tWC
WE#
tWB
tAR
ALE
tR tRC tRHZ
RE#
tRR tRP
Col Col Row Row Row DOUT DOUT DOUT

DQx 00h 30h
add 1 add 2 add 1 add 2 add 3 N N+1 M
RDY Busy
Don’t Care
PDF: 09005aef83d2277a

Figure 80: READ PAGE Operation with CE# “Don’t Care”
CLE
CE#
RE#
ALE
tR
RDY
WE#
DQx 00h Address (5 cycles) 30h Data output
tCEA
CE#
tREA tCHZ
RE# tCOH
Don’t Care
I/Ox Out
PDF: 09005aef83d2277a

Figure 81: CHANGE READ COLUMN
CLE
tCLR
CE#
WE#
tRHW
tCCS
ALE
tRC tREA
RE#
DQx DOUT DOUT

05h Col Col E0h DOUT DOUT
N–1 N add 1 add 2 M M+1
Column address M
RDY
PDF: 09005aef83d2277a

Figure 82: READ PAGE CACHE SEQUENTIAL
CLE
tCLS tCLS tCLH
tCLH
tCH tCS
tCS tCH
CE#
tWC
WE#
tCEA tRHW
ALE
tRC
RE# tWB
tDH tREA
tDS
tDS tWB tR tRR tDH
DQx 00h Col Col Row Row Row 30h 31h DOUT DOUT DOUT 31h
add 1 add 2 add 1 add 2 add 3 0 1
Column address Page address tRCBSY Page address

00h M M
RDY
Column address 0
CLE
tCLS tCLH
tCS
tCH
CE#
WE#
tRHW tRHW
tCEA
ALE
tRC tRC
RE# tWB
tREA tDS tRR
tDH tREA
DOUT DOUT DOUT DOUT DOUT DOUT
DQx 0 1
DOUT 31h 0 1
DOUT 3Fh 0 1
DOUT
Page address tRCBSY Page address tRCBSY Page address

M M+1 M+2
RDY
Column address 0 Column address 0 Column address 0
1 Don’t Care
PDF: 09005aef83d2277a

Figure 83: READ PAGE CACHE RANDOM
CLE
tCLS
tCLH
tCH
tCS
CE#
tWC
WE#
ALE
RE#
tDH
tWB tR
tDS
Col Col Row Row Row Col Col Row Row
DQx 00h add 1 add 2 add 1 add 2 add 3
30h 00h add 1 add 2 add 1 add 2
Column address Page address Column address Page address

00h M 00h N
RDY
CLE tCLS
tCLH
tCS
tCH
CE#
WE# tCEA tRHW
ALE
tRC
tWB
RE# tDS tRR
tDH tREA
Col Col Row Row Row DOUT DOUT DOUT DOUT DOUT DOUT
add 1 add 1 add 2 add 3
31h 3Fh
add 2 0 1 0 1
DQx
Column address Page address tRCBSY Page address tRCBSY Page address
00h N M N
RDY Column address 0 Column address 0
1 Don’t Care
PDF: 09005aef83d2277a

Figure 84: READ ID Operation
CLE
CE#
WE#
tAR
ALE
RE#
tWHR tREA
DQx 90h 00h or 20h Byte 0 Byte 1 Byte 2 Byte 3 Byte 4

Address, 1 cycle
Figure 85: PROGRAM PAGE Operation
CLE
CE#
tWC tADL
WE#
tWB tPROG tWHR
ALE
RE#
DQx 80h Col Col Row Row Row DIN DIN 10h 70h
add 1 add 2 add 1 add 2 add 3 Status
N M
1 up to m byte
serial Input
RDY
Don’t Care
PDF: 09005aef83d2277a

Figure 86: PROGRAM PAGE Operation with CE# “Don’t Care”
CLE
CE#
WE#
ALE
DQx 80h Address (5 cycles) Data input Data input 10h
tCS tCH
CE#
tWP
WE#
Don’t Care
Figure 87: PROGRAM PAGE Operation with CHANGE WRITE COLUMN
CLE
CE#
tWC tADL tCCS

WE#
tWB tPROG tWHR
ALE
RE#
Col Col Row Row Row DIN DIN Col Col DIN DIN
DQx 80h add 1 add 2 add 1 add 2 add 3 M N
85h add 1 add 2 P Q
10h 70h Status
CHANGE WRITE Column address READ STATUS

Serial input COLUMN command Serial input command
RDY
Don’t Care
PDF: 09005aef83d2277a

Figure 88: PROGRAM PAGE CACHE
CLE
CE#
tWC tADL
WE#
tWBtCBSY tWB tLPROG tWHR
ALE
RE#
Col Col Row Row Row DIN DIN Col Col Row Row Row DIN DIN
DQx 80h add 1 add 2 add 1 add 2 add 3 N M
15h 80h add 1 add 2 add 1 add 2 add 3 N M
10h 70h Status
Serial input
RDY
Last page - 1 Last page
Don’t Care
Figure 89: PROGRAM PAGE CACHE Ending on 15h
CLE
CE#
tWC tADL tADL

WE#
tWHR tWHR
ALE
RE#
Col Col Row Row Row DIN DIN Col Col Row Row Row DIN DIN
DQx 80h
15h 70h Status 80h
add 1 add 2 add 1 add 2 add 3 M
15h 70h Status 70h Status
N M N
Serial input
Last page – 1 Last page

Poll status until: To verify successful completion of the last 2 pages:
I/O6 = 1, Ready I/O5 = 1, Ready
I/O0 = 0, Last page PROGRAM successful
Don’t Care I/O1 = 0, Last page – 1 PROGRAM successful
PDF: 09005aef83d2277a

Figure 90: COPYBACK
CLE
CE#
tWC tADL
WE#
tWB tWB tPROG tWHR
ALE
RE#
tR
DQx 00h Col Col Row Row Row 35h 85h Col Col Row Row Row Data Data 10h 70h Status
add 1 add 2 add 1 add 2 add 3 (or 30h) add 1 add 2 add 1 add 2 add 3 1 N
READ STATUS
Busy Busy command
RDY
Data Input Don’t Care

Optional
Figure 91: ERASE BLOCK Operation
CLE
CE#
tWC
WE#
tWB tWHR
ALE
RE#
tBERS
Row Row Row
DQ[7:0] 60h add 1 add 2 add 3 D0h 70h Status
Row address READ STATUS

command
Busy
RDY
I/O0 = 0, Pass
I/O0 = 1, Fail
Don’t Care
PDF: 09005aef83d2277a

Synchronous Interface Timing Diagrams
Figure 92: SET FEATURES Operation
tCS
CE#
CLE
tCALS tCALS
ALE
tCAD tCAD tCAD tWB tFEAT
CLK
tDQSS
W/R#
DQS
DQx EFh Feat P10 P11 P20 P21 P30 P31 P40 P41
Addr
R/B#
Don’t Care
Notes: 1. When CE# remains LOW, tCAD begins at the rising edge of the clock from which the last
data byte is input for the subsequent command or data input cycle(s).
2. tDSH (MIN) generally occurs during tDQSS (MIN).
3. tDSS (MIN) generally occurs during tDQSS (MAX).
4. The cycle that tCAD is measured from may be an idle cycle (as shown), another com-
mand cycle, an address cycle, or a data cycle. The idle cycle is shown in this diagram for
simplicity.
PDF: 09005aef83d2277a

Figure 93: READ ID Operation
tCS
CE#
tCALS tCALS
CLE
ALE
tCALH
tCAD tCAD tWHR
CLK
tCKWR tRHW
tCALS tCALH
W/R#
tDQSD tDQSCK tCALS tDQSHZ
DQS
DQ[7:0] 90h 00h Byte 0 Byte 0 Byte 1 Byte 1 Byte 2 Byte 2 Byte 3 Byte 3 Byte 4 Byte 4
or 20h
Don’t Care Driven
PDF: 09005aef83d2277a

Figure 94: GET FEATURES Operation
tCS
CE#
tCALS tCALS
CLE
ALE
tCALH
tCAD tCAD
CLK
tWRCK tCKWR tRHW

tCALS
tCALH
W/R#
tDQSCK tDQSHZ
tDQSD tCALS
DQS
DQ[7:0] EEh Feat

Addr P1 P2 P3 P4
tWB tFEAT
RDY
Don’t Care Driven
PDF: 09005aef83d2277a

Figure 95: RESET (FCh) Operation
tCS tCH
CE#
tCALS tCALH
CLE tCALS tCALH
tCAD tCALH
ALE
CLK
W/R#
tWB
DQS
tCAS tCAH
DQ[7:0] FCh
SYNCHRONOUS
RESET command tRST
R/B#
Don’t Care
PDF: 09005aef83d2277a

Figure 96: READ STATUS Cycle
CE#
CLE
ALE
tWHR tCKWR tRHW
CLK
W/R#
tDQSD tDQSHZ
DQS
DQ[7:0] 70h Status Status
READ STATUS
command
RDY
Don’t Care Driven
PDF: 09005aef83d2277a

Figure 97: READ STATUS ENHANCED Operation
tCS
CE#
CLE
ALE
tCAD tCAD tCAD tCAD tWHR tCKWR tRHW
CLK
W/R#
tDQSD tDQSHZ
DQS
DQ[7:0] 78h Row Row Row Status Status

add 1 add 2 add 3
Don’t Care Driven
PDF: 09005aef83d2277a

Figure 98: READ PARAMETER PAGE Operation
tCS
CE#
tCALS tCALS
CLE
ALE
tCAD tCAD tCALH
CLK
tCKWR tRHW
tWRCK
tCALH
W/R#
DQS
DQ[7:0] ECh 00h P0 P1 P2 Pn-3 Pn-2 Pn-1 Pn
tWB tR
RDY
Driven Don’t Care
PDF: 09005aef83d2277a

Figure 99: READ PAGE Operation
tCS
CE#
CLE
ALE
tCAD tCAD tCAD tCAD tCAD tCAD tCAD
CLK
tCALS
W/R#
DQS
DQx 00h Col Col Row Row Row 30h

tWB tR
RDY
CE#
tCALS tCALS
CLE
ALE
tCALH
tCAD tCAD
CLK
tCKWR tRHW
tWRCK
tCALS
tCALH
W/R#
DQS
DQx Row 30h Dout Dout Dout Dout Dout

add 3 0 N-3 N-2 N-1 N
1 up to m Byte
tWB tR serial input
RDY
1
Don’t Care Driven
PDF: 09005aef83d2277a

Figure 100: CHANGE READ COLUMN
CE#
tCALS tCALS
CLE
ALE
tRHW tCAD tCAD tCAD tCCS tRHW
CLK
tDQSD tDQSHZ
W/R#
tDQSCK
DQS
DQx 05h Col Col Dout Dout Dout Dout Dout

add 1 add 2 E0h C C+1 D-2 D-1 D
RDY
Don’t Care Driven
PDF: 09005aef83d2277a

Figure 101: READ PAGE CACHE SEQUENTIAL (1 of 2)
CE#
CLE
ALE
tRHW
CLK
tDQSHZ
W/R#
tDQSD tDQSCK tDQSD
DQS
Initial
Read Data
DQx 30h 31h Data Output 31h
tWB tR tWB tRCBSY tWB tRCBSY
RDY
1
Initial Read Sequential Sequential
Access Read Access A Read Access B
Driven Don’t Care
PDF: 09005aef83d2277a

Figure 102: READ PAGE CACHE SEQUENTIAL (2 of 2)
CE#
CLE
ALE
tRHW tRHW
CLK
tDQSHZ tDQSHZ
W/R#
tDQSD tDQSCK tDQSD tDQSCK
DQS
Sequential Sequential
Read Data A Read Data B
DQx Data Output 3Fh Data Output
tRCBSY
tWB tRCBSY
RDY
Driven Don’t Care
PDF: 09005aef83d2277a

Figure 103: READ PAGE CACHE RANDOM (1 of 2)
CE#
CLE
ALE
tRHW tCAD tCAD x 4 tRHW tCAD tCAD x 4
CLK
tDQSHZ
W/R#
tDQSD tDQSCK
DQS
Initial
Read Data
30h 5 Address 31h 5 Address 31h
DQx 00h Data Output 00h
Cycles Cycles
tRCBSY
tWB tR tWB tRCBSY tWB
RDY
Initial Read Random Random

Access Read Access A Read Access B
Don’t Care Driven
Figure 104: READ PAGE CACHE RANDOM (2 of 2)
CE#
CLE
ALE
tCAD x 4 tRHW tRHW
CLK
tDQSHZ tDQSHZ
W/R#
DQS
Random Random
Read Data A Read Data B
DQx 31h Data Output 3Fh Data Output
tWB tRCBSY tWB tRCBSY
RDY
Random
Read Access B
1
Don’t Care Driven
PDF: 09005aef83d2277a

Figure 105: Multi-Plane Read Page (1 of 2)
CE#
CLE
tCALS tCALS
ALE
tCAD tCAD x 5 tCAD tCAD x 5 tRHW tCAD tCAD x 5
CLK
tDQSHZ
W/R#
tDQSD tDQSCK
DQS
If data from a plane other than A is desired, a 06h-E0h command sequence

tWB is required after tR and prior to taking W/R# LOW.
Address A Address B Data A 06h Address B E0h

DQx 00h 5 Cycles
32h 00h 5 Cycles 30h Output 5 Cycles
tWB tR
RDY
tDBSY
1 Don’t Care Driven 2
PDF: 09005aef83d2277a

Figure 106: Multi-Plane Read Page (2 of 2)
CE#
CLE
ALE
tRHW tCAD tCAD x 5
CLK
tDQSHZ
W/R#
tCCS
DQS
Data B Address A E0h

DQx E0h Output
06h 5 Cycles
RDY
2 3
CE#
CLE
ALE
tRHW tCAD tCAD x 5 tRHW
CLK
tDQSHZ tDQSHZ
W/R#
tCCS
tDQSCK tDQSD tDQSCK
DQS
Data A Address B Data B

DQx 06h 5 Cycles E0h
Output Output
RDY
3 Undefined (driven by NAND) Don’t Care
PDF: 09005aef83d2277a

Figure 107: PROGRAM PAGE Operation (1 of 2)
tCS
CE#
CLE
tCALS tCALS
ALE
tCAD tCAD tCAD tCAD tCAD tCAD tADL tDQSS
CLK
W/R#
DQS
DQx 80h Col Col Row Row Row Din Din Din Din Din
add 1 add 2 add 1 add 2 add 3 N N+1 M-2 M-1 M
RDY
Don’t Care Driven
Figure 108: PROGRAM PAGE Operation (2 of 2)
CE#
CLE
tCALS
ALE
tDQSS tCAD tWB tPROG tWHR tCKWR tRHW
CLK
tCAD
W/R#
tDQSHZ
tDQSD
DQS
DQx Din Din Din Din Din 10h 70h Status Status
N N+1 M-2 M-1 M
READ STATUS
command
RDY
Don’t Care Driven
PDF: 09005aef83d2277a

Figure 109: CHANGE WRITE COLUMN
CE#
CLE
tCALS tCALS
ALE
tCAD tCAD tCAD tCCS tDQSS
CLK
W/R#
DQS
DQx Din Din Din Din 85h Col Col Din Din
N+1 M-2 M-1 M add 1 add 2 C C+1
RDY
CE#
CLE
tCALS tCALS
ALE
tCAD tCAD tCAD tCCS tDQSS tCAD
CLK
W/R#
DQS
DQx 85h Col Col Din Din Din Din Din

add 1 add 2 C C+1 D-2 D-1 D
RDY
1
Don’t Care Driven
PDF: 09005aef83d2277a

Figure 110: Multi-Plane Program Page
CE#
CLE
tCALS tCALS
ALE
tCAD tCAD x 4 + tADL tDQSS tCAD tWB tDBSY tCAD
CLK
W/R#
DQS
80h Address A Data A 11h 80h Address B

DQx 5 Cycles 5 Cycles
RDY
CE#
CLE
ALE
tCAD tCAD x 4 + tADL tDQSS
tCAD tWB tPROG tWHR tRHW
CLK
tCAD tDQSHZ
W/R#
tDQSD
DQS
DQx Address B Data B 10h 70h Status Status

5 Cycles
RDY
PDF: 09005aef83d2277a

Figure 111: ERASE BLOCK
tCS
CE#
CLE
ALE
tCAD tCAD tCAD tCAD tCAD tWHR tRHW
CLK
tCAD
W/R#
tDQSD tDQSHZ
DQS
DQ[7:0] 60h Row Row Row D0h 70h Status Status

add 1 add 2 add 3
READ STATUS
tWB tBERS command
RDY
Don’t Care Driven
Figure 112: COPYBACK (1 of 3)
CE#
CLE
ALE
tCAD tCAD x 5 tRHW tCAD tCADx2
CLK
tDQSHZ
W/R#
tDQSD tDQSCK
DQS
5 Address 35h Data 05h 2 Address

DQx 00h Cycles or 30h E0h
Output Cycles
tWB tR
RDY
Don’t Care Driven 1
PDF: 09005aef83d2277a

CE#
CLE
tCALS tCALS
ALE
tRHW tCAD tCAD x 5 tCAD tCAD + tADL tDQSS
CLK
tDQSHZ
W/R#
tDQSD tDQSCK
DQS
Data 5 Address 85h 2 Address

DQx h 85h Cycles Cycles Data
Output
RDY
1 Don’t Care Driven 2
CE#
CLE
ALE
CLK
tCAD tDQSHZ
W/R#
tDQSD
DQS
DQx 10h 70h Status Status
RDY
2 Don’t Care Driven
PDF: 09005aef83d2277a

Figure 115: READ OTP PAGE
tCS
CE#
tCALS tCALS
CLE
ALE
tCALH
tCAD tCAD tCAD tCAD tCAD tCAD tCAD
CLK
tCALS tWRCK tCKWR tRHW
tCALH
W/R#
DQS
DQx 00h Col Col OTP 00h 00h 30h Dout Dout Dout Dout Dout
add 1 add 2 page1 0 N-3 N-2 N-1 N
tWB tR
R/B#
Don’t Care Driven
PDF: 09005aef83d2277a

Figure 116: PROGRAM OTP PAGE (1 of 2)
tCS
CE#
CLE
tCALS tCALS
ALE
CLK
W/R#
DQS
DQx 80h Col Col OTP 00h 00h Din Din Din Din Din
add 1 add 2 page1 N N+1 M-2 M-1 M
RDY
Don’t Care Driven 1
Figure 117: PROGRAM OTP PAGE (2 of 2)
CE#
CLE
tCALS
ALE
tCAD tWB tPROG tWHR tCKWR tRHW
CLK
tCAD
W/R#
tDQSHZ
tDQSD
DQS
DQx Din Din Din 10h 70h Status Status

M-2 M-1 M
READ STATUS
command
RDY
OTP data written

(following "pass"
status confirmation)
1 Don’t Care Driven Transitioning
PDF: 09005aef83d2277a

Figure 118: PROTECT OTP AREA
CE#
CLE
tCALS
ALE
CLK
W/R#
DQS
DQ[7:0] 80h Col Col 01h 00h 00h 00h

00h 00h
RDY
CE#
CLE
tCALS
ALE
CLK
tCAD tDQSHZ
W/R#
tDQSD
DQS
DQ[7:0] 10h 70h Status Status
READ STATUS
command
RDY
1 Don’t Care Driven Transitioning
PDF: 09005aef83d2277a

Revision History
Revision History
Rev. E Production – 3/11
• Updated Output Drive Strength Impedance Values (VCCQ = 2.7-3.6V) table
• Changed tPROG MAX from 2500µs to 2600µs
Rev. D Production – 12/10

• Noted Synchronous TSOP support to Synchronous timing mode 4
• Updated Read Parameter Page values
• Updated values for Output Drive Impedance for VCCQ 3.3V
• Updated capacitance values for BGA/LGA/TSOP devices
• Changed Icc4r and Icc4w values for both Asynchronous and Synchronous operations
• Updated tWHR for Synchronous mode of operation to 80ns for all timing modes
• Changed tBERS TYP from 3ms to 3.8ms
Rev. C – 7/10
• Added Synchronous TSOP device support
• Changed endurance from 5000 Program/Erase cycles to 3000 Program/Erase cycles
• Changed Data Retention statement from '10 years' to 'JESD47G compliant; see quali-
fication report'
• Added Shared Pages section
• Added Output Slew Rate information to support Synchronous TSOP device
• Changed tAC Min from 10ns to 3ns
• Changed tDQSD Max from 20ns to 18ns
• Changed tCBSY Typ from 3µs to 35µs
• Changed tPROG Max from 2200µs to 2500µs
• Changed tR and tRCBSY Max from 50µs to 75µs
• Change tOBSY Max from 30µs to 40µs
Rev. B – 2/10
• Corrected Part Numbering figure for Design Revision from "B" to "A"
• Corrected MT29F256G08CMAA part number in Read ID Parameter table
• Changed NOP limit for OTP operations from 8 to 4
• Corrected the first spare area location byte number in Error Management
• Added Input Slew Rate information
• Changed CCK capacitance for SDP/DDP BGA devices
Rev. A – 11/09
• Initial release
PDF: 09005aef83d2277a

Revision History
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

www.micron.com/productsupport Customer Comment Line: 800-932-4992
Micron and the Micron logo are trademarks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.
Although considered final, these specifications are subject to change, as further product development and data characterization some-
times occur.
PDF: 09005aef83d2277a

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64Gb, 128Gb, 256Gb, 512Gb Asynchronous/Synchronous NAND

NAND Flash Memory

Features • RESET (FFh) required as first command after power-

64Gb, 128Gb, 256Gb, 512Gb Asynchronous/Synchronous NAND

Part Numbering Information

Figure 1: Part Numbering

Micron Technology Design Revision

Device Width Operating Temperature Range

Classification Package Code

Generation Feature Set

Note: 1. Pb-free package.

64Gb, 128Gb, 256Gb, 512Gb Asynchronous/Synchronous NAND

64Gb, 128Gb, 256Gb, 512Gb Asynchronous/Synchronous NAND

Read Operations ............................................................................................................................................. 81

64Gb, 128Gb, 256Gb, 512Gb Asynchronous/Synchronous NAND

64Gb, 128Gb, 256Gb, 512Gb Asynchronous/Synchronous NAND

64Gb, 128Gb, 256Gb, 512Gb Asynchronous/Synchronous NAND

Figure 51: CHANGE ROW ADDRESS (85h) Operation ..................................................................................... 80

64Gb, 128Gb, 256Gb, 512Gb Asynchronous/Synchronous NAND

Figure 103: READ PAGE CACHE RANDOM (1 of 2) ......................................................................................... 150

64Gb, 128Gb, 256Gb, 512Gb Asynchronous/Synchronous NAND

Asynchronous and Synchronous Signal Descriptions

Table 1: Asynchronous and Synchronous Signal Definitions

64Gb, 128Gb, 256Gb, 512Gb Asynchronous/Synchronous NAND

Table 1: Asynchronous and Synchronous Signal Definitions (Continued)

64Gb, 128Gb, 256Gb, 512Gb Asynchronous/Synchronous NAND

64Gb, 128Gb, 256Gb, 512Gb Asynchronous/Synchronous NAND

Figure 3: 52-Pad LGA (Top View)

G DQ0-21 DQ0-1 WP#-21 DQ7-21

J DQ1-21 DQ2-1 DQ6-1 DQ6-21

L DQ2-21 VSS DQ4-1 DQ5-21

N DNU/ DQ3-21 DQ4-21 DNU/

Top View, Pads Down

64Gb, 128Gb, 256Gb, 512Gb Asynchronous/Synchronous NAND

Figure 4: 100-Ball BGA (Ball-Down, Top View)

D RFU DNU NC WP#-23 NC NC DNU RFU D

E RFU DNU NC WP#-1 NC NC DNU RFU E

F VCC VCC VCC VCC VCC VCC VCC VCC F

G VSS VSS VSS VSS VSS VSS VSS VSS G

H Vssq Vccq RFU RFU R/B2#3 R/B4#4 Vccq Vssq H

J DQ0-23 DQ2-23 ALE-23 CE4#4 R/B# R/B3#4 DQ5-23 DQ7-23 J

K DQ0-1 DQ2-1 ALE-1 CE3#4 CE2#3 CE# DQ5-1 DQ7-1 K

L Vccq Vssq Vccq CLE-23 RE#-23 Vccq Vssq Vccq L

M DQ1-23 DQ3-23 Vssq CLE-1 RE#-1 Vssq DQ4-23 DQ6-23 M

N DQ1-1 DQ3-1 RFU N/A1 RFU WE#-23 DQ4-1 DQ6-1 N

P Vssq RFU N/A1 RFU WE#-1 Vccq Vssq

64Gb, 128Gb, 256Gb, 512Gb Asynchronous/Synchronous NAND

Figure 5: 48-Pin TSOP – Type 1 CPL (Package Code: WP)

0.25 Mold compound:

Note: 1. All dimensions are in millimeters.

64Gb, 128Gb, 256Gb, 512Gb Asynchronous/Synchronous NAND

Figure 6: 52-Pad VLGA

40X Ø0.71 6 CTR Substrate material: plastic laminate.

2 TYP 1.0 MAX

Note: 1. All dimensions are in millimeters.

64Gb, 128Gb, 256Gb, 512Gb Asynchronous/Synchronous NAND

Figure 7: 100-Ball VBGA – 12mm x 18mm (Package Code: H1)

1 TYP 1.0 MAX