864 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 30, NO.

8, AUGUST 1995

A Comprehensive Delay Model for CMOS Inverters

Santanu Dutta, Shivaling S . Mahant Shetti, and Stephen L. Lusky, Member, ZEEE

Abstract-A method to accurately calculate the delay and the Hedenstiema [7] extended the theory to handle ramp inputs
output transition-time of a CMOS inverter for any input ramp to a gate. Even though they offer faster delay evaluation
and output loading is considered. This paper is an extension of techniques, all these works are based on Shockley’s square-
Sakurai’s [l] work on delay modeling of inverters for fast input
ramps. We observed that two different mechanisms, that can be law MOS model (for the transistor operating in its saturation
adequately modeled analytically, govern the delay and the output region) that ignores the carrier velocity saturation effect. AS
transition-time of an inverter in two extreme cases: infinitely fast a result, the results tend to become inaccurate for sub-micron
and infinitely slow inputs. These extreme points are joined by a devices.
curve that can predict the delay and the output transition-time
for any input. We found that the delay and the output transition- Sakurai [ l ] recently introduced his a-power law MOSFET
time for an inverter with small fanouts are similar to those for model that takes care of the velocity saturation effect, which
large input transition-times. This behavior is explained by the use becomes prominent in the short-channel devices. He has given
of I-V trajectories. We describe a method to generate parameters an excellent intuitive understanding of the inverter operation
to model delay and output transition-time for different fanouts and has also derived closed-form equations for evaluating the
and input transition-times; this method can be generalized to add
parameters for different temperatures and supply voltages. Given propagation delay and the output rise (or fall) time. These
a new process technology and its corresponding SPICE-model pa- equations are valid only if the input slope exceeds one-third of
rameters, our delay calculation scheme comprises characterizing the output slope, i.e., when the inverters are reasonably loaded
a minimal number of coefficients for each new technology (a one- and when the input waveforms are fast-rising ramps. For
time process) and evaluating the analytical forms thereafter to relatively slow inputs and/or for very low fanouts, Sakurai’s
obtain the delay and the transition-time. Our delay equations also
explain negative delays that arise in case of slow input rise-times. assumption ceases to be valid, thereby leading to inaccuracies.
A program incorporating the above idea has been implemented in Auvergne [ 101 investigated the delays for lightly loaded
C. Delay and transition-time values obtained from the program structures controlled by slowly varying input signals. His
have been found to be typically within 3% of SPICE. method addresses gate delays for slow input rise-times but
omits the effects of low fanout and slow input rise-times on
I. INTRODUCTION the output slope. Output slope is an important factor in the
delay analysis of a series chain of gates because the output
D ELAY analysis plays a very important role in the de-
sign and synthesis of VLSI systems. Integrated circuit
designers have constantly sought accurate and efficient delay
slope of a gate is the input slope to the next gate.
We have observed that the delay and the output transition-
evaluation techniques that will help them to explore a wide time for an inverter with small fanouts are similar to those
variety of options and better utilize the design space. for large input transition-times. We explain this behavior
Much of past research has addressed the issue of accurate by the use of I-V trajectories and present a comprehensive
and efficient delay modeling of CMOS inverters. People inverter-model explainable over the entire range of input
have tried macromodeling approaches [2], [ 3 ] that facilitate transition-times and output loads. At one extreme is the very
a table-lookup scheme, where the tables are generated via fast input ramp that is explained well by Sakurai’s a-power
pre-characterization of gates using SPICE [4]. These methods law model. At the other extreme is the slow input rise-
are not only time and space consuming, but incorporate time spectrum, where the transient response of an inverter
interpolation errors as well. A different approach [5] models follows its dc voltage-transfer-characteristic. Thus, our work
each gate as a combination of linear resistors and capacitors may be considered as an extension of Sakurai’s initial results
and performs an interconnect delay analysis assuming the El]. Our modeling scheme identifies the turnpoints for the
driver circuit-model to be an integral part of the interconnect. infinitely fast and infinitely slow input rise-times and fits a
Modeling of the nonlinear behavior of transistors as linear smooth curve that can predict the delay and the transition-
resistors contributes to inaccuracies. Besides, the mean re- time, for this whole range, with an accuracy typically within
sponse of the gate is derived from delay bounds and can be 3% of SPICE. The tumpoints for very low and very high
very pessimistic or optimistic. To enable a faster evaluation fanouts are also derived in an analogous way. Sakurai 181,
of delay and transition-time, Bums 161 derived a closed-form [9] has also described a similar methodology, where infinitely
delay expression for a step input neglecting slope effects. fast and infinitely slow input cases are joined smoothly by
Manuscript received June 21, 1994; revised December 27, 1994. an inverting voltage, but we establish a simpler and more
S. Dutta is with the Electrical Engineering Department, Princeton Univer- practical expression for evaluating delay and output transition-
sity, Princeton, NJ 08544 USA. time. Whereas the phenomenon of negative delays has been
S. S. M. Shetti and S . L. Lusky are with Integrated Systems Laboratory,
Texas Instruments Inc., Dallas, TX USA. noted before 191, [lo], we present a more formal derivation
IEEE Log Number 9412021. of the general delay equation that explains negative delays as
0018-9200/95$04.00 0 1995 IEEE

~~ ____
DVITA et al.: A COMPREHENSIVE DELAY MODEL FOR CMOS INVERTERS 865

4 threshold voltage of the transistor and a is the velocity

I saturation index for submicron devices. a can be computed
by fixing a value for the transistor size (W), calculating IDO
and V& for W , and fitting Sakurai's current equation to the
VGS - IDScurve obtained from SPICE.
CL, the total output load that the inverter sees when
it is acting as a driver, comprises the gate capacitances
(contributed by the fanout' blocks), the diffusion capacitances,
and the interconnect capacitance. We consider situations where
the first two dominate such as within a block with close
interaction. When the inverter drives an interconnect load,
only the interconnect capacitance is included since the com-
putation of the coupling capacitance is difficult. The gate
and the diffusion capacitances are calculated using well-
known formulae involving the transistor width and length
Fig. 1. Interpretation of IDO, VDO, and RL.
and technology parameters such as gate-oxide capacitance,
side-wall and bottom-wall capacitances, length and width
a special case. All of the discussions throughout this paper reductions, moat overhang, and junction depth. The same
concentrate on the NMOS transistor or the inverter with a formulae are used in SPICE, which contribute to the closeness
rising input ramp. As shown by Sakurai [l] , the case of the of our model to SPICE.
PMOS transistor and the inverter with a falling input signal V,,, is defined as the threshold of the inverter and is that
can be analyzed in a similar fashion. point on the dc characteristic curve for which V,, = Vout.
The paper is organized as follows: Some terms and defini-
tions are clarified in Section 11. Section I11 describes Sakurai's
111. SAKURAI'S EQUATIONS FOR
original inverter-delay model and its limitations. The proposed
DELAYAND TRANSITION-TIME
transition-time and delay analysis schemes are detailed in
Sections IV and V, respectively. Results are cited in Section We present below the inverter delay and transition-time
VI, and Section VI1 draws the conclusions. Some key features equations derived by Sakurai [l]. The delay of an inverter
of the program implementation and SPICE characterization in the discharging case tpHL or the delay in the charging case
are illustrated in the Appendix. tpLH is calculated as

11. DEFINITIONS
AND PRELIMINARIES
In this section, we explain the meanings and the sig-
VTH
nificances of some symbols and terms that will be used with VT = -
extensively throughout the paper.
VDD
IDO is the drivability of a MOSFET and is calculated by where T is the input transition-time. The output transition-time
substituting VGS = VDS = VDD in the equation for the drain is given by
saturation current IDSAT. The delay and the output transition-
time of an inverter are governed entirely by IDO.
RL is the effective triode resistance of a transistor operating
in the linear region and is calculated as RL = ~ / G L where ,
GL = limvDs+o (w
) . In the equation for GL, IDLIN
denotes the linear drain-current equation and VDS is the drain-
A. Limitations of Sakurai's Model
Fig. 2 compares with SPICE the output fall-time (tf) and
to-source voltage.
the delay ( t d ) of an inverter as predicted by (1) and (2). The
VDO is the drain saturation voltage at VGS= VDD and is
delays and the fall-times are plotted as functions of input
given by VDO = IDO x RL.
transition-times (tr). All plots in this paper correspond to
A graphical interpretation of IDO,VDO, and RL is given in
inverters having 1 (the transistor channel length) = 0.8pm,
Fig. 1 that shows a typical IDS- VDS plot for an NMOS
W, (the width of the PMOS transistor) = 20pm, and W,
transistor. During the high-to-low transition at the inverter
(the width of the NMOS transistor) = 10pm. In Fig. 2, the
output, since the delay is measured at 2.5 V, VDS < 2.5 V
inverter drives a fanout of six inverters. It is evident from
(this corresponds to the region to the left of the dotted line in
the figure that the a-power law approximations are valid, and
Fig. 1) does not play any significant role. The triode region
the predicted delays and fall-times are in reasonable agreement
describes the output waveform below VDO and even though
with SPICE when the input transition-times (tr) are small (this
it has an impact on the crow-bar current, it does not affect
corresponds to the region to the left of the dotted vertical line),
the delay.
but when extrapolated beyond the regime of fast inputs, the
The transistor saturation current e q u a t p proposed by Saku-
model tends to become less accurate.
rai [l] is IDSAT = IDO ($:I$$ where VTH is the
9 Fanout is defined in the Appendix.
866 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 30, NO. 8, AUGUST 1995

1.4 I 0.1
1
tkSPICE - 0.09
tksakurpi-model ------
1.2
0.08

1 0.07

-
v
B 0.8 h

3
0.06

0.05
3 3
d 0.6 0.04

0.4

0.2
: o : :0.01 0.5 15 25

0 ‘ I
0 0.5 1 15 2 2.5 3 3.5
tr tr (ar)

Fig. 2. Output fall-time and propogation delay versus input rise-time. Fig. 4. Propagation delay versos input rise-time.

1 45
SPICE - f d , t r = 0 5 -1---
4 f d , tr-1.2 --e----
fo=l,tr=0.5+
0.8 ID0
35

3
0.6
-
%
%
1
v

3
2.5

2
0.4
15

0.2 1

05

0 0
0 0.5 1 1.5 2 2.5 3 0 1vDo 2 3 4 5
tr (as) vdo (v)

Fig. 3. Output fall-time versus input rise-time. Fig. 5. Operating point trajectory of an inverter.

According to Sakurai’s equations, with increasing values of

0.5 ns. Only after the output voltage drops to VDO, does the
t,, the output fall-time ( t f ) remains constant and the delay ( t d )
NMOS transistor enter its nonsaturation region of operation
increases with a fixed slope. However, if we replot the previous
whence the output capacitance is discharged by an effective
SPICE simulations over magnified ranges of t f , t d , and t,, as
triode resistance. This scenario, however, is true only as long
shown in Figs. 3 and 4, we see that over extended ranges of
input transition-times, the delay cannot be modeled by a line of as the input rise-time is fast enough compared to the output
zero slope and a ramp cannot be used to model the output fall- fall-time. For a fast input ramp, the inverter operating point
time. The deviation of Sakurai’s inverter delay model from the reaches the IDS curve corresponding to VGS = VDD early in
SPICE results, for low fanouts and large input transition-times, the discharging cycle and stays there for a considerable period
can be explained with the help of Fig. 5. In this figure, the of time so that the output capacitor is primarily discharged by
operating-point trajectories of an inverter, under three different the peak value of the saturation current. Note that a transition
input-output conditions, are superimposed on a family (for at the input of an inverter driving a high fanout, that could be
varying VGS values) of IDS - VDS NMOS transistor curves. regarded as “fast” when compared with the output transition,
Sakurai assumes that for a rising input to an inverter, the input may not be considered as fast when the fanout is very low.
signal approaches VDDbefore the output of the inverter starts If the inverter is very lightly loaded and/or the input
to move. What this translates into on the IDS - VDS plane is a slow-moving signal, the current contribution from the
is that the load capacitance is initially discharged by a time- PMOS transistor cannot be neglected totally and the NMOS
dependent current source for a relatively short period of time transistor saturation current never reaches its peak value of
within which the operating point of the inverter reaches the IDS IDO. Therefore, the operating point never reaches this second
curve corresponding to VGS = VDD and traces this curve for region (characterized by VGS = VDD and IDSAT = IDO)of
some time during which the output capacitance is discharged operation. The discharging time of the output capacitance, in
by a constant current-source of value IDO.This happens when this case, is small compared to the input transition-time and the
the input signal is fast and the fanout is sufficiently high. Such load capacitance is discharged by an NMOS saturation current
a situation is depicted in Fig. 5 by the cross (*)-point line that is less than the maximum drive current ( I D o )possible.
corresponding to a fanout of six and an input rise-time of To represent the situation graphically in Fig. 5, let us plot
DIJTrA et al.: A COMPREHENSIVEDELAY MODEL FOR CMOS INVERTERS 867

the operating point trajectory of the inverter for two separate

cases-slow input (1.2 ns) and low fanout (fanout = 1). As is
evident from the diamond (0)-marked and the plus(+)-marked
lines, the operating point, in either case, follows a path where
the discharging current never reaches IDO.Hence, Sakurai's
assumption that the output capacitance of the inverter is
discharged by a saturation current of magnitude IDO is not
valid anymore. The delay expression derived on the basis of
this assumption cannot be used to model the inverter when the
input rise-time is large or the fanout is small.

Iv. MODELING
THE OUTPUT W S I T I O N - T M E
v n
This section describes our approach to accurately model the ' 0 100 200 300 400 500 600 700 800
tr (ns)
output transition-time of an inverter over the whole range of
input transition-times and fanout. Conventionally, researchers Fig. 6 . Asymptotic limit of output transition-time.
have identified the 90% and 10% points on the output curve
and calculated the slope from the time difference between
these points. The selection of these points is based on the
fact that for a power supply voltage of 5 V and for usual
circuit configurations, the output waveform is governed by
approximately a constant slope between these points. When
we scale the power supply voltages for different technologies,
these points may not be suitable for calculating the transition-
time.
Inspecting Sakurai's equation, we see that the peak satura-
tion current is given by

,/'.
0 '
For fast input transitions, we calculate the output (ac) slope as 0 1 2 3 4 5
Vin (v)
IDO/CLand divide VDDby this slope to obtain the time for a
voltage transition of VDD.As shown in the results, the output Fig. 7. DC transfer curve.
transition-time thus obtained is typically within 3% of SPICE.
When the input rise-time is extremely slow, a change in the shows that for a sufficiently large fanout, the transition-time
output voltage is solely limited by the change in the input curve approaches the calculated asymptote for large input rise-
voltage and so, the output voltage follows the dc voltage times. The derivation of the asymptotic slope is illustrated in
characteristics of the inverter. It is obvious that for all input the following subsection.
transition-times greater than a particular critical value tr,,
the output of the inverter will follow the same dc curve. In
other words, for an input transition-time t r greater than tr,, A. DC Slope as an Asymptotic Limit
if the time axis is scaled such that t r corresponds to VDD, As mentioned earlier, for all input rise-times greater than
then the scaled transient response curve will overlap with the tr,, the transient response of the inverter follows the dc
dc voltage-transfer-characteristic curve of the inverter. This characteristic curve. On a typical dc curve for an inverter,
implies that the transition-time curves, for increasing values as shown in Fig. 7, we can identify the straight portion of
of fanout, asymptotically approach the same slope, which we the curve and determine the points v l , v2, v3, and v4 such
call the asymptotic limit of the output transition-time. The that for a AV,, (= v 2 - v l ) change in the input voltage, the
slope of the asymptote is calculated from the slope of the corresponding change in the output voltage is given by AVout
dc transfer curve. The value of tr, depends on the fanout (= w4 - v3). gives the slope of the dc curve in the
(or the capacitive loading) of the gate and increases as the region where the major transition takes place. A line drawn at
fanout increases. This observation leads us to scale both the an angle of 45" through the origin of the plot intersects the dc
input and the output transition-times by the fanout, so that, curve at a point where Vn = Vout.This point represents the
as the fanout increases, the relative separation between the threshold of the inverter denoted by V,,,.
transition-time curves for various fanouts now asymptotically We perform some geometrical constructions in order to
approaches zero. (The curves virtually overlap for fanouts of derive the slope of the dc asymptote. As shown in Fig. 8, we
six or more.) Once we know the slope of the dc asymptote place a rotated version of the dc transfer curve adjacent to the
and the value of the output fall-time for a step input, we seek transient response (for a very slow input signal) of an inverter.
an expression that connects the zero and the infinite-rise-time The plot on the left is the ac response of the inverter for an
cases by a smooth curve for the various fanout cases. Fig. 6 extremely slow input rise-time of 200 ns. V, is the output
868 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 30, NO. 8, AUGUST 1995

A major impact of scaling the curves by the fanout is that

the above coefficients do not vary with the individual transistor
sizes so long as the @-ratio(Wp/Wn) remains the same. Also
note that (4) can be recast as e +
= (1 $) x Slope, showing
that the scaled output transition-time is independent of both
trin and fo but is sensitive to their ratio 7.

v . INVERTER DELAYFOR SLOW INPUT SIGNALS

For the delay modeling of inverters, we identify a “kink-
point,” once again, on the input-transition-time axis. When
the input signals are faster than this “kink-point’’ value, we
use Sakurai’s equation to model the delay. For slower signals,
0 Vout(V) 5
we derive an expression as before.
Fig. 8. Output fall-time determined by dc slope. The delay of an inverter for very large input transition-times
can also be found from the dc transfer curve and there is again
response waveform corresponding to the input ramp V,. On an asymptote that the delay values approach in the limit.
the right is the dc curve for the same inverter, plotted with V;,
as the vertical and Vout as the horizontal axis. Vertical lines A. Derivation of the Delay Asymptote
drawn through the points p l and p2 intersect the V;, = Vout
line at points p 3 and p4. The vertical distance between p 3 On the transient analysis plot, any slow input signal, for
and p4 determines AV,,, and horizontal lines drawn through which the inverter output follows the dc transfer curve, in-
these points intersect the output transient-response curve at the tersects the output voltage waveform at the threshold of the
points p 6 and p 5 . AV;, is determined by the vertical distance inverter KnV. The input has to pass through the threshold
between pl and p2, and the horizontal lines drawn through point as it is at this voltage that Kn = Vout, and the input
these points also have a corresponding intercept on the input cannot reach this threshold either before or after the output
waveform vi. For the transient-analysis, if we determine the ac does because the inverter output is tracing the dc curve. Let m
slope of the V , and V, curves, respectively from the intercepts denote the slope of the output response of the inverter. We are
of theAV,, and the AV,,, lines on them, the ratio of the input
S1oPev -
and the output slopes can be expressed as Slopev; - AV av,,,. transfer curve m = w.
considering the dc case and so m can be obtained from the dc
Let the output response (v,) of the
inverter be approximated by the straight line V, = m x V; c. +
Since VDDdivided by slope yields the transition-time, we can Note that m is negative for a rising input signal. The output
write the previous equation as % = *. S O , for all inputs
passes through V,, and so, the coordinates of the inverter
a constant ratio given by z.
slower than tic, the output and the input transition-times bear
This is the slope of the dc
asymptote. For the plot in Fig. 6, the slope of the dc asymptote
threshold satisfy the straight-line equation giving the intercept
value
is calculated to be 0.075.
c = KnV(1- m). (5)
B. Joining End-Points by a Smooth Curve
From a number of simulations, we infer that a general If we measure the delay at half of the power supply voltage,
expression of the form the delay is (t2 - t l ) , where t2 is the time when the output

trout = (1 + 5)x trin x Slope (4)

response reaches vDD/2 and t l is the time for the input to
r e a c h V ~ ~ / Denoting
2. the input transition-time by trin, we
can write t l = trin/2. If V represents the input voltage when
where = trin/fo’ be in with (3) the output voltage reaches vDD/2, t2 corresponds to the time
to model the output transition-times over the whole range taken by V , to reach voltage V, which can be expressed as
of input transition-times for any fanout (fo). Slope in the c. Using (5), we get
vDD/2 = +

above equation refers to the slope of the dc asymptote. The

coefficients a and b are functions of the inverter @-ratioand
the fanout. A predetermined set of SPICE runs produces a K n v (1 - m)
m
(6)
table of coefficient-values, and given a @-ratio and a fanout,
the exact coefficients are determined from the table using a
Since the input waveform slope is vDD/trin, the time taken
two-dimensional interpolation formula.
we identify a 6Gkink-point77 on the input transition-time by the input signal to reach V , = v is given by t2 =
Substituting for from we get
e.
axis. Below this ‘‘kink-point,’’ the output transition-time is (6)y

evaluated using Sakurai’s model, and above the point, we

use the proposed equation to model the transition-time. The 1 Knv(1 - m )
(7)
“kink-point’’ is where the two solutions meet.
D U T A et al.: A COMPREHENSIVE DELAY MODEL FOR CMOS INVERTERS 869

5 0.45

Od -

deIayforfanout=6 - ~
0.35 r
de m p t o t e ------

tf-SPICE-
- tf-model----
-15 td-SPICE
td-model -
-20 - 0.15

-25 .
0.05
-30 -
~

-35
0 1 0 0 u I o 3 0 0 4 0 0 5 0 0 6 0 0
h' (us)

Fig. 9. Asymptotic behavior of dc delay

has a positive slope and the delay curve is restricted to the

The delay equation can now be written as first quadrant. This implies that if we measure the inverter
delay as the time difference between the input and the output-
Delay = t 2 - tl = trin x response waveforms at a voltage point (on the input curve)
which is above the threshold of the inverter, then there exists
a possibility for this calculation to yield a negative delay value.
Delay and input transition-time bear a ratio that is a function of
the dc slope and the threshold of the inverter. This ratio gives
C. The Delay Equation
the slope of the asymptote that the delay curves approach when
plotted for lar e input transition-times. The slope of the dc A search for a continuous curve that smoothly joins the
asymptote is /+
- mVDD - i].
Fig. 9 shows the delay
zero-rise-time delay with the delay asymptote leads us to an
expression of the form
versus input rise-time plot for an inverter driving a high fanout.
The delay curve approaches the slope of the asymptote for
extremely large input transition-times.

B. Explanation of Negative Delays where 7 = trin/fo and Dslopeis the slope of the dc asymptote
that the delay curves follow at infinite input rise-times. If
When the input signal is slow andor the fanout is low, the the coefficients a and b are properly determined, the curve
condition for the delay to be always positive can be written represented by the above equation accurately models the
as t 2 - tl 2 0. From (8) inverter delay over the whole range of input transition-times
and fanout. The coefficients, as before, are functions of the
inverter P-ratio and the fanout (fo) and are determined by
a table look-up. Note that the scaled delay, like the scaled
transition time, is independent of trin and f o but is sensitive
Thus, the delay in the dc case depends on the voltage dif- to their ratio T .
ference between the inverter threshold and the voltage v d at
which the delay for a rising input is measured. It follows that:
VI. RESULTS
Figs. 10-13 compare with SPICE the delay and the
transition-time waveforms predicted by the proposed model.
t f ,t d , and f o refer to the outputfall-time, the input rise-time,
and the fanout, respectively.

v d is usually chosen to be v D D / 2 . When v d > V,,, for fast

inputs, the delay increases with the rise-time of the ramp, and VII. CONCLUSION
then starts decreasing, and finally goes negative with very A scheme to accurately evaluate the delay and the output
high values of the input transition-time. trc, in this case, transition-time of an inverter is presented. The model used
can be defined as that value of the input transition-time for is analytical and comprehensive and can predict the inverter
which the delay curve crosses the horizontal axis and starts delay with reasonable accuracy over any range of input signal
going negative. The curve approaches its asymptotic limit in slopes and output loading. Results obtained from a program
the fourth quadrant because the rising-input delay asymptote implementation have been found to be typically within 3% of
has a negative slope. If v d < Knv, the delay asymptote SPICE.
870 IEEE JOURNAL OF SOLID-STATE CIRCUlTS, VOL. 30, NO. 8, AUGUST 1995

o s , , , , , , , I , , , A.1 Spice Characterization

Obtain the current and the voltage equations from SPICE.
For a given technology, calculate the velocity-saturation index
Oa7I
0.6 (a) via SPICE-characterization. This is a one-time process.
05 -
A.2 Modeling the Output Fall-Time and
0.4 - the Delay of an Inverter
1) Decide on a W, and a W, for the inverter and calculate
P(= w,/ wn1 *

2) Calculate the transistor diffusion capacitances Codiff at

the inverter output.
0.1
0 03 0.4 0.6 Os 1 13 1.4 1.6 IS 2 3) Decide on a fanout cfo). A fanout of one is a capacitive
tr (as)
loading equal to the input capacitance of an inverter
Fig. 11. tf,td plot for p = 1 , f o = 6. of size W, and W,. The capacitance for unit fanout
is denoted by CLi,. The external capacitive loading
is given by CL = CL;, x fo. Therefore, the total
0.55
I capacitance used in the modeling equations is C T =
05 -
-
tf-SPICE-
tf-model
td.sPIcE .....
+
CL Codiff.
0.45
td-model ----
4) Determine the output fall-time for a step input using
0.4 - Sakurai’s equation and obtain the slope ( A S S ) of the dc
0.35 - asymptote for an injnite input rise-time from the slope
9 03 - ( D C S ) of the inverter voltage-transfer-characteristic:
S
ri A S S = l/DCS.
5 ) To join the extreme points (obtained in the previous
step) by a smooth curve, run SPICE on the inverter
for various irt values. The corresponding output fall-
times (oft’s) determine the smooth curve represented by
0.2 0.4 0.6 OS 1 1.2 1.4 1.6 1.8 2 oft = (1 + $) x irt x ASS, where r = E. The
tr (as) coefficients a1 and b l are determined by a curve-fitting
Fig. 12. tf,td plot for p = 2 . 5 , f O = 1. procedure.
6) Repeat all of the above steps for various values of P and
f o (that involves recalculating the new coefficients a1
and b l each time).
7) Determine the delay for a step input from Sakurai’s
delay equation and calculate the slope ( A S S D )of the dc
asymptote for an infinite input rise-time from the slope
( D C S ) of the dc voltage-transfer-characteristic and the
inverter threshold (Knv)
Knv(l - D C S )
A S S D = --
2DCS
1 [ DCSVDD
8) To join the extreme points (obtained in the previous
step) by a smooth curve, run SPICE on the inverter
for various irt values. The corresponding delay values
determine the smooth curve represented by delay =
(-1 + $-) x irt x A S S D , where T = irt/fo. The
coefficients a2 and b2, once again, are determined by a
curve-fitting procedure.
In the future, we would like to model NAND, NOR, 9) As before, run experiments for various values of p and
complex gates, and pass-transistor circuit configurations using f o and generate a two-dimensional table of coefficients
a method similar to the one followed in case of the inverter. (a2 and b2).
We also wish to extend our delay model to include process 10) A symbolic program to determine the output fall-time
variations. and the delay can now be written as
9
Inputs: irt, W,, W,, fo,VDD, and temperature
APPENDIX
Determine: coefficients a l , b l , a2, b2 by inter-
The steps in deriving our delay and transition-time equations polation and “kink-points” TO, 71, 7 2 , and 7 3
for an inverter are outlined below. depending upon f o and ,B.
DUlTA et al.: A COMPREHENSIVEDELAY MODEL FOR CMOS INVERTERS 871

Define: r = irt/fo, V, = 2,
and SS = Santanu Dutta received the B.Tech. degree, with

b.5 - 54. honors, in electronics and electrical communication

engineering from the Indian Institute of Technology,
Kharagpur in 1987, the M.A. degree in engineering
Compute output fall-time (oft): from Princeton University, Princeton, NJ in 1994,
and the M.S. degree in electrical engineering from
oft = { (1
(
VDDx CT)
ID0
+ 3) x irt x ASS
if 0 5 r < 70
if r 2 ro
the University of Texas at Austin in 1990.
From 1987 to 1989, he was a full-time research
staff member with the VLSI Design Laboratory,
Texas Instruments (TI), Dallas, TX, where he was
Compute delay: involved in the research and development of CAD
tools. As a student at University of Texas at Austin, while on a leave of absence
from TI from 1989 to 1991, his main focus was path-tracing algorithms
IF (Knv < V D D / ~ ) for interconnect analysis. From 1991 to 1992, he worked part-time at Ross
Sakurai Delay if 0 5 r < r1 Technology Inc., where his primary responsibility was as a circuit designer and

delay =
+
S S x irt [(-l+ $) a layout engineer. Since September 1992, he has been pursuing graduate work
in computer engineering at Princeton University. His Ph.D. research involves
.ASS - S S ] x r 2 x f o if r1 5 r < 7-2 design and analysis of video signal processing systems. His main research
interests include video signal processing, circuit simulation and analysis, and
design and synthesis of low-power digital systems.

Sakurai Delay if 0 5 7 < 73

delay =
irt x ASS if r 2 7-3
Shivaling S. Mahant Shetti received the B. Tech.
degree, with honors, in electrical engineering from
It is to be noted that 7;’s actually correspond to particular Indian Institute of Technology, Bombay, India in
values of r = (irt/fo). The equations, that have terms with r 1972 and the Ph.D. and Sc.M. degrees in electrical
sciences from Brown University, Providence, RI in
in the denominator, are used only when 7 is greater than some 1977 and 1975, respectively.
positive value (ri)-therefore, the equations need not be and Since joining Texas Instruments, Dallas, TX in
are in fact not defined for r = 0. 1982, he contributed to many projects including
the design and testing of the 72K VHSIC SRAM,
programmatic generation of the submicron CMOS
REFERENCES testchips, Statistical Parametric Data Analysis and
Design Rule Synthesis (SPADS), 32-b LISP chip design and debug, successful
T. Sakurai and R. Newton, “Alpha-power law MOSFET model and commission of the first MegaOne tester at Texas Instruments, and parametric
its applications to CMOS inverter delay and other formulas,” IEEE J. testing for EPIC1 technology. He was elected a Senior Member of the
Solid-State Circuits, vol. 25, pp. 584-593, Apr. 1990. Technical Staff in 1987 and managed the Design Engineering Branch from
L. Brocco, S. Mccormik, and J. Allen, “Macromodeling CMOS circuits 1987 to 1989. In 1989, he went to Texas Instruments, India to set up the Lin-
for timing simulation,” IEEE Trans. Computer-AidedDesign, vol. 7, pp. ASIC Design Center. In 1990, he retumed to SPDC as the Branch Manager
1237-1249, Dec. 1988. of the Technology and Circuit Characterization Branch and is currently
F. Chang, C. Chen, and P. Subramaniam, “An accurate and efficient responsible for 0 . 5 p m technology design issues, parametric testing, functional
gate level delay calculator for MOS circuits,” in 25th ACM/IEEE Design testing, SPICE model verification and delivery, and electron beam-based
Automation ConJ, pp. 282-287, 1988. parametric and functional testing. He designed chips for fuzzy logic and
L. Nagel, “SPICE2: A computer program to simulate semiconductor clustering. He worked on a low-power gate-array basecell and is currently
circuits,” University of Califomia, Berkeley, Memo ERL-M520, May pursuing low-power image compressions algorithms. He has published more
9, 1975. than 18 papers, holds 8 patents, and has over 14 patent applications pending.
R. Putanda,“Auto-delay: A program for automatic calculation of delays
in LSWLSI chips,” in 19th ACM/IEEE Design Automation C o f , pp.
616-621, 1982.
J. R. Burns, “Switching response of complementary symmetry MOS
transition logic circuits,” RCA Rev., vol. 25, pp. 627461, 1964. Stephen L. Lusky (S’73-M’75) received the B.S
N. Hedenstiema and K. 0. Jeppson, “CMOS circuit speed and buffer (magna cum laude) and M.S.E.E. degrees from the
optimization,” IEEE Trans. Computer-Aided Design, pp. 27G281, Mar. University of Michigan, Ann Arbor by 1975.
1987. He is a Member of the Technical Staff with the
T. Sakurai and Richard Newton, “Delay analysis of series-connected Integrated Systems Laboratory, Texas Instruments,
MOSFET circuits,” IEEE J. Solid-State Circuits, vol. 26, no. 2, pp. Dallas, TX. He has been involved in CMOS design
122-131, Feb. 1991. including several large mcroprocessors, venfica-
-, “A simple MOSFET model for circuit analysis,” IEEE Trans. tion, testability, and CAD development for accurate
Elecfron Devices, vol. 38, no. 4, pp. 887-894, Apr. 1991. timing analysis and design synthesis. He is presently
D. Auvergne, N. Azemard, and D. Deschacht, “Input waveform slope working on issues regarding digital video over a
effects in CMOS delays,” IEEE J. Solid-State Circuits, vol. 25, pp. broadband network.
1588-1590, Dec. 1990. Mr. Lusky is a member of Tau Beta Pi.