Chapter 2

A TOP-LEVEL VIEW OF COMPUTER FUNCTION AND

INTERCONNECTION
Key Points
• The major computer system components (processor, main memory, I/O modules) need to
be interconnected in order to exchange data and control signals.
• Thus, at a top level, we can describe a computer system by:
1. Describing the external behavior of each component – that is, the data and control
signals that it exchanges with other components
2. Describing the interconnection structure and the controls required to manage the
use of the interconnection structure.
• The most popular means of interconnection is the use of a shared system bus consisting
of multiple lines.
Key design elements for buses include:
➢ arbitration – whether permission to send signals on bus lines is controlled
centrally or in a distributed fashion
➢ timing – whether signals on the bus are synchronized to a central clock or are sent
asynchronously based on the most recent transmission
➢ width – number of address lines and number of data lines

Computer Components
Virtually all contemporary computer designs are based on concepts referred to as von
Neumann architecture.
• Von Neumann architecture is based on three key concepts:
➢ Data and instructions are stored in a single read-write memory.
➢ Contents of this memory are addressable by location, without regard to the type of
data contained there.
➢ Execution occurs in a sequential fashion from one instruction to the next.
• There is a small set of basic logic components that can be combined in various ways to
store binary data and to perform arithmetic and logical operations on that data.
• If there is a particular computation to be performed, a configuration of logic components
designed specifically for that computation could be constructed.

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• We can think of the process of connecting the various components in the desired
configuration as a form of programming.
• The resulting “program” is in the form of hardware and is termed a hardwired program.
• Hardwired programming is done by constructing a configuration of hardware logical
components to perform a particular set of arithmetic and logic operations on a set of data.

• Programming is now much easier. Instead of rewiring the hardware for each new
program, all we need to do is provide a new sequence of codes.
• Each code is an instruction and part of the hardware interprets each instruction and
generates control signals.
• To distinguish this new method of programming, a sequence of codes or instructions is
called software

• Two major components of the system are an instruction interpreter and a module of
general-purpose arithmetic and logic functions.

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• Several other components are needed to yield a functioning computer. Data and
instructions must be put into the system.
• For this we need some sort of input module. This module contains basic components for
accepting data and instructions in some form and converting them into an internal form of
signals usable by the system.
• A means of reporting results is needed, and this is in the form of an output module.
• Taken together, these are referred to as I/O components.
• An input device will bring instructions and data in sequentially.
• Thus, there must be a place to store temporarily both instructions and data.
• That module is called memory or main memory to distinguish it from external storage
or peripheral devices.
• Figure shows top-level components and suggests the interactions among them.

• CPU exchanges data with memory. For this purpose, it typically makes use of two
internal registers:
➢ a memory address register (MAR), which specifies the address in memory for the
next read or write

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 ➢ a memory buffer register (MBR), which contains the data to be written into
memory or receives the data read from memory.
• Similarly, an I/O address register (I/OAR) specifies a particular I/O device.
• An I/O buffer (I/OBR) register is used for the exchange of data between an I/O module
and the CPU.
• A memory module consists of a set of locations, defined by sequentially numbered
addresses.
• Each location contains a binary number that can be interpreted as either an instruction or
data.
• An I/O module transfers data from external devices to CPU and memory, and vice versa.
It contains internal buffers for temporarily holding these data until they can be sent on.

Computer Function
• Basic function performed by a computer is execution of a program, which consists of a
set of instructions stored in memory.
• Processor does actual work by executing instructions specified in program.
• In its simplest form, instruction processing consists of two steps: the processor reads
(fetches) instructions from memory one at a time and executes each instruction.
• Program execution consists of repeating the process of instruction fetch and instruction
execution. The instruction execution may involve several operations and depends on the
nature of the instruction.
• The processing required for a single instruction is called an instruction cycle.
• Program execution halts only if the machine is turned off, some sort of unrecoverable
error occurs, or a program instruction that halts the computer is encountered.

• At the beginning of each instruction cycle, the processor fetches an instruction from
memory.
• In a typical processor, a register called the program counter (PC) holds the address of the
instruction to be fetched next.

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• The processor always increments the PC after each instruction fetch so that it will fetch
the next instruction in sequence.
• The fetched instruction is loaded into a register in the processor known as the instruction
register (IR).
• The instruction contains bits that specify the action the processor is to take.
• The processor interprets the instruction and performs the required action.
In general, these actions fall into four categories:
• Processor-memory: Data may be transferred from processor to memory or from
memory to processor.
• Processor-I/O: Data may be transferred to or from a peripheral device by
transferring between the processor and an I/O module.
• Data processing: The processor may perform some arithmetic or logic operation
on data.
• Control: An instruction may specify that the sequence of execution be altered.
Example:
• Consider a simple example using a hypothetical machine that includes the characteristics
shown below.

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 Example:
• The processor contains a single data register, called an accumulator (AC).
• Both instructions and data are 16 bits long.
• The instruction format provides 4 bits for the opcode.
• A program fragment adds contents of memory word at address 940 to content of memory
word at address 941 and stores result at address 941.
• Program Counter (PC) register contains the value 300.
• To summarize:
• Step 1: Load AC from 940
• Step 2: Add contents of 941 to AC
• Step 3: Store AC to 941
Example:
1. PC contains 300, address of first instruction. This instruction (value 1940 in hexadecimal)
is loaded into instruction register IR and PC is incremented.
2. First instruction in IR is 1940.
1. First 4 bits (1) indicates that AC is to be loaded.
2. Remaining 12 bits specify the address (940) from which data are to be used.
3. Next instruction (5941) is fetched from location 301 and PC is incremented.
4. Old contents of AC and content of location 941 are added and result is stored in AC.
5. Next instruction (2941) is fetched from location 302 and PC is incremented.
6. Content of AC are stored in location 941.

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 Solution

• Virtually all computers provide mechanism by which other modules (I/O, memory) may
interrupt normal processing of processor.
• Interrupts are provided primarily as a way to improve processing efficiency.
• The most common classes of interrupts:
➢ Program: Occurs as a result of an instruction execution, such as arithmetic
overflow, division by zero, etc.
➢ Timer: Generated by a timer within the processor and allows the operating
system to perform certain functions on a regular basis.
➢ I/O: Generated by an I/O controller, to signal normal completion of an operation
or to signal a variety of error conditions.
➢ Hardware failure: Generated by a failure such as power failure or memory parity
error.

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• Most external devices are much slower than processor. Suppose that processor is
transferring data to a printer using instruction cycle. After each write operation, processor
must pause and remain idle until printer catches up.
• Length of this pause may be order of many hundreds or even thousands of instruction
cycles that do not involve memory.
• This is a very wasteful use of processor. With interrupts, the processor can be engaged in
executing other instructions while an I/O operation is in progress.
• From the point of view of the user program, an interrupt is just an interruption of the
normal sequence of execution.
• When the interrupt processing is completed, execution resumes. Thus, the user program
does not have to contain any special code to accommodate interrupts; the processor and
the operating system are responsible for suspending the user program and then
resuming it at the same point.

• To accommodate interrupts, an interrupt cycle is added to the instruction cycle.

• In the interrupt cycle, the processor checks to see if any interrupts have occurred,
indicated by the presence of an interrupt signal.
• If no interrupts are pending, the processor proceeds to the fetch cycle and fetches the next
instruction of the current program.
• If an interrupt is pending, the processor does the following:

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 ➢ It suspends execution of the current program being executed and saves its context
on the system stack – a special place in memory.
➢ It sets the program counter to the starting address of an interrupt handler routine.

• The processor now proceeds to the fetch cycle and fetches the first instruction in the
interrupt handler program, which will service the interrupt.
• The interrupt handler program is generally part of the operating system.
• The processor can be employed much more efficiently with the use of interrupts.
Example:
• The user program performs a series of WRITE calls interleaved with processing.
• Code segments 1, 2, and 3 refer to sequences of instructions that do not involve
I/O.
• The WRITE calls are to an I/O program that is a system utility and that will
perform the actual I/O operation.
• The I/O program consists of three sections:
1. Code segment 4 is used to prepare for the actual I/O operation.
2. The actual I/O operation.
3. Code segment 5 is used to complete the operation.

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Example: Solution
(Short I/O wait)

Example: Solution
(Long I/O wait)
WRIT WRIT
E E

WRIT
WRIT E
E

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 • The discussion so far has focused only on the occurrence of a single interrupt. However,
multiple interrupts can occur.
• For example, a program may be receiving data from a communications line and printing
results.
➢ The printer will generate an interrupt every time that it completes a print
operation.
➢ The communication line controller will generate an interrupt every time a unit of
data arrives.
Two approaches can be taken to dealing with multiple interrupts.
1 The first is to disable interrupts while an interrupt is being processed. A disabled
interrupt simply means that the processor can and will ignore that interrupt request signal.
If an interrupt occurs during this time, it generally remains pending and will be checked
by the processor after the processor has enabled interrupts. This approach is nice and
simple, as interrupts are handled in strict sequential order.
Sequential Interrupt Processing

2. A second approach is to define priorities for interrupts and to allow an interrupt of higher
priority to cause a lower-priority interrupt handler to be itself interrupted.

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 Nested Interrupt Processing

Example:
• Consider a system with three I/O devices: a printer, a disk and a
communications line, with increasing priorities of 2, 4 and 5, respectively.
• A user program (priority=0) begins at t=0.
• At t=10, a printer interrupt occurs.
• At t=15, a communications line interrupt occurs.
• While this routine is executing, a disk interrupt occurs at t=20.
• Assume that all of the devices need 10 seconds to execute in the CPU.

Solution for sequential interrupt processing

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 Solution for nested interrupt processing

Interconnection Structures

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• A computer consists of a set of components or modules of three basic types (processor,
memory, I/O) that communicate with each other. In effect, a computer is a network of
basic modules.
• Thus, there must be paths for connecting the modules. The collection of paths connecting
the various modules is called the interconnection structure.
• Interconnection structure must support following types of transfers:
➢ Memory to CPU: Processor reads an instruction or a unit of data from
memory.
➢ CPU to memory: Processor writes a unit of data to memory.
➢ I/O to CPU: Processor reads data from an I/O device.
➢ CPU to I/O: Processor sends data to an I/O device.
➢ I/O to or from memory: An I/O module is allowed to exchange directly with
memory, without going through processor, using Direct Memory Access
(DMA).
• Over the years, a number of interconnection structures have been tried. By far the most
common is the bus and various multiple-bus structures.

Bus Interconnection
• A bus is a communication pathway connecting two or more devices. A key characteristic
of a bus is that it is a shared transmission medium.
• Multiple devices connect to the bus, and a signal transmitted by any one device is
available for reception by all other devices attached to the bus.
• If two devices transmit during the same time period, their signals will overlap and
become garbled. Thus, only one device at a time can successfully transmit.
• Typically, a bus consists of multiple communication pathways, or lines. Each line is
capable of transmitting signals representing binary 1 and binary 0.
• Over time, a sequence of binary digits can be transmitted across a single line. Taken
together, several lines of a bus can be used to transmit binary digits simultaneously (in
parallel).
• For example, an 8-bit unit of data can be transmitted over eight bus lines.
• Computer systems contain a number of different buses that provide pathways between
components at various levels of the computer system hierarchy.
• A bus that connects major computer components (processor, memory, I/O) is called a
system bus.
• The most common computer interconnection structures are based on the use of one or
more system buses.

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 Bus Structure
➢ A system bus consists, typically, of from about 50 to hundreds of separate lines.
Each line is assigned a particular meaning or function.
➢ Although there are many different bus designs, on any bus the lines can be
classified into three functional groups: data, address, and control lines.
➢ In addition, there may be power distribution lines that supply power to the
attached modules.

➢ The data lines, collectively, are called the data bus.

➢ The data bus may consist of 32, 64, 128, or even more separate lines, the number of lines
being referred to as the width of the data bus.
➢ Because each line can carry only 1 bit at a time, the number of lines determines how
many bits can be transferred at a time.
➢ The width of the data bus is a key factor in determining overall system performance.
➢ For example, if the data bus is 32 bits wide and each instruction is 64 bits long,
then the processor must access the memory module twice during each instruction
cycle.
➢ The address lines are used to designate the source or destination of the data on the data
bus.
➢ The width of the address bus determines the maximum possible memory capacity of the
system.
➢ Furthermore, the address lines are generally also used to address I/O ports.
➢ The control lines are used to control the access to and the use of the data and address
lines.
➢ Because the data and address lines are shared by all components, there must be a means
of controlling their use.

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 Typical control lines include:
➢ Memory write: Causes data on the bus to be written into the addressed location.
➢ Memory read: Causes data from the addressed location to be placed on the bus.
➢ I/O write: Causes data on the bus to be output to the addressed I/O port.
➢ I/O read: Causes data from the addressed I/O port to be placed on the bus.
➢ Transfer ACK: Indicates that data have been accepted from or placed on the bus.
➢ Bus request: Indicates that a module needs to gain control of the bus.
➢ Bus grant: Indicates that a requesting module has been granted control of the bus.
➢ Interrupt request: Indicates that an interrupt is pending.
➢ Interrupt ACK: Acknowledges that the pending interrupt has been recognized.
➢ Clock: Is used to synchronize operations.
➢ Reset: Initializes all modules.
➢ The operation of the bus:
➢ If one module wishes to send data to another, it must do two things:
✓ obtain the use of the bus
✓ transfer data via the bus
➢ If one module wishes to request data from another module, it must:
✓ obtain the use of the bus
✓ transfer a request to the other module over the appropriate control and
address lines
✓ it must then wait for that second module to send the data
➢ If a great number of devices are connected to bus, performance will suffer. There are two
main causes:
✓ Propagation delay: Time it takes for devices to coordinate use of bus.
✓ Bus may become a bottleneck as total data transfer demand approaches
the capacity of the bus.
➢ Most computers systems use multiple buses, generally laid out in a hierarchy.

Traditional hierarchical bus architecture:

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• There is a local bus that connects processor to a cache memory and that may support one
or more local devices.
• Use of a cache structure insulates CPU from frequent accesses to main memory.
• Main memory can be moved off local bus onto a system bus.
• It is possible to connect I/O controllers directly onto system bus. A more efficient
solution is to make use one or more expansion buses for this purpose:
➢ An expansion bus interface buffers data transfers between system bus and I/O
controllers on expansion bus.
➢ An expansion bus interface insulates memory-to-processor traffic from I/O traffic.

High performance bus architecture:

• Traditional bus architecture is reasonably efficient but begins to break down as higher
and higher performance is seen in the I/O devices.
• Solution to this is to incorporate a high-speed bus. Specifically designed to support high-
capacity I/O devices.
➢ Brings high-demand devices into closer integration with processor and at the
same time is independent of processor.
➢ Changes in processor architecture do not affect high-speed bus and vice-versa.
• This arrangement is sometimes known as a mezzanine architecture.

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High performance bus architecture

Peripheral component interconnect (PCI)

• The peripheral component interconnect (PCI) is a popular high-
bandwidth, processor-independent bus that can function as a
mezzanine or peripheral bus.
• Compared with other common bus specifications, PCI delivers
better system performance for high-speed I/O subsystems (e.g.
graphic display adapters, network interface controllers, disk
controllers, and so on).
• But it is not just a high speed that makes PCI attractive. PCI is
specifically designed to meet economically the I/O requirements of
modern systems; it requires very few chips to implement and
supports other buses attached to the PCI bus.
• Figure shows a typical use of PCI in a single-processor system.
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 • A combined DRAM controller and bridge to the PCI bus
provides tight coupling with the processor and the ability to
deliver data at high speeds.
• The bridge acts as a data buffer so that the speed of the PCI
bus may differ from that of the processor’s I/O capability.

• In a multiprocessor system, one or more PCI configurations may be connected by bridges

to the processor’s system bus.
➢ The system bus supports only the processor/cache units, main memory, and the
PCI bridges.
➢ Again, the use of bridges keeps the PCI independent of the processor speed yet
provides the ability to receive and deliver data rapidly.

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