SYNOPSIS REPORT

(April – 2022)
On

Design and Implementation of high speed 32 bit Vedic

Arithmetic unit on FPGA

BY
ASHISH SUBHASH PHUSE
From
VLSI and Embedded System
(Department of Electronics and Telecommunication Eng.)

MIS NO: 122035015

Under the Guidance of
Prof. Pankaj.P.Tasgaonkar

DEPARTMENT OF ELECTRONICS AND

TELECOMMUNICATION ENGINEERING
COLLEGE OF ENGINEERING, PUNE
CONTENTS

1 Introduction 1
2 Literature Survey 3
3 Problem statement 5
4 Objectives 5
5 Methodology 6
6 Resources required 13
7 Plan of execution 16
References 17
1..INTRODUCTION

BACKGROUND
Multiplication is a crucial unfussy, basic function in arithmetic procedures and
Vedic mathematics is an endowment prearranged for the paramount of human
race, due to the capability it bestows for quicker intellectual computation.

Beside multiplier is power hungry components so reducing their power

dissipation satisfying the overall power budget of digital computer.

2>>Low power very large-scale integration (VLSI) circuit is vital criteria

for designing an energy efficient design for prime performance and the
compact device design.
>>Multiplier plays an important role for planning the energy economical
processor that determine the potency of the processor.
Multiplier has important role in DSP, DIP, microprocessor, and microcomputer
application. Among all the arithmetic operation that exist, a processor consumes
most of the time and hardware resources for carrying out multiplication when
compared to other operations like addition and subtraction.

While comparing various multipliers, it has been observed that the

selecting an appropriate multiplier for any application is always a tradeoff
between speed, power and the area.
Array multiplier has the largest delay and low power consumption and have
large area, while booth encoded wallace tree multiplier has least delay and it
also have large area. In above multipliers, one of the limitations is no of partial
products. The booth algorithm for multiplication overcomes the limitation and
hence, the performance is improved. In this review, the booth algorithm and its
variant which outperform the several multipliers will be discussed.
The detail comparison of multipliers and their performance matrix in
term of delay, area and power consumption will be provided, so that the
most appropriate multiplier can be chosen for application.

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3. Design and Synthesis Of Signed and Un-Signed Approximate Multiplier
Using Rounding Based Approximation ( June 2018)
1.INTRODUCTION
Energy minimization is one among the most style necessities in any electronic
systems, particularly the moveable ones like mobile phones, tablets, and totally
different gadgets [1].
It’s extremely desired to realize this minimization with least performance
(speed) penalty [1]. Digital signal processing (DSP) blocks are key elements of
those moveable devices for realizing varied multimedia system applications.
The procedure core of those blocks is that the arithmetic logic unit wherever
multiplications have the best share among all arithmetic operations performed
in these DSP systems [2]. Therefore, rising the speed and power/energy-
efficiency characteristics of multipliers plays a key role in rising the efficiency
of processors.

METHODOLY implemented
Outline of results
Future scope

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2. LITERATURE SURVEY

Srn Paper Author Conclusion

o name
1 Design and S. Lad and This paper presents highly efficient Vedic
Comparison V. S. multiplier unit using various Sutras of Vedic
of Multiplier Bendre Mathematics. Design, synthesis and simulation
using Vedic of 16-bit Vedic multiplier unit is done
Sutras using Verilog

2 Modified M. B. When it comes to the terms of time delay then

High Speed Murugesh, the proposed system is more efficient than
32-bit Vedic S. Nagaraj, exisitng methods.
MultiplierDes J. Jayasree
ign and and G. V.
Implementati K. Reddy
n
3 Vedic Jagadguru The author had compiled  16 vedic sutras and
Mathematics Swami Sri 13 sub sutras  from various vedic texts such as
Bharati atharva -veda
Krisna
Tirthaji
Maharaj
4 High speed D. K. Kahar The design is based On Urdhva Tiryagbhyam
vedic and H. Sutra is highly efficient algorithm for
multiplier Mehta applicable to all multiplication operation.
used vedic
mathematics
5 Low power Neeraj Using this multiplier module a Vedic MAC
32x32 bit Kumar unit was constructed and both these modules
multiplier Mishra, were integrated into an arithmetic unit along
architecture Subodh with the basic adder subtracter.
based on Wairya
Vedic
Mathematics
using Virtex 7

3
 low power
design
6 Low power A. Kumar
ALU design and A.
by ancient Raman
mathematics
7 performance Nitin The Multiply Accumulate Unit is designed
analysis of Krishna V using four different multipliers in Verilog
MAC unit HDL, simulated and synthesized in Xilinx
using Booth , Vivado. These designs are compared in terms
Array and of delay incurred, power consumption and
vedic FPGA ultilisation parameters
multiplier
8 Design and S.P.Pohokar
Implementati , R.S.Sisal,
on of 16 x 16 K.M.Gaikw
Multiplier ad,
using Vedic M.M.Patil,
Mathematics Rushikesh
Borse
9 Design and A. Jais and A very effective method, i.e. Urdhva-
///// implementatio P. Tiryakbhyam Sutra based on Vedic
///// n of 64 bit Palsodkar mathematics is used in this paper for
///// multiplier the multiplication of two 64 bit numbers. This
///// using vedic method allows us to design a multiplier of any
///// algorithm bit number
del
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13
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3. PROBLEM STATEMENT

The performance of the any processor will depend upon its power and
delay. The power and delay should be less in order to get a effective processor.
In processors the most used architecture is multiplier.
3.2016 ijret vedic app A multiplier is a very important element in any
processor design and a processor spends considerable amount of time in
performing multiplication and generally the most area consuming. Hence,
optimizing the speed and area of the multiplier is a major design issue.

We will be designing highly efficient Vedic multiplier based arithmetic unit to

tackle this problems .

4. PROJECT OBJECTIVE

 Our objective is to design and compare with conventional multipliers

with Vedic multiplier.

 To design and implement Vedic arithmetic unit based on Urdhva

Tiryakbham algorithm using verilog language in Xilinx environment and
on Artix 7 FPGA board.

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5. METHODOLOGY

Block Diagram
Technical Overview

Fig. Workflow diagram [1]

3) Vedic multiplier:

Authors [5] describes Vedic mathematics - a gift given to this world by the
ancient sages of India. A system which is far simpler and more enjoyable than
modern mathematics. The word “Vedic” is derived from the word “Veda”
which means the storehouse of all knowledge.

Vedic mathematics is mainly based on 16 Sutras (or aphorisms) dealing with

various branches of mathematics like arithmetic, algebra, geometry etc. These
methods and ideas can be directly applied to trigonometry, plain and spherical
geometry, conics, calculus (both differential and integral), and applied
mathematics of various kinds.

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The performance of the any processor will depend upon its power and delay [9].
The power and delay should be less in order to get a effective processor. In
processors the most commonly used architecture is multiplier.

The architecture for multipliers are mainly Array and Vedic multipliers. In
Vedic multipliers there are two types of techniques for multiplications based on
Urdhva Triyagbhyam and Nikhilam sutras.

 Vedic mathematics respects with various parts of mathematics which are

the most dependent on 16 Sutras which are given as follows [11] :

1) (Anurupye) Shunyamanyat
2) Chalana-Kalanabyham
3) Ekadhikina Purvena
4) Ekanyunena Purvena
5) Gunakasamuchyah
6) Gunitasamuchyah
7) Nikhilam Navatashcaramam
8) Paraavartya Yojayet.
9) Puranapuranabyham
10) Sankalana- vyavakalanabhyam
11) Shesanyankena Charamena
12) Shunyam Saamyasamuccaye
13) Sopaantyadvayamantyam
14) Urdhva-tiryagbhyam
15) Vyashtisamanstih
16) Yaavadunam

2. VEDIC MATHEMATICS ( irjet c vedic app 2016

Vedic mathematics is an ancient fast calculation mathematics technique which
provides the unique technique of mental calculation with the help of simple
rules and principles. Veda rediscovered by the holiness Jagad Guru Shree Bharti
Krishna Tirtha JiMaharaj (1884-1960) in between 1911-1918. According to
Swami-Ji all Vedic mathematics is based on 16-Sutra (Algorithm) and 16- up-
sutra (Subalgorithm) after broadly research in Atharva Veda [4]. It computes all
the basic as well as complex mathematical operation easily and quickly also
provides a powerful technique. It is more consistent than modern mathematics
and provides an expeditious solution..

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Fig : Vedic 2 bit U-T based multiplier[3]

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Fig : Vedic 4 bit multiplier

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 Fig : Vedic 8 bit

1) Array multiplier :

Array multiplier functions based on the add-shift algorithm. It multiplies

two binary numbers by using an array of half and full adders. Add and shift
operations are simultaneously executed while checking the bits of the multiplier
followed by the addition of partial products. This multiplier has a systematic
and regular structure. However, when compared with other multipliers, it
consumes larger power and suffers from long delays.[7]

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2) Booth multiplier:
Booth multiplier follows Booth’s multiplication algorithm invented by Andrew
Donald Booth in 1950. It multiplies two signed binary numbers in two’s
complement notation while preserving the sign of the result. It outperforms
earlier methods of multiplication by reducing the number of iteration steps. It
skims the multiplier operand and skips chains of the algorithm thus reducing the
number of additions required to produce the result. [7]

Fig : Booths algorithm

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WORK DONE

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6. RESOURCES REQUIRED

 Xilinx ISE 14.7 Software.

The Xilinx ISE is primarily used for circuit synthesis and design.

 Verilog HDL
 Verilog is a HARDWARE DESCRIPTION LANGUAGE (HDL).
It is a language used for describing a digital system like a network switch
or a microprocessor or a memory or a flip−flop. It means, by using a
HDL we can describe any digital hardware at any level.

 Modelsim software
ISIM or the ModelSim logic simulator is used for system-level testing.

 FPGA (Artix 7 Nexys 4)

Overview
The Nexys 4 board is a complete, ready-to-use digital circuit development
platform based on the latest Artix-7™ Field Programmable Gate Array (FPGA)
from Xilinx. With its large, high-capacity FPGA (Xilinx part number
XC7A100T-1CSG324C), generous external memories, and collection of USB,
Ethernet, and other ports, the Nexys 4 can host designs ranging from
introductory combinational circuits to powerful embedded processors. Several
built-in peripherals, including an accelerometer, temperature sensor, MEMs
digital microphone, a speaker amplifier, and a lot of I/O devices allow the
Nexys 4 to be used for a wide range of designs without needing any other
components.
The Artix-7 FPGA is optimized for high performance logic, and offers more
capacity, higher performance, and more resources than earlier designs. Artix-7
100T features include:
• 15,850 logic slices, each with four 6-input LUTs and
8 flip-flops
• 4,860 Kbits of fast block RAM
• Six clock management tiles, each with phase-locked
loop (PLL)
• 240 DSP slices
• Internal clock speeds exceeding 450MHz
• On-chip analog-to-digital converter (XADC)

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 Fig: Nexys 4 board features [N 4 ref man.

CalloutComponent Description CalloutComponent Description

1 Power select jumper and battery

13 FPGA
header
configuration reset button

2 Shared UART/ JTAG USB port14 CPU reset button (for soft cores)

3 External configuration jumper

15 (SD
Analog
/ USB)signal Pmod port (XADC)

4 Pmod port(s) 16 Programming mode jumper

5 Microphone 17 Audio connector

6 Power supply test point(s) 18 VGA connector

7 LEDs (16) 19 FPGA programming done LED

8 Slide switches 20 Ethernet connector

9 Eight digit 7-seg display 21 USB host connector

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 10 JTAG port for (optional) external
22 PIC24
cable programming port (factory use)

11 Five pushbuttons 23 Power switch

12 Temperature sensor 24 Power jack

RESULTS :

Vedic Array Booth

No of LUTs 114 97
Delay(ns) 7.159 12.5
Power (W)
IOBs 32 32

Table : Comparison table for 8 bit

7. PLAN OF EXECUTION

Month Expected Work

November-January •   Study of  Conventional multiplier (Array and
Booth)
• Study of  Vedic multiplier
February-March • Study of Verilog Programming language 
• Design and Implementing   2 bit,4 bit,8 bit
multiplier.
April-May •   Design and  Implementation of  16 bit,32
bit multiplier .
• To implement on FPGA hardware 
June– July • Target for Conference Publication  and
scopus /SCI journal.

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 •   Obtaining,  improving results

Table 1: Expected timeline of the project

REFERENCES
[1] A. Bisoyi, M. Baral and M. K. Senapati, "Comparison of a 32-bit Vedic
multiplier with a conventional binary multiplier," ICACCCT IEEE 2014.

[2] G. C. Ram, D. S. Rani, R. Balasaikesava and K. B. Sindhuri, "VLSI

architecture for delay efficient 32-bit multiplier using vedic mathematic sutras,"
2016 International Conference on Recent Trends in Electronics, Information &
Communication Technology , IEEE 2016, pp. 1873-1877.

[3] D. K. Kahar and H. Mehta, "High speed vedic multiplier used vedic
mathematics," 2017 International Conference on Intelligent Computing and
Control Systems , IEEE 2017, pp. 356-359.

[4] Jagadguru Swami Sri Bharati Krisna Tirthaji Maharaja, Vedic

Mathematics: Sixteen Simple Mathematical Formulae from the Veda, Delhi
(1965).

[5] S. Lad and V. S. Bendre, "Design and Comparison of Multiplier using Vedic
Sutras," 2019 5th International Conference On Computing, Communication,
Control And Automation (ICCUBEA), IEEE 2019, pp. 1-5.

[6] Neeraj Kumar Mishra, Subodh Wairya, “Low power 32x32 bit multiplier
architecture based on Vedic Mathematics using Virtex 7 low power design” in
IJRREST Vol. 2, Issue-2, June 2013.

[7] A. Kumar and A. Raman, "Low power ALU design by ancient

mathematics," (ICCAE), 2010, pp. 862-865.

[8] Nitin Krishna V”performance analysis of MAC unit using Booth , Array
and vedic multiplier” IJRET-2020.

[9] S.P.Pohokar, R.S.Sisal, K.M.Gaikwad, M.M.Patil, Rushikesh Borse.

"Design and Implementation of 16 x 16 Multiplier using Vedic Mathematics"
International Conference on Industrial Instrumentation and Control (ICIC)
College of Engineering Pune, India. May 28-30, 2015.

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[10] M. B. Murugesh, S. Nagaraj, J. Jayasree and G. V. K. Reddy, "Modified
High Speed 32-bit Vedic Multiplier Design and Implementation," 2020
International Conference on Electronics and Sustainable Communication
Systems (ICESC), pp. 929-932, IEEE 2020.

[11] Ch. Harish Kumar - Implementation and Analysis of Power, Area and
Delay of Array,Urdhva, Nikhilam Vedic Multipliers - published at:
"International Journal of Scand Research Publications (IJSRP), Volume 3, Issue
1, January 2013 Edition".

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