Introduction to Microprocessors

Microcontrollers
 Microcontroller vs General-purpose Microprocessor

General purpose microprocessors such as Intel’s x 86 family (8086, 80286, 80386,

80486 and Pentium) or Motorola’s 680x0 family (68000, 68010, 68020, 68030, 68040,
etc.). – These microprocessors contain no RAM, no ROM, and no I/O ports on the chip
itself. A system designer using a general purpose microprocessor must add RAM, ROM,
I/O ports, and timers externally to make them functional.
these systems bulkier, more expensive , and advantage of versatility

A microcontroller has a CPU (a microprocessor) in addition to a fixed amount of RAM ,

ROM, and I/O ports a timer all on a single chip. Therefore,, the designer cannot add any
external memory, I/O ports and timer to it. The fixed amount of on-chip ROM, RAM
and number of I/O ports in microcontroller makes them ideal for may applications in
which cost and space are critical.
CPU
Data bus
General-
purpose Serial
Micropr RAM ROM I/O Timer COM
ocessor ports port

Address bus

General Purpose Microprocessor system

CPU RAM ROM

I/O Timer Serial

COM
Port

Microcontroller
 The 8051 Family
In 1981, Intel Corporation introduced an 8-bit microcontroller called the 8051

128 bytes of RAM

4K bytes of on-chip
ROM

Two timers

One serial port

Four ports (each 8-

bits wide)
Total 32 I/O pins
Comparison of 8051 Family Members
 Various 8051 microcontrollers

Versions of 8051/52 Microcontroller from Dallas Semiconductor (Maxim)

Part number ROM RAM I/O pins Timers Interrupts Vcc

DS89C420 16K(flash) 256 32 3 6 5V
DS89C440 32K(flash) 256 32 3 6 5V
DS89C450 64K(flash) 256 32 3 6 5V

Versions of 8051 Microcontroller Atmel

Part number ROM RAM I/O pins Timers Interrupts Vcc

AT89C51 4K(flash) 128 32 2 6 5V
AT89C2051 2K(flash) 128 15 2 6 3V
AT89LV52 8K(flash) 128 32 3 8 3V
 Intel MCS-51 family

Port 1 Port 0

Port 3

Port 2
 Intel MCS-51 family

Address/data b

Serial port

interrupts

Timer inputs

Read/Write Address bus

 Inside the 8051 – Registers
The vast majority of 8051 registers are 8-bit registers. With an 8-bit data type,
any data larger than 8 bits must be broken into 8-bit chunks before it is
processed.

The most widely used registers of the 8051 are A (accumulator), B, R0, R1, R2,
R3, R4, R5, R6, R7 and DPTR (data pointer) and PC (program counter). All of the
above registers are 8-bits except DPTR and program counter.

A
B
R0 DPTR DPH DPL
R1
R2 PC PC (program counter)

R3
R4
The point to remember is that no member of the 8051
family can access more than 64K bytes of opcode since the
R5
program counter in the 8051 is a 16-bit register (0000 to
R6
FFFF address range).
R7
 Assembling and Running an 8051 Program
Editor Ex. MS-DOS EDIT, Notepad
Program

myfile.asm
The assembler converts the instructions
Assembler into machine code. It will produce an
The lst file lists all the Program object file and a list file
opcodes and addresses
as well as errors that the myfile.lst
assembler detected. This myfile.obj Other obj files
file can be accessed by
Linker Assemblers requires a third step called
an editor such as DOS
EDIT Program linking. The link program takes one or
more object files and produces an
absolute object file with the extension
myfile.abs “abs”.

OH Next, the “abs” file is fed into a

Program program called “OH” (object to hex
converter), which creates a file with
extension “hex” that is ready to burn
myfile.hex into ROM.
Program Counter (PC) in the 8051

The program counter in the 8051 is 16 bits wide. This means that the 8051 can access
program addresses 0000 to FFFF, a total of 64K bytes of code. However, not all
members of the 8051 have the entire 64K bytes of on chip ROM installed.

Where the 8051 wakes up when it is powered up?

The microcontroller wakes up at memory address 0000 when it is powered up. By

powering up mean applying Vcc to the RESET pin. When the 8051 is powered up, the
PC has the value of 0000 in it. That it expects the first opcode to be stored at ROM
address 0000H. For this reason in the 8051 system, the first opcode must be burned
into memory location 0000H of program ROM.
Placing Code in program ROM
ROM Address Machine Language Assembly Language

1 0000 ORG 0H ; start at location 0

2 0000 7D25 MOV R5, #25H ;load 25H into R5 0000
3 0002 7F34 MOV R7, #34H ;load 34H into R7
4 0004 7400 MOV A, #0 ;load 0 into A
5 0006 2D ADD A, R5 ;add contents of R5 to A
;now A=A+R5
6 0007 2F ADD A, R7 ;add contents of R7 to A
;now A=A+R7 0FFF
7 0008 2412 ADD A, #12H ;add to A value 12H
8051 On-Chip
; now A=A+12H ROM Address
8 000A 80FE HERE: SJMP HERE ;stay in this loop Range
9 000C END ;end of asm source file

Address code
0000 7D
0001 25 Note:
0002 7F MOV R6,#12 ; load 12 decimal (0CH)
0003 34 MOV R5,#0F9H; that a 0 is used between the #
0004 74 and F to indicate that F is a hex number and not
0005 00 a letter
0006 2D
MOV R5,#F9H; will cause an error
0007 2F
0008 24
MOV A,#7F2H ; ILLEGAL: 7F2H>8bits (FFH)
0009 12 MOV R2,#456;ILLEGAL: 456>255 decimal (FFH)
000A 80
000B FE
 MCU 8051 IDE

128 Byte
Memory Space Main Registers Special Function Registers SFR
ORG 0H ;START AT LOCATION 0
MOV R5,#25H ;LOAD 25h INTO R5
MOV R7,#34H ;LOAD 34H INTO R7
MOV A,#0 ;LOAD 0 INTO A
ADD A,R5 ;ADD CONTENTS OF R5 TO A
ADD A,R7 ;ADD CONTENTS OF R7 TO A
ADD A,#12H ;A=A+12H
END ;END OF ASM SOURCE FILE
 RAM memory space allocation in the 8051

The 128 bytes of RAM inside the 8051 are assigned addresses 00 to 7FH. These 128
bytes are divided into three different groups as follows.

7F

Scratch Pad RAM

30
2F
Bit-Addressable RAM
20
1F
Register Bank 3
18
17
Register Bank 2
10
0F
Register Bank 1 (Stack)
08
07
Register Bank 0 PSW (program status word) register
00
By default RS1 = 0 and RS0 = 0
Register Bank 0
PSW (program status word) register
PSW (program status word) register
PSW (Program Status Word) Register
The PSW register is an 8-bit register. It is also referred as the flag register.
Although the PSW register is 8 bits wide, only 6 bits of it are used by the 8051. The
two unused bits are user-definable flags.

CY AC F0 RS1 RS0 OV - P

CY PSW.7 carry flag

AC PSW.6 Auxiliary carry flag
F0 PSW.5 Available to the user for general purpose
RS1 PSW.4 Register Bank selector bit 1
RS0 PSW.3 Register Bank selector bit 0
OV PSW.2 Overflow flag
- PSW.1 User-definable bit
P PSW.0 parity flag. Set/cleared by hardware each instruction cycle to
indicate an odd/even number of 1 bits in the accumulator
 PSW Bank Selection
RS1 (PSW.4) RS0 (PSW.3) Register Bank Address
0 0 0 00H – 07H
0 1 1 08H – 0FH
1 0 2 10H – 17H
1 1 3 18H – 1FH

ORG 0H
SETB PSW.4 ;MAKE RS1=1 FOR SELECTING BANK3
SETB PSW.3 ;MAKE RS0=1 FOR SELECTING BANK3
MOV R0,#05H ;LOAD R0 WITH VALUE 05H
MOV R1,#35H ;LOAD R1 WITH VALUE 05H
MOV R2,#21H ;LOAD R2 WITH VALUE 05H
MOV R3,#85H ;LOAD R3 WITH VALUE 05H
END
 1 2

3 4

5 6
PSW Continue …
1. Use assembler directives to place constants 0FCH, 05H,76H,28D and character string
“SAM” in consecutive program memory locations beginning from location 0005H.

ORG 0005H
DB 0FCH,05H,76H,28
DB 'S','A','M'

DB (define byte) used to define the

8-bit data. When DB is used to
define data, the numbers can be
decimal, binary, hex or ASCII
formats.
PSW Continue …
2. Add the numbers 56H and 95H, and show how CY, AC, and P flags are affected.

ORG 0H 56H 01010110

MOV A,#56H + 95H 10010101
ADD A,#95H EBH 11101011

In the calculation, CY =0, since there is no carry beyond D7.

AC=0, since there is no carry from D3 to D4.
P=0, since the accumulator has an even number of bits
PSW Continue …
3. Show the status of the CY,AC, and P flags after addition of 9CH and 64H in the
following instructions.

MOV A, #9CH 9CH 10011100

ADD A, #64H + 64H 01100100
100H 00000000

CY = 1 since there is a carry beyond the D7 bit.

AC = 1 since there is a carry from the D3 to the D4 bit.
P = 0 since the accumulator has an even number of 1s(it has zero 1s)
PSW Continue …
4. Show the contents of the PSW register after the execution of the following instructions.

MOV A, #0BFH BFH 10111111

ADD A, #1BH + 1BH 00011011
DAH 11011010

PSW.7:CY = 0 since there is no carry beyond the D7 bit

PSW.6:AC = 1 since there is a carry from the D3 to D4 bit
PSW.5:F0, unused , hence 0
PSW.4:register bank selector bit RS1=0 since by default, Bank 0 is selected
PSW.3:register bank selector bit RS0=0 since by default, Bank 0 is selected
PSW.2:OV=0 since there is no carry from D6 to D7
PSW.1:not used, hence 0
PSW.0:P=1 since there is an odd number of 1’s in the accumulator

The content of the PSW is thus 01000001, i.e. 41H

 Looping in the 8051
Repeating a sequence of instructions a certain number of times is called a loop.

Instruction Action
JZ Jump if A=0
JNZ Jump if A≠0
DJNZ Decrement and jump if register ≠0

Problem1. Multiply 25 by 10 using the technique of repeated addition.

MOV A,#0 ;A=0, CLEAR ACC

MOV R2,#10 ;THE MULTIPLIER IS PLACED IN R2
AGAIN: ADD A,#25 ;ADD THE MULTIPLICAND TO THE ACC
DJNZ R2,AGAIN ;REPET UNTIL R2=0 (10 TIMES)
MOV R5,A ;SAVE A IN R5;R5=FAH
END
Problem2. Write a program to add the first ten natural numbers

MOV A,#0 ;A=0,CLEAR ACC

MOV R2,#10 ;LOAD COUNTER VALUE IN R2
MOV R0,#0 ;INITIALIZE R0 TO ZERO
AGAIN: INC R0 ;INCREMENT R0 TO HOLD THE NATURAL NUMBERS
ADD A,R0 ;ADD FIRST NUMBER TO ACC
DJNZ R2,AGAIN ;REPEAT UNTIL R2=0 (10 TIMES)
MOV 46H,A ;SAVE THE RESULT (37H)IN RAM LOCATION 46H
END
How stacks are accessed in the 8051

If the stack is a section of RAM, there must be a registers inside the CPU to
point to it. The register used to access the stack is called the SP (stack pointer)
register. The stack pointer in the 8051 is only 8 bits wide, which means that is
can take values of 00 to FFH.

When the 8051 powered up, the SP register contains value 07. This means that
RAM location 08 is the first location used for the stack by the 8051.

In the 8051 the stack pointer (SP) points to the last used location of the stack.
As we push data onto the stack, the stack pointer is incremented by one.
ORG 0
MOV R0,#25H
MOV R1,#12H
MOV R2,#0F3H
PUSH 2
PUSH 1
PUSH 0
POP 7
POP 6
POP 5
END
The Special
Function
Registers (SFRs)
Problem3. Write a program to toggle all the bits of port 1 by sending to it the value 55H and
AAH continuously. Put a time delay in between each issuing of data to port 1.

ORG 0100H
BACK: MOV A,#55H ;LOAD A WITH 55H (0100 0101)
MOV P1,A ;SEND 55H TO PORT1 (0102 0103)
LCALL DELAY1 ;TIME DELAY (0104 0105 0106)
MOV A,#0AAH ;LOAD A WITH AA IN HEX (0107 0108)
MOV P1,A ;SEND AAH TO PORT1 (0109 010A)
LCALL DELAY1 ;TIME DELAY (010B 010C 010D)
SJMP BACK ;KEEP DOING THIS INDEFINITELY (010E 010F) SHORT JUMP
; THIS IS THE DELAY SUBROUTINE
ORG 300H ;PUT TIME DELAY AT ADDRESS 300H
DELAY1: MOV R5,#05H ;R5=5 THE COUNTER1
DELAY2: MOV R6,#03H ;R6=3 THE COUNTER2
AGAIN: DJNZ R6,AGAIN ;STAY HERE UNTILL R6 BECOMES 0
DJNZ R5,DELAY2
RET ;RETURN TO CALLER (WHEN R5=0)
END
ORG 0100H
BACK: MOV A,#55H ;LOAD A WITH 55H (0100 0101)
MOV P1,A ;SEND 55H TO PORT1 (0102 0103)
LCALL DELAY1 ;TIME DELAY1 (0104 0105 0106)
MOV A,#0AAH ;LOAD A WITH AA IN HEX (0107 0108)
MOV P1,A ;SEND AAH TO PORT1 (0109 010A)
LCALL DELAY1 ;TIME DELAY1 (010B 010C 010D)
SJMP BACK ;KEEP DOING THIS INDEFINITELY (010E 010F) SHORT JUMP
; THIS IS THE TIME DELAY1 SUBROUTINE
ORG 300H ;PUT TIME DELAY1 AT ADDRESS 300H
DELAY1: MOV R5,#05H ;R5=5 THE COUNTER1 (0300 0301)
AGAIN1: DJNZ R5,AGAIN1 ;STAY HERE UNTILL R5 BECOMES 0 (0302 0303)
LCALL DELAY2 ;TIME DELAY2 (0304 0305 0306)
RET ;RETURN TO CALLER (WHEN R5=0) (0307)
; THIS IS THE TIME DELAY2 SUBROUTINE
ORG 400H ;PUT TIME DELAY1 AT ADDRESS 400H
DELAY2: MOV R6,#03H ;R6=3 THE COUNTER2 (0400 0401)
AGAIN2: DJNZ R6,AGAIN2 ;STAY HERE UNTILL R6 BECOMES 0 (0402 0403)
RET ;RETURN TO CALLER (WHEN R6=0) (0404)
END
Time Delay for Various 8051 chips

Machine Cycle for the 8051

The CPU takes a certain number of clock cycles to execute an instruction. Theses clock
cycles referred to as machine cycles. The length of the machine cycle depends on the
frequency of the crystal oscillator connected to the 8051 system. The crystal oscillator,
along with on-chip circuitry, provide the clock source for the 8051 CPU. Very often the
11.0592 MHz crystal oscillator is used to make the 8051 based system compatible with
the serial port of the IBM PC. In the original 8051, one machine cycle lasts 12 oscillator
periods. Therefore, to calculate the machine cycle for the 8051, we take 1/12 of the
crystal frequency, then takes its inverse.

The following shows crystal frequency for three different 8051 based systems. Find the
period of the machine cycle in each case.

(a) 11.0592 MHz

11.0592 MHz/12 = 921.6 kHz; machine cycle (MC) is 1/921.6 kHz = 1.085 µs

(b) 16 MHz (MC = 0.75 µs)

(c) 20 MHz (MC = 0.60 µs)

8051 instructions and their machine cycles
Instruction Machine cycles
MOV R3,#55 1
DEC R3 1
DJNZ R2,TARGET 2
SJMP 2
NOP 1
MUL AB 4

Problem 4. For an 8051 system of 11.0592 MHz, find the time delay for the following
subroutine:

machine cycles
The time delay inside the HERE loop is
DELAY: MOV R3,#250 1
[250(1+1+1+1+2)]x1.085 µs = 1627. 5 µs
HERE: NOP 1
NOP 1
Adding the two instructions outside the loop
NOP 1
we have
NOP 1
1627.5 µs + 3x1.085 µs = 1630.755 µs
DJNZ R3,HERE 2
RET 2
 I/O Port Programming
In the 8051 there are a total of four ports for I/O operations.

The four ports P0,P1,P2 and P3

each use 8 pins, making them 8
bit ports. All the ports upon
Port 0 RESET are configured as inputs,
Port 1 ready to be used as input ports.

When the first 0 is written to a

port, it becomes an output. To
reconfigure it as an input, a 1
must be sent to the port.

Port 3

Port 2
Port 0
Port 0 occupies a total of 8 pins(pin32-39). It can be used for input or output. To use the
pins of port 0 as both input and output ports, each pin must be connected externally to a
10Kohms pull-up resistor. This is due to the fact that P0 is an open drain, unlike P1,P2 and
P3. Open drain is a term used for MOS chips in the same way that open collector is used for
TTL chips.

ORG 0H
MOV A,#0FFH
MOV P0,A
MOV A,#00H
MOV P1,A
BACK: MOV A,P0
MOV P1,A
SJMP BACK
I/O ports and bit-addressability

Sometimes we need to access only 1 or 2 bits of the port instead of the entire 8
bits. A powerful feature of 8051 I/O ports is their capability to access
individual bits of the port without altering the rest of the bits in that port.

SETB P1.2 ; CHANGE ONLY P1.2 =HIGH

CLR P1.2 ; CHANGE ONLY P1.2 = LOW

Write following programs.
(a) Create a square wave of 50% duty cycle on bit 0 of port 1.
(b) Create a square wave of 66% duty cycle on bit 3 of port 1.

Solution
(a) The 50% duty cycle means that the “on” and “off” states (or the high and low
portion of the pulse) have the same length. Therefore, we toggle P1.0 with a time
delay in between each state.
ORG 0
HERE: SETB P1.0 ;SET TO HIGH BIT 0 OF PORT 1
LCALL DELAY ;CALL THE DELAY SUBROUTINE
CLR P1.0 ;P1.0=0
LCALL DELAY
SJMP HERE ;KEEP DOING IT
ORG 300H
DELAY: MOV R5,#5H ;R5=5 THE COUNTER (0300H 0301H)
AGAIN: DJNZ R5,AGAIN ;STAY HERE UNTILL R5 BECOMES 0 (0302H 0303H)
RET ;RETURN TO CALLER (WHEN R5=0) (0304H 0305H)
END
(b) The 66% duty cycle means the “on” state is twice the “off” state.
ORG 0
HERE: SETB P1.3 ;SET TO HIGH BIT 0 OF PORT 1
LCALL DELAY ;CALL THE DELAY SUBROUTINE
LCALL DELAY ;CALL THE DELAY SUBROUTINE
CLR P1.3 ;P1.0=0
LCALL DELAY
SJMP HERE ;KEEP DOING IT
ORG 300H
DELAY: MOV R5,#5H ;R5=5 THE COUNTER (0300H 0301H)
AGAIN: DJNZ R5,AGAIN ;STAY HERE UNTILL R5 BECOMES 0 (0302H 0303H)
RET ;RETURN TO CALLER (WHEN R5=0) (0304H 0305H)
END
Write a program to perform the following.
(a) Keep monitoring pin P0.1 until it becomes high
(b) When P0.1 becomes high, read in the data from P1
(c) Send a low to high pulse on P0.2 to indicate that the data has been read

Solution

SETB P0.1 ;MAKE P0.1 AN INPUT

MOV P1,#0FFH ;MAKE P1 AN INPUT PORT
AGAIN: JNB P0.1,AGAIN ;CHECK IF P0.1 IS HIGH, IF NOT, KEEP CHECKING
MOV A,P1 ;IF P0.1 IS FOUND HIGH, TAKE IN DATA FROM P1
CLR P0.2 ;CLEAR P0.2
SETB P0.2 ;SET P0.2
P0.1
 Microcontrollers with 8051 Core

Philips P89C51RA2/RB2/RC2/RD2xx
80C51 8-bit Flash microcontroller family
8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM
In-System Programming capability (ISP)
Parallel programming with 87C51 compatible hardware
interface to programmer
Four interrupt priority levels
Programmable Counter Array (PCA) – PWM and Capture/compare
Power control modes: stopped clock, idle, power down
 In-System Programming (ISP)
also called In-Circuit Serial Programming (ICSP)

In-System Programming allows programming and

reprogramming of a microcontroller positioned inside the
end system.

Typically, chips with ISP have internal circuitry to generate

any necessary programming voltage internally, and to
communicate with the programmer via a serial protocol.

A variant of the JTAG protocol or a proprietary protocol is

used for programming.

A typical interface used for this is SPI (Serial Peripheral

Interface Bus)
 Serial Peripheral Interface Bus

A synchronous serial data link standard that operates in full

duplex mode.

In-System Programming eliminates the physical removal of chips from the system. This
will save time, and money, both during development in the lab, and when updating the
software or parameters in the field.
 Microcontrollers with 8051 Core

Atmel AT89S51

4K Bytes of In-System Programmable (ISP) Flash Memory

Six Interrupt Sources
Watchdog Timer
 Microcontrollers with 8051 Core

Philips P8xC591
Single-chip 8-bit microcontroller with CAN controller

Three 16-bit timers/counters

10-bit ADC with 6 multiplexed analog inputs with fast 8-bit ADC
Two 8-bit resolution, Pulse Width Modulated outputs
I2C-bus serial I/O port
On-chip Watchdog Timer
 Watchdog Timers

Sometimes microcontrollers are used in places where humans are

not available to press reset in cases of software faults. If software
hangs, such systems are permanently disabled.

A watchdog timer is a piece of hardware that can be used to

automatically detect software anomalies and reset the processor
when necessary.
 Watchdog Timers

The software running in the microcontroller must restart the

watchdog timer at a regular rate.

If it fails to reset within a specified time interval, the watchdog

timer resets the microcontroller.
 Power Modes

Power consumption is one of the big issues on mobile or battery powered devices.

Some microcontrollers allow you to reduce the clock frequency, for example by
switching to an internal clock, to reduce power consumption when only little work
has to be done.

Typical power modes available are:

Execution mode (running)

Programming mode

Sleep or power down mode (low power consumption)

 Instruction Pipelines
c
Instructions can fill several clock cycles. Instructions can
further be divided into smaller steps like:

Fetch instruction

Decode instruction

Read data

Process data

Write data

Pipelining allows these stages to overlap and to perform with

parallelism, hence better performance.
 Instruction Pipelines
c

The pipeline will only work at full efficiency if it can fetch instructions
from sequential locations in memory.

Operations that change the program counter, jumps to other memory

locations, will lead to pipeline breaks, requiring the content of the
pipeline buffer to be discarded.

This will lead to delays in execution and degrade the performance.

 Reduced Instruction Set Computing
(RISC)

Simplified instructions can provide higher performance if

this simplicity enables much faster execution of each
instruction.
 Complex Instruction Set Computing
(CISC)

Powerful and easy-to-use instructions

Instructions that would do as much work as feasible

Provide every possible addressing mode

Few registers because

more registers mean more complex instructions
and more time spent in saving in stack
 RISC Philosophy

Some addressing modes are rarely used

Some operations are faster when implemented as a

series of simple operations
Therefore, one can make a CPU faster, having a small
number of well optimized simple instructions
 Atmel AVR family

The AVR is a modified Harvard architecture 8-bit RISC

single chip microcontroller

One of the first microcontroller families to use on-chip

flash memory for program storage
 Atmel AVR family
ATtinyXXXX – less instructions and smaller packages
1–8 kB program memory
8–28-pin package
Limited peripheral set
Limited instruction set – the instruction sets are limited. For
example , some of them do not have the multiply instruction.

ATmegaXXXX – more than 120 instructions and lots of

different peripheral capabilities
4–256 kB program memory
28–100-pin package
Extended instruction set – They have rich instruction sets
Extensive peripheral set
 Some members of the Atmega and Attiny Families

Part Num. Code Data Data I/O pins ADC Timers Pin numbers &
ROM RAM EEPROM Package

ATmega8 8K 1K 0.5K 23 8 3 TQFP32, PDIP28

ATmega16 16K 1K 0.5K 32 8 3 TQFP44, PDIP40

ATmega32 32K 2K 1K 32 8 3 TQFP44, PDIP40

ATmega64 64K 4K 2K 54 8 4 TQFP64, MLF64

ATmega1280 128K 8K 4K 86 16 6 TQFP100,CBGA

ATtint13 1K 64 64 6 4 1 SOIC8, PDIP8

ATtiny25 2K 128 128 6 4 2 SOIC8, PDIP8

Attiny44 4K 256 256 12 8 2 SOIC14, PDIP14

Attiny84 8K 512 12 8 2 2 SOIC14, PDIP14

Atmega32
 The general purpose registers in the AVR

The vast majority of AVR registers are 8-bit registers. In AVR there are 32 general
purpose registers (GPRs). They are R0-R31 and are located in lowest location of memory
address 00-1F.

AVR microcontrollers are Harvard architecture. This means, that in this architecture are
separate memory types (program memory and data memory) connected with distinct
buses. Such memory architecture allows processor to access program memory and data
memory at the same time. This increases performance of MCU comparing to CISC
architecture, where CPU uses same bus for accessing program memory and data
memory.
Each memory type has its own address space:
For instance few Atmega series memory map examples:

Type Flash RAM EEPROM

F_END Size, kB RAMEND Size, kB E_END Size, kB

Atmega8 $0FFF 8 $045F 1 $1FF 0.5

Atmega32 $3FFF 32 $085F 2 $3FF 1

Atmega64 $7FFF 64 $10FF 4 $7FF 2

Atmega128 $FFFF 128 $10FF 4 $FFF 4

 LDI instructions

LDI Rd, K ; load Rd (destination) with Immediate value K

; d must be between 16 and 31

Ex:

LDI R20, 0x25 ; load R20 with 0x25 (R20 = 0x25 -- 25 in hex)

LDI R5, 0x99 ; invalid instruction

; we cannot load values into registers R0 –R15 using LDI instructions

Note : If we want to present a number in hex, we put a dollar sign ($) or a 0x in front of it.
If we put nothing in front of a number, it is in decimal.
ADD instruction

ADD Rd, Rr ; ADD Rr to Rd and store the result in Rd

Ex :
LDI R16, 0x25 ; load 0x25 into R16
LDI R17, 0x34 ; load 0x34 into R17
ADD R16,R17 ; add value R17 to R16 (R16 = R16 + R17)

LDS instruction (Load direct from data Space)

LDS Rd, K ; load Rd with the contents of location K (0<= d <=31)

; K is an address between $0000 to $FFFF

Ex:

LDS R0, 0x300 ; R0 = the content of location 0x300

LDS R1, 0x302 ; R1 = the content of location 0x302
ADD R1, R0 ; add R0 to R1
 STS instruction (Store direct to data space)

STS K, Rr ; store register into location K

; K is an address between $0000 to $FFFF

Registers of the Atmega32 and their Data memory Address Locations

Memory Address Name
$31 DDRD LDI R16, 0x55 ; R16=55 in hex
$32 PORTD STS 0x38,R16 ;copy R16 to PortB
$34 DDRC STS 0x35,R16 ;copy R16 to PortC
$35 PORTC STS 0x32,R16 ;copy R16 to PortD
$37 DDRB
$38 PORTB The above program first loads the R16
$3A DDRA register with value 0x55, then moves this
$3B PORTA value around to I/O registers of ports B, C,
and D.
The Programming Interface

For In-System Programming, the programmer is connected to the target using as few wires
as possible. To program any AVR microcontroller in any target system, a simple Six-wire
interface is used to connect the programmer to the target PCB. Below shows the
connections needed.

To assure proper communication on the three SPI lines, it is necessary to connect ground
on the programmer to ground on the target (GND).

The Serial Peripheral Interface (SPI) consists of three wires: Serial ClocK (SCK), Master In –
Slave Out (MISO) and Master Out – Slave In (MOSI). When programming the AVR, the In-
System Programmer always operate as the Master, and the target system always operate as
the Slave.
The In-System Programmer (Master) provides the clock for the communication on the
SCK Line. Each pulse on the SCK Line transfers one bit from the Programmer (Master) to
the Target (Slave) on the Master Out – Slave In (MOSI) line. Simultaneously, each pulse
on the SCK Line transfers one bit from the target (Slave) to the Programmer (Master) on
the Master In – Slave Out (MISO) line.

Recommended In-System Programming Interface Connector Layout (Top View)

 USBASP AVR Programmer

USBasp is a USB in-circuit programmer for

Atmel AVR controllers. It simply consists of an
ATMega88 or an ATMega8 and a couple of
passive components. The programmer uses a
firmware-only USB driver, no special USB
controller is needed.

Some of the features include:

Allows you to read or write the microcontroller EEPROM, firmware, fuse bits and lock bits
Support for Windows, Mac OS X and Linux (will work on Windows 8.1)
5 KB/sec maximum write speed
Software controlled SCK option to support targets with low clock speed (< 1.5MHz)
10 pin ISP interface (conforms to standard ISP 10-pin pinout)
In order for a master device to program a slave device, they need have communication amongst each other.
The master device needs to be able to write data to the slave device's flash memory and be able to receive
data from the slave data. This is done through the MOSI and MISO pins. The MOSI pin stands for Master Out
Slave In. This is the pin by which the master device outputs, or writes, data to the target AVR which is being
programmed. MISO stands for Master In Slave Out. This is the pin by which the slave device (AVR being
programmed) can send information to the master device. Both these communication pathways are essential to
program a device. So the MOSI and MISO pins establish communication amongst the master device and the
slave device it is to program.

The SCK pin is the clock. It is essential because in order for the master and slave device to communicate, they
need to have a time signal to communicate data in synchrony. The common clock signal shared between the
master and slave device allow for efficient communication.

The RST pin is an essential connection because it must be put to an active low connection in order for
programming to occur between the master and slave device. It is normally held high, but for programming to
occur, it must be put low. It is an active low pin. When the RST pin is put low, the master slave can
communicate on the SCK, MISO, and MOSI lines.

The remaining 2 connections, VCC and GND, are the simplest; they are for power. The AVR chip being
programmed and the master device doing the programming both need to power in order to operate.
End of Part 1
 Atmega 32 C programming using Atmel Studio

Step 01.
install USBASP driver
http://www.protostack.com/accessories/usbasp-avr-programmer
Download the driver and save it
Plug the USBASP
Mycomputer -> Manage -> update the driver software browse the above folder

Step 02.
Install AVRDUDE
The programmer come with WINAVR . Install WINAVR

Step 03.
Test the connections and response
Step 4
Command Window -> avrdude
Connect the atmega32 with usbasp
Then command and arguments in command window

avrdude –c usbasp –p m32

Then it should response

Step 05.
Install Atmel Studio

Step 06.
Settings of Atmel Studio
Tools -> external tools

-c usbasp -p m32 -U flash:w:$(TargetDir)$(TargetName).hex:i