1

Chapter III. MOS transistor

III.1. MOS transistor…..................……………..slides 2-62
III.1.1: Si/SiO2 interface and MOS capacitor
III.1.2: from MOS capacitor to MOS transistor
III.1.3: MOSFET non idealities

III.2. TCAD - Analysis of n-MOS transistor ....slides 61-72

III.3. CMOS Technologies …. slides 73-79

III.3.1: Active and passive components
 2
III.1. MOS transistor
a) Silicon
Junction Transistors Integrated circuits
diodes
MOSFET CMOS technologies
BiCMOS technologies
JFET
BJT Bipolar technologies
BJT/CMOS power electronics
b) GaAs et al.(III-V and II-VI semic.) Optoelectronics
Optical communications
M/S Diodes MESFET M.M.I.C.
HBT, HFET Monolithic Microwave Integrated Circuits
 3
MOSFET = Metal Oxide Semiconductor Field Effect Transistor
poly-Si Gate
metal (Source) metal (Drain)
0
n+ n+ Field oxide
XJ

p (substrate) Cross-section
Gate oxide
Gate

Drain
Si Layout
chip
Source
 4
Enhancement (normally off) MOS transistors
Circuit symbol
• n-channel MOSFET
S G D D

n+ n+ G B
pSi (substrate= Bulk)
S
• p-channel MOSFET
S G D D

p+ p+ G B
nSi (substrate=Bulk)

• 3 main electrodes: S= source; G= gate; D= drain S

+ Bulk electrode (Substrate)
 5
n-channel MOSFET (n-MOSFET)
S G D

n+ n+
pSi (substrate= Bulk)

B
• The gate electrode controls the electrical conductivity at the
Si/SiO2 interface (Field Effect)

• MOS transistors can be obtained only from Si substrates (and

maybe SiC ... )

• The peculiar properties of Si/SiO2 interface are exploited

 6
III.1.1: Si/SiO2 interface and MOS capacitor
• “naked” silicon surface E
Inner lattice
silicon

C.B.
External surface

Si4+ Si4+ Si4+

Surface
Si4+ Si4+ Si4+
states

Si4+ Si4+ Si4+ V.B.

Si4+ Si4+ Si4+

In this condition the electrical
conductivity of the surface region
dangling bonds can not be controlled
 7

• thermally oxidized silicon surface E

silicon
external
Inner lattice
oxide
C.B.
Si4+ Si4+ Si4+
No
surface
Si4+ Si4+ Si4+ states
V.B.
Si4+ Si4+ Si4+

Residual density of surface

Si4+ Si4+ Si4+ states < 1010 /cm2 eV !

The oxide saturates the dangling bonds,

Si/SiO2 interface so that the surface conductivity can be
controlled by applying an electric field.
 8
Metal Oxide (Si) Semiconductor (MOS) structure
The surface charge in the semiconductor ( QS ) is controlled by
means of the gate voltage ( vG )
Metal (n+poly-Si gate)

Gate Gate oxide SiO2

vG
voltage Thickness = t ox
p-Si substrate Dielectric
constant = e ox

vG = Vox + Ψ s(vG )
Vox = electric potential across the oxide
Ψ s(vG ) = electric potential across the semiconductor
 9
• The surface charge in the semiconductor ( QS ) is controlled
by means of the gate voltage ( vG );
• No perturbation far from the interface (equilibrium) !!

tox
Gate vG
voltage pSi

Charge in the metal QM = – QS charge in the semiconductor

Qm Qs
vG = Vox + Ψ s(vG ) = + Ψ s (vG ) = - + Ψ s (vG )
Cox Cox
Qm: charge/cm2 in metal = -Qs: charge/cm2 in semic.
capacitance/cm2 of the oxide: Cox = eox / tox
 10
Ideal MOS capacitor

No current can flow:

dy dn Dn =
kT
µn
J n = -qµ n n + qDn =0 with
dx dx q
dy dn kT dn kT dn
qµ n n = qDn =q µn dy =
dx dx q dx q n
0
kT
n0
dn æ qy s ö
Integrating: ò dy = ns = n0 expç
ys q òn n è kT ø
÷
æ qy s ö
s

and similarly for holes: ps = p0 expç - ÷

è kT ø
Different charge carrier concentrations at the surface can be
obtained by varying the surface potential ...
Accumulation: vG < 0 Þ y s < 0
11

Hole accumulation at the M O pSi

Si/SiO2 interface QM <0
VG
Ψs 0
x
vG
Ψ(x)
pSi substrate QS >0 M O pSi
r (x)

ì æ qΨ s ö Qs
ïns = n0 expç kT ÷ < n0
ï è ø x
í Qm
ï p = p expæç - qΨ s ö÷ > p Charge neutrality
ï
î
s 0
è kT ø
0
|Qm | =Qs[ Ψ s(VG )]
Depletion: 0 < vG < VTn Þ 0 < y s < 2j F 12

Depletion of holes at the Ψ(x)

Si/SiO2 interface QM M O pSi
(positive)

VG
Ψs 0
vG ( )( ) ( ) ( )( )
x
M O pSi
pSi substrate r (x) depletion

Depletion: QS (negative NA–) Qm w

It can be shown that: x
2ε s Qb=-qNAw
w= Ψs
qN A Qs = Qb (Ψ s ) = - 2εs qN AΨ s
 13
Poisson equation for fully depleted SCR

ì d 2j r qN A
ï 2 = - = ;0 £ x £ xd Boundary conditions:
ï dx es es
í 2
ïd j dj
j (¥) = =0
ïî dx 2 = 0; x ³ xd dx ¥

Two integrations:

ì qN A
ïj ( x ) = × ( x - x ) 2
;0 £ x £ x d
2e s
d
í
ïj ( x) = 0; x ³ x
î d

At the interface: x = 0; j = j s
qN A 2 2e s
js = × xd xd = js Qb = -qN A x d = - 2e s qN Aj s
2e s qN A
 14
Strong inversion threshold voltage:
By definition: r (x)
depletion

Ψ s = 2j F Qm
VG = VTn Þ wm
n s = p0
x
It can be shown that the Qb=-qNAwm
surface potential is:
Beyond VT, the electron layer acts
kT æ NA ö
j S = 2j F = 2 × × lnçç ÷÷ as a screen, the surface potential and
q è ni ø the depletion width stop increasing.
2ε s
The maximum depletion width is: wm = (2j F )
qN A
Qs = Qb (2j F ) = -qN A wm
and the maximum charge in the SCR is:
= - 2ε s qN A (2j F )
 15
Charge vs surface potential

Hole Strong
accumulation inversion

Weak
inversion
Depletion
 16
Charge vs depth

holes

electrons

holes

electrons

Depth Depth
 17
Strong inversion: vG > VTn Þ Ψ s ³ 2j F
An electron layer (inversion channel) is formed at the Si/SiO2
interface QM (positive)

vG ( )( ) ( ) ( )( ) Inversion channel

pSi substrate Qi = -Cox × (vG - VTn )

r (x)
depletion
For vG > VTn the electron
surface concentration is not
negligible any more.
Qm wm
x Semiconductor charge/cm2:
Qb=-qNAwm
Qsc = Qb( 2j F ) + Qi
Qi
 18
Qb
From: VG = - + Ψ s (VG )
Cox

tox
VG pSi

The strong inversion threshold voltage of the ideal

MOS capacitor can be derived:
- Qb (2j F ) 2ε s qN A (2j F )
VTn = + 2j F = + 2j F
Cox εox /tox
It depends on the oxide thickness tox and on the substrate
doping concentration NA
 19

Example: ideal Metal / Oxide / pSilicon capacitor

substrate: pSi NA = 1015/cm3 es » 10-12 F/cm

kT æ N A ö æ 1015 ö
2j F = 2 lnçç ÷÷ = 2 × 0.026 ln çç ÷ @ 0.58V
10 ÷
q è ni ø è 1.4 ´10 ø

oxide: SiO2 tox = 34 nm = 3.4´10-6cm

eox = 0.34 ´ 10-12 F/cm
so that: Cox = e ox / tox = 10-7 F/cm2

2ε s qN A( 2j F ) 2 ×10 -2 ×1.6 ´10 -19 ×1015 × 0.58

VTn = + 2j F = -7
+ 0.58 @ 0.72 V
εox / tox 10
 20

Capacitance of the MOS capacitor

tox
Co VG
C pSi
Cs
SCR

1 1 1 Cox C s
= + C= [F/cm2]
C Cox Cs Cox + C s

εox εs
Cox = Cs =
tox w[Ψ s (VG )]
 21

Capacitance – Voltage characteristics

C=C (VG) measurement

Qi
C-V meter
VG
pSi
C = C (VG)

Chf (VG) at high frequency (e.g., 1 MHz): Qi varies with the bias
voltage but can not keep pace with the measurement signal

Clf (VG) at low frequency (e.g., 1 Hz): Qi varies with the bias
voltage and keeps pace with the measurement signal
 22

Example: ideal Metal / Oxide / pSilicon capacitor

C [F/cm2]
εox
= Cox
tox CFB low frequency Clf

εox ε s
×
tox wm high frequency Chf
= Cmin
εox ε s
+
tox wm
VG
0 VT ~ 0.72V
accumulation depletion strong inversion
 23

Flat Band capacitance

Semiconductor capacitance/cm2:
εs εs
Cs,FB (Ψ s = 0 ) = =
LD ε s kT/q 2 N A

Debye length: LD = 2
ε s kT/ (q N A )

Total MOS capacitance /cm2 :

C FB =
Cox Cs,FB
=
(εOX /tOX ) × (ε S /LD )
Cox+Cs,FB (εOX /tOX ) + (ε S /LD )
 24

Strong inversion threshold voltage in a real MOS capacitor:

Qb (2j F )
VT = + 2j F + VFB
Cox
Ideal MOS
Flat Band voltage:
Qeq F ms
VFB = Φms -
Cox

Φms = Φm - Φs Metal-Semiconductor
Workfunction difference

Qeq = equivalent oxide charge

 25

Equivalent oxide charge : Qeq

~ 1010 +q/cm2 for (100) Si/SiO2

Qeq =
~ 1011 +q/cm2 for (111) Si/SiO2

due to :
• ionic contaminations
in the oxide
• fixed interface charge
• electric stress
• radiation damage
 26

Example: real Metal/ Oxide / pSi capacitor

substrate: (100)pSi NA = 1015/cm3 YB = 0.29 V

oxide: SiO2 tox = 34nm Cox = 10-7 F/cm2
metal=Al
Φms = Φm - Φs = 4.10 - 4.80 = -0.70V
Qeq / Cox = 5 ´1010 ×1.6 ´10 -19 / 10 -7 @ 0.08V
Qeq
so that: VFB = Φms - = -0.78
Cox
VT = VT (ideal) + VFB = 0.72 - 0.78 = -0.06 V
 27
Example: real Metal / Oxide / pSilicon capacitor

C [F/cm2]
Cox
CFB
(ideal)

Cmin
VG
VFB ~ -0.78V VT ~ -0.06V

accumulation depletion strong inversion

Note that at the silicon surface an inversion layer is present also

if the gate is floating, due to Φms and Qeq
 28

Strong inversion threshold voltage adjustment

It is possible to control the flat-band voltage VFB

and so the threshold voltage VT by means of ion
implantation :
Qeq ± Qii
VFB = Φms - -
Cox Cox
Threshold adjustment
ion implantation

Using the Threshold adjustment ion implantation

positive charges (donors) or negative charges (acceptors)
can be introduced at the silicon surface close to the Si/SiO2
interface, so as to shift the flat-band voltage.
 29

Example: real Metal / Oxide / pSilicon capacitor

Threshold voltage shift from -0.06V to VT = +1V

DVFB =Qii /Cox= +1.06V by means of acceptor implantation

Qii = -Cox × DVFB = -1.06 ´10- 7 C/cm 2

Ion implantation at the semiconductor surface

(low energy) at a dose:
Qii 1.06 ´10 -7
= ~ 7 ´ 1011
Boron ions/cm 2
q 1.6 ´10 -19
 30
Example: real Metal / Oxide / pSilicon capacitor

High frequency characteristic Chf(VG) after ion implantation

C [F/cm2]
Cox
DVFB

VG
VFB ~ 0.28V VT ~ 1V

accumulation depletion strong

inversion
 31
III.1.2: from MOS capacitor to MOS transistor

n-channel MOSFET

W
S L D L: channel length
W: channel width
Source Gate Drain
tox: Gate oxide
n+ n+

pSi (substrate) Qi inversion channel

Bulk (electrons)
(Source and Drain junctions: abrupt model)
 32
Reference condition: Common Source configuration

vGS > VTn iD

S iD
D
n+ n+
vDS G B vDS
pSi (substrate)
vGS
B S
Circuit symbol
Gate voltage vGS > VTn (positive)
Drain voltage vDS (positive)
Drain current iD (positive)
Bulk voltage vBS = 0
At gate voltages vGS < VTn we assume that the transistor is off
 33

a) quasi-linear region : vDS < vGS - VTn

vGS > VTn iD

S

n+ n+
vDS
pSi (substrate)

æW ö é vDS ù
2
Drain current : iD = k n × ç ÷ × ê(vGS - VTn ) × vDS - ú
èLø ë 2 û
æW ö
k n = “technological” conductivity ç ÷ = aspect ratio
èLø
 34

é vDS ù
2

Drain current : iD = b n ê(vGS - VTn ) × vDS - ú

ë 2 û
æW ö
b n = k n × ç ÷ = “extrinsic” conductivity
èLø
At vDS << vGS - VT (linear region):
iD
iD @ b n × (vGS - VTn ) × vDS = Gch × vDS
1
Gch = b n × (vGS - VT ) =
Rch
Voltage controlled resistor
0 vDS
linear vGS - VTn
 35

b) pinch - off: vDS = vGS - VTn = VDsat

iD
S vGS > VTn vDS

n+ n+

pSi (substrate) iD
B
IDsat

Drain current :
bn
iD = (vGS - VTn ) = I Dsat
2

2 0 VDsat vDS
 36

c) saturation: vDS > vGS - VTn

iD
S vGS > VTn vDS
n+ n+

pSi (substrate) iD
B IDsat

Drain current :
bn
iD = (vGS - VTn ) = I Dsat
2

2 0 vDS
 37

Static current-voltage characteristics iD = iD (vDS; vGS )

iD VDsat
vGS = 6 V

5V

4V
3V
2V
0 2 4 6 8 vDS

at vGS < VTn (= 1V): iD ~ 0 transistor is off

 38
Static characteristic analysis iD=iD(vGS; vDS)
nch-MOSFET in the quasi-linear region: vGS >VTn; vDS < vGS -VTn
Model: iD
vDS
vGS
Gate
channel
n+ source n+ drain

ground 0 voltage vDS v

0 distance L x
é vDS ù
2

It can be shown that: iD = b n ê(vGS - VTn )vDS - ú

ë 2 û
where: b n = µ n*Cox (W / L ) = K n × (W / L ) Extrinsic
conductivity
 39
Demonstration.

We assume the Gradual Channel Approximation,

that allows for a 1-D analysis, since it involves:

• Long channel: the transversal electric field (E┴) is not

correlated to and is much higher than the longitudinal
electric field (E//). [This always holds if Vds is not very high]
• The only current contribution comes from drift
• The mobility in the channel is constant (not dependent
on E) [But note that it differs from the mobility in the bulk]
• Sub-threshold currents are null

Every slice of the channel can be assimilated

to an elementary MOS capacitor.
 40

Source L W Drain

vDS
vGS > vTn
iD
x
channel d
n+ source n+ drain

Qi (0) Qi (x) Qi (L)

ground vDS
v(x) dv( x)
E=
dx

x
0 x x + dx L
 41
Charge in the inversion channel:

Qi (0) = -Cox × (vGS - VTn )

Qi ( x) = -Cox × [vGS - v( x) - VTn ]
Qi ( L) = -Cox × [vGS - vDS - VTn ]
Charge contained in a Wdx element of the inversion
channel (having a thickness d):

dQi ( x) = -Cox × [vGS - v( x) - VTn ]× Wdx

Electron density in the inversion channel:

dQi Cox × [vGS - v( x) - VTn ]

n( x ) = =
- qdWdx qd
 42
Current density (drift component):
Cox × [vGS - v( x) - VTn ]
J n ( x) = qn( x) µ E =
*
µ E
*

d
n n

Total current:
iD = Wd × J n ( x)
= Cox × [vGS - v( x) - VTn ]× Wµ E *
n

dv( x)
= Cox × [vGS - v( x) - VTn ]× Wµ *
n
dx
Integrating along the channel:
L v DS

ò iD dx = ò n × Cox ×W × [vGS - v( x) - VTn ]dv

µ *

0 0
 43
And finally ...

æ W ö é v 2
ù
iD = µ n × Cox × ç ÷ × ê(vGS - VTn ) × vDS -
* DS
ú
èLø ë 2 û
e ox
Cox = gate oxide capacitance/cm2
tox
µ = electron mobility in the channel
*
n
(~ 0.5µn in substrate, due to surface scattering)
K n = µ n*Cox : technological conductivity (process dependent)
W/L : aspect ratio (design dependent)
For a given technology, the designer can choose the conductivity
within a large range of values by changing the device width and
length (aspect ratio).
 44

Example: n-channel MOSFET

n+ poly-Si
metal

W NA = 1015/cm3
S L D
tox = 34 nm
Cox = 10-7 F/cm2
Source Gate Drain µn* ~ 200 cm2/ Vs
“driver” MOSFET
n+ n+
W/L = 4
pSi (substrate) bn ~ 0.28 mA / V2
 45

Example: n-channel MOSFET

n+ poly-Si
metal

W NA = 1015/cm3
S D
L tox = 34 nm
Cox = 10-7 F/cm2
Source Gate Drain µn* ~ 200 cm2/ Vs
“load” MOSFET
n+ n+
W/L = 1/4
pSi (substrate) bn ~ 0.018 m A/V2
 46
n-channel MOSFET :
Threshold voltage measurement VT0=VT(VBS=0)
vDS = vGS > vGS -VTn
iD Diode configuration
iD (MOSFET in saturation)
D

G B vDS
bn
iD = (vGS - VT )
2
vGS
S 2

VT vDS (= vGS )
 47
n-channel MOSFET :
Threshold voltage measurement VT0=VT(VBS=0)

vDS = vGS > vGS-VTn

iD
MOSFET in saturation
iD
D

G B vDS
vGS * bn
S
iD = (vGS - VT )
* 2
*
* * * V vDS (= vGS )
T
 48

Body effect: VTn = VT0 + DVT (vBS )

It can be shown that: [
ΔVTn = γn × 2j Fn + vBS - 2j Fn ]
iD
iD where: g n = 2e s qN A / Cox
D vBS= 0V; -1V; -2V;

G B vDS
vGS vBS
S

VT0 VT1 VT2 vDS (= vGS )

 49

Physical reason of Body effect

If Vbs<0, the surface to substrate potential is larger à The depletion region

is wider, and more majority charges (holes in n-channel MOSFET) should
be repelled before the channel can be formedà Larger threshold voltage.
 50

Example: n-channel MOSFET

iD VT0 = 1 V
S vGS > VTn vDS
NA = 1015/cm3
n+ n+ tox = 34 nm
Cox = 10-7 F/cm2
pSi (substrate)
Body effect coefficient:
B
vBS gn ~ 0.18V1/2
2fFn = 0.6 V

vBS[V] 0 -1 -2 -3 -4 -5

VTn[V] 1 1.08 1.15 1.20 1.25 1.29

 51
III.1.3: MOSFET non idealities
a) Channel length modulation
Saturation: vDS > VGS - VTn = VDsat ; vBS = 0
L 2ε s
ΔL~ (VDS - VDsat )
S qN A
n+ n+

pSi (substrate)
B
iD
bn
iD ~ (vGS - VTn )2 (1 + λvDS )
2

VA = 1/λ 0 vDS
 52
Channel length modulation
&' +,
!" = $" + )*
VB=0, VS=1 V è VTH=0.8 V ( *-

VG=3 V è VDS-SAT=1.2 V

potential (V)
position along the channel (um)

electron concentration (cm-3)

2ε s
ΔL~ (VDS - VDsat )
qN A
position along the channel (um)
 53

b) MOSFET capacitances
There are 3 main contributions:
• The MOS capacitor structure
• The inversion channel charge
• The space charge regions associated to the junctions

Gate
Source Drain
CGS CGB CGD

CSB CDB
Bulk
 54

MOS structure capacitances

Gate
Source/drain diffusion extend
below the gate oxide by the
lateral diffusion (xd), thus W Source Source
causing the source/drain overlap xd xd
capacitances:
Gate-bulk
overlap

C gso = C gdo = Co ´ W L

Co (F/m) tox
Leff

Cgso Cgdo
Gate-bulk overlap capacitance: G/S overlap G/D overlap

Weff

Cgbo = C o' ´ L, C o' (F / m)

Source/Drain
Cgbo/2
Overlap Overlap
 55

Channel capacitance

• The channel capacitance is nonlinear

• Its value depends on the operation region
• It consists of three components:
Cgb - gate-to-bulk capacitance
Cgs - gate-to-source capacitance
Cgd - gate-to-drain capacitance

Operation region Cgb Cgs Cgd

Cutoff Cox W L 0 0
Linear 0 (1/2) Cox W L (1/2) Cox W L
Saturation 0 (2/3) Cox W L 0
 56
Channel capacitance

MOSFET - Saturation
 57
Channel capacitance
Cg = Weff ´ Leff ´ Cox
Gate-to-bulk
Cg + Cgbo
Gate-to-source

2/3 Cg + Cgso

1/2 Cg + Cgbo

Gate-to-drain
Cgdo , Cgso
Cgbo
!"" #$%&'$%() *+,($'
 58
Junction capacitances
Csb and Cdb and diffusion capacitances composed of:

• Bottom-plate capacitance: Cbottom = C j × W × Ls

• Side-wall capacitance: Csw = C jsw × (2 Ls + W )

Side wall Bottom plate

Channel-stop
implant
W

Xj Channel
Ls
 59
c) Subthreshold conduction
At Vgs < VT the current is non zero.
Even subthreshold, indeed, a certain
amount of minority carriers is present
at the Si/SiO2 interface, that allows a
current to flow if Vds>0.
This is particularly relevant for the
design of circuits operated with low
voltage supplies and for dynamic logic
gates;
From the 2D analysis of the device, the following expression can be
derived for the current, mainly due to the diffusion component:
2
æ kT ö é q × (vGS - VT ) ù é æ qvDS öù
id @ K n × çç ÷÷ × exp ê ú × ê1 - expç - ÷ú
è q ø ë nkT û ë è kT øû
At VDS >> kT/q, the current no longer depends on VDS
 60

Other important short-channel effects

Due to the continuous reduction in the MOSFET
geoemetries, other effects normally negliged should
be carefully considered for short channel devices:
• source and drain series resistances
• velocity saturation of carriers in the channel
• short channel (L<<) and narrow channel (W<<)
effects on the threshold voltage
• impact ionization, hot electrons,
• gate currents, substrate currents ...
• punch-through conduction
 61
III.2: TCAD: analysis of n-channel MOS transistor
Poly-Si Gate
metal (Source) metal (Drain)
0
n+ n+ Field oxide
XJ
Cross-section
p (substrate)
Gate oxide
Gate

Drain
Si Layout
Chip
Source
 62
nch-MOSFET process simulation
1 Active area
Litho + Boron implantation + LOCOS oxidation
oxide

channel stop

pSi substrate
 63
2 Threshold adjustment channel implantation

Boron
 64
3 poly-Si gate
Gate oxide, n+ poly-Si deposition, litho and etching
Gate oxide: Poly-Si gate
tox=12nm tpoly = 450 nm

L=1µm
 65

4 Source & Drain

Arsenic implantation and drive-in (self-aligned S&D)

Xj~0.15µm
 66
5 Poly passivation and contact opening
CVD oxide deposition + litho

Field
oxide Poly-Si
Fox gate
 67
6 Interconnections
Aluminium deposition + litho + etching

Poly-Si Gate
Source Drain

pSi substrate
 68

1D process simulation

1D section
x
x x

Doping profiles
S&D junctions
Channel stop
channel

0 1 2
x[µm]
 69

Transfer characteristic simulation

iD=iD(vGS)
Threshold voltage calculation: VTn
20

15
ID [µA]

10
VTn
5

VGS [V]
 70
Output characteristics simulation
ID=ID( VDS,VGS )

40
VGS=5V
30
VGS=4V
ID [µA]

20

VGS=3V
10

VDS[V]
 71
N-channel MOSFET:
without the threshold adjustment implantation ...
 72

ID ( VGS ) characteristics

without implant
20
with
15
implant
ID[µA]

10

5 VTn
0

VGS[V]
III.3 CMOS Technologies 73

Poly-Si Gate, N-channel MOSFET

source drain
SiO2 SiO2
n+ n+
p+ p+
pSi (substrate)
a) cross-section
gate

drain

b) layout

source
 74

Poly-Si Gate, P-channel MOSFET

source drain
SiO2 SiO2
p+ p+
p+ p+
n-well
pSi (substrate)
a) cross-section
gate

drain

b) layout n-well
source
 75

Basic microstructure of CMOS technology

(Complementary n-ch/p-ch MOSFETs)
• high integration density
• low power consumption

n-ch. MOSFET p-ch. MOSFET

n+ n+ p+ p+

n-well
pSi (substrate)
 76

III.3.1 Active and passive components

• Besides n-channel and p-channel MOSFETs

• p+/n-well diodes n-well

b) layout
p+ n+

A K

a) cross-section Fox SiO2

p+ n+
p+ n-well p+

pSi (substrate)
 77

Basic CMOS technology: passive components

b) layout
• resistors
n-well
a) Diffused resistors p
• p+ in n-well L
W

Rs (p+) ~ 10÷ 30W / L n+

p
R = Rs(L/W) W

a) cross-section Fox
p + n+
p+ n-well
pSi (substrate)
 78
b) polySi resistors depositated on field oxide Fox
Rs (polySi) ~ 100÷ 1000 W /
b) layout
W
R=
Rs(L/W) L

nch-MOSFET
SiO2
n+ n+
p+ channel stop

pSi (substrate)
a) cross-section
 79
• MOS capacitors

2
e ox 1
C = ACox = A
tox
layout

1
2
Fox SiO2
p+ n+ p+
n-well
Cross-section
+ poly1-poly2, poly-metal capacitors