Performance Analysis of AFDX Switch for

Space On-Board Data Networks

Chakkaphong Suthaputchakun, Zhili Sun, Senior Member, IEEE,
Christoforos Kavadias, and Philippe Ricco

The resource sharing concept then becomes more promising

Abstract— AFDX is designed for deterministic communications and concrete in early 2000 through Avionics Full-Duplex
in avionics sensor networks embedded in large aircraft such as Switched Ethernet (AFDX) standard initiated by Airbus [10-
the Airbus A380 and Boeing 787. This paper proposes to apply 11] and developed in Airbus 380 and Boeing 787 aircrafts [12-
the AFDX concept to space domain since there are increasing
13] shown in Figure 1. Aeronautical Radio, Incorporated or
requirements to develop a similar system in spacecraft. In this
paper, the AFDX switch is comprehensively studied and analyzed
ARINC-664 Part 7 specification [14] is the AFDX standard
to provide a tailorisation of the standard for applicability to the providing technology for network I/O in IMA architectures
space domain. The evaluation results show that AFDX can be and offering hardware assisted service, determinism and
efficiently adapted for space on-board data networks to provide standardization as a minimum to efficiently deal with
deterministic communications even in asynchronized and high- flexibility, scalability, reliability, and security in space on-
traffic networks. board data networks. Since AFDX is currently implemented in
avionics industry, it is of interest for the space industry to
Index Terms— ARINC-664, AFDX, Avionics Full-Duplex investigate if similar technology could be adapted to the space
Switched Ethernet, Space on-board data network, IMA, domain due to very similar requirements.
Integrated Modular Avionics Table I shows a comparison of Ethernet, TTP, and AFDX
specifications for deterministic communications [15]. Both
I. INTRODUCTION AFDX and TTP achieve in providing deterministic
eterministic communications are crucial and significantly communications except Ethernet. TTP relies on robust fault-
D demanded for military communication especially in
avionics sensor systems. There are several applications
tolerant synchronization, tight control of jitter, TDMA
communication, and scheduled exchange of data frames.
relying on the deterministic communications of both aircraft However, it has a strict limitation in term of communication
and spacecraft such as statistical detection of anomalous pilot- bandwidth. In contrast, ADFX achieves much higher
aircraft interactions, and sensory information exchange for safe bandwidth, while providing a good control of jitter and real-
spacecraft landing [1-4]. The pioneer concept [5] of the time communications. Thus, AFDX becomes more suitable to
traditional avionics communications developed in 1990 is support a wider range of systems and applications, such as
based on the principle that a set of resources, such as one deterministic backbone, IMA 1G, core avionics systems,
computer and one dedicated network or data bus, is dedicated modular control, and by-wire systems.
to only one function. This becomes very challenging to
interconnect all the devices. A lot of cable also raises concerns
regarding installation, maintenance, cost, and reparation. It is
obviously not cost-effective approach.
Integrated Modular Avionics (IMA) architectures [6] is
introduced based on the resource sharing, such as sharing
capability of processing units, electronic devices, and networks
or data buses. The IMA standard mainly defines time and Figure 1 AFDX equipped aircraft [12-13]
space partitioning of processing units. The standard also Therefore, this paper aims to evaluate the performance of
addresses policies and several APIs for communication and AFDX communication switch for applying this ARINC-664
resource sharing. Therefore, Time-Triggered Protocol (TTP) standard into space on-board data networks. The ARINC 664
[7-9] with a shared bus has emerged as a new protocol in part 7 will be analyzed to provide a tailorisation of the
distributed avionics real time system. TTP can achieve the standard for applicability to the space domain. The evaluation
maximum bandwidth of 5Mbps and satisfy rigid requirements will focus on network capability, full duplex and physical
of avionics systems in terms of reliability and real-time interconnection, traffic policy, virtual link, bandwidth
communications. TTP transfers the data frames by means of allocation gap concept, redundancy, filtering, integrity, and
radio propagation using TDMA multiplexing and the global network management function.
clock. TTP can improve determinism, security, and reliability
of distribution avionics communications.
 TABLE I
COMPARISON OF TTP AND AFDX SPECIFICATIONS
Standards
Specifications Ethernet TTP AFDX
Network Traditional Ethernet Deterministic Fieldbus Deterministic Ethernet
Media Access Full Duplex, Switched Scheduled Communication, TDMA Full Duplex, Switched
Bandwidth 1Gbps and higher Up to 5 Mbps (BUS), and 20 Mbps (STAR) Up to 1 Gbps
Determinism Non-Deterministic: Best Effort Deterministic: Defined fixed latency, jitter, and Deterministic: Defined maximum latency for all
frame order Virtual Links
Frame Size Up to 1522 Bytes Up to 248 Bytes Up to 1518 Bytes
Redundancy No Yes Yes
Fault Tolerant System Clock No Yes No
Real-Time Limited Yes Yes
Hard Real Time No Yes Limited
Target Application Standard LAN Modular Control and Deterministic By-Wire Deterministic Backbone, IMA 1G, Core Avionics
Systems Systems, Modular Control, By-Wire Systems

Therefore, the main objectives of the paper can be four major functional layers: network application layer,
summarized into three folds as follows; transport, network, and data link. A complete AFDX network
- Study an impact of high network load on AFDX’s consists of two kinds of components: End System (ES) and
performance: In a high traffic network, AFDX can Switch. A suite of functional elements operate on an AFDX
achieve in providing high data integrity End System to sequentially process data sending and reception
and deterministic timing, such as 100% reception rate and is depicted in Figure 2.
bounded end-to-end jitter.
A. AFDX End System
- Study an impact of loose time synchronization on
The design of AFDX End System (ES) is to provide service
AFDX’s performance: AFDX is robust to a network with
of guaranteeing secure and reliable data exchange amongst the
loose time synchronization; i.e. time drift, by achieving
partition software. Each avionics computer system is equipped
high data reception rate and deterministic delay time.
with an End System as its network interface through which the
- Study an impact of unexpected event on AFDX’s
host applications on the avionics system, i.e. avionics
performance: AFDX can maintain high system
subsystems, can communicate with other avionics computer
performance in respect to impacts of unexpected events,
systems.
such as an unfunctional hardware causing anomaly large
communication delay jitter. 1) Virtual Link and MAC Addressing
The rest of the paper is organized as follows. Section II The concept of Virtual Link is used in an AFDX network to
gives an overview of AFDX standard. The detail of system build virtual connections for both sides of communications.
models and configurations is described in Section III. Section The virtual links isolate the underlying available bandwidth of
IV provides the performance evaluations and analysis of the physical connection, which therefore provide feasibility for a
AFDX switch as well as its applicability in space on-board host application to allocate multiple communication channels.
data networks. Finally, Section V concludes the paper and The mechanism of isolation is also helpful in protecting
provides guidelines for future implementation. individual Virtual Link from being affected by other Virtual
Links sharing the same physical bandwidth.
A Virtual Link is a logical unidirectional connection which
originates from a source End System to one or more
destination End Systems. As specified in the AFDX standard,
an End System can have receive VLs and / or transmit VLs.
However, it should be assured that each transmit VL can
originate from only one End System, but it may represent
multiple recipients on an AFDX network. The AFDX switch
will analyze the Virtual Link ID of the received frame to
determine which output ports the frame can be dispatched to.
Figure 3 illustrates an example of packet routing.

Figure 2 AFDX End System protocol layers

II. AFDX OVERVIEW

AFDX [16-20] is defined as a deterministic network used
for the aircraft system. The AFDX standard is included in the Figure 3 Example packet routing
ARINC specification 664 as part 7. The standard consists of
2) Algorithm of Flow & Traffic Control and Scheduling The range of jitter for each VL at the output of an End
Two parameters are defined to regulate the traffic carried by System defined in the standard can be calculated as follows:
VL(s): Bandwidth Allocation Gap (BAG) and jitter. BAG
specifies the minimum time interval between the first bits of  (20bytes  L max j
)8
two consecutive frames on the same VL. Figure 4 shows an max_ jitter  40s  j{ setsofVLs}

example of traffic regulation on a Virtual Link. Nbw

(1)
max_ jitter  500s
(2)

where Lmax j denotes the maximum allowed frame size on jth

Figure 4 Regulator input and output Virtual Link, Nbw is the link bandwidth in Mbps (e.g. 10
Mbps, 100 Mbps). Equitation (1) is for an end system having a
In Figure 4, if the data flow inputted into a regulator is
small number of Virtual Links with small frame sizes.
unregulated, the possible consequence could be congestion on
Equitation (2) is the upper limit for all cases of Virtual Links
an End System’s output port, especially when a Virtual Link is
on an end system.
under heavy load. The unpredictable arrival of data packets
Each Virtual Link must be assigned with a certain BAG and
could lead to inefficient bandwidth usage. The idea of BAG is
Lmax. The selection of BAG and Lmax for a Virtual Link
to shape data flow by defining minimum timeslot between two
depends on the designed traffic load.
consecutive frames. Specifically, only one data fame is
allowed to be processed within each slot, and the processing 3) Redundancy Management
should start from the beginning of a slot (illustrated as Redundancy management in an AFDX network is achieved
“Regulator Output” in Figure 4), by which the performance of through employing independent and redundant networks. If
network communication is possible to be predicted and redundancy management is enabled, each End System
measured. BAG is a value ranging in power of 2 from 0 to 7 connects to two networks, i.e. network A and B, and send data
(i.e. from 1 to 128 milliseconds). packet through these two networks respectively. A sequence
As mentioned before, an End System could be featured with number is added to each frame and increase on each
multiple Virtual Links. A specific virtual link scheduler is successive frame. Upon receipt of data frames, the receiving
needed to multiplex data frames from different Virtual Links End System would check the frame with the policy of “First
onto the same physical Ethernet link (as shown in Figure 5). Valid wins”, which means the first valid frame received by the
destination End System, will be accepted. The secondly
received or invalid frame will be simply discarded.

B. AFDX Switch
AFDX switch is the device that interconnects both
communicating End Systems, and polices data traffic
according to the specified configurations. There are five
functional blocks defined for an AFDX switch, Filtering &
Policing Function, Switching Function, End System,
Figure 5 Virtual link scheduler
Configuration Tables and Monitoring Function (as shown in
In Figure 5, multiple regulated traffics are fed into a unified Figure 7).
scheduler. Jitter will not be present when traffic is processed
by traffic regulator which works on per-link basis. However End System
certain jitter is measurable on multiplexed flow due to the
Monitoring
process delay on the Scheduler MUX. AFDX standard Configuration
Tables Function

specifically defines the concept of Jitter, which is used to

bound the upper limit of transmit latency between the start of a
Switching Function
BAG and the first sent bit of the frame being transmitted
Filtering &
within the corresponding slot. Policing Function

Jitter is applied at the output of an End System, i.e. the

output of a scheduler, to measure the contention of data frames
when a scheduler is scheduling VLs (Figure 6).
Figure 7 AFDX switch function blocks

1) Filtering and Policing Function

Filtering function means only valid frames will be accepted
by a switch. The validation includes frame size, frame
Figure 6 Virtual Link scheduling with jitter
integrity, and frame destination. If validation fails, the invalid Traffic policing algorithm can effectively avoid acceptance
frame will be discarded. of false packet not conforming deterministic characteristic. An
An algorithm for policing traffic on a switch is described in example of frame-based traffic policing with Jimax=BAGi/2 is
the AFDX specification. Traffic policing operating on a switch shown in Figure 8.
is for performing traffic control on each virtual link. A virtual In Figure 8, the initial value of ACi is Simax(1+Jimax/BAGi).
link is defined with certain properties regulating the traffic it When packet 1 arrives at the beginning of BAGi where no
carries, such as the identification of recipients, minimum gap jitter is present, this packet is accepted by switch since ACi is
between two frames. Each received frame is policed with the greater than Simax. Accordingly, ACi is immediately debited by
configuration parameters assigned to the Virtual Link which Simax. Due to the proportional increment on ACi, it recovers to
conveys the frame. The parameters are based on BAG, Jitter, Simax(1+Jimax/BAGi) at the beginning of second BAGi. When
Smax (maximum frame size for the corresponding Virtual Link), packet 2 arrives just at Jimax, it is also able to be accepted as the
and Smin (minimum frame size for the corresponding Virtual acceptance condition of ACi is satisfied. Similar situation
Link). happens to the arrival of packet 3 and 4. When packet 4 is
The AFDX standard specifies the use of algorithm, “token accepted, ACi has been completely consumed. According to
bucket”, to validate the eligibility of each packet. An AFDX the definition of ACi, it corresponds to the time necessarily
switch maintains an account, also called as AC and expressed required to process a packet assuming it is with maximum
in bytes, for each Virtual Link connects to it. For example, ACi frame size, i.e. Simax. Before ACi recovers to Simax, no new
corresponds to VLi. Another three parameters are also packet should be accepted as the processing of previous packet
employed to cooperate the use of AC, Simax (the maximum may not complete. Take packet 5 as an example, when it
frame size for VLi , which is a configurable parameter in the arrives, ACi just recovers to a value less than Simax. Then
range of 84-1538 bytes), Simin (the minimum frame size for packet 5 should be discarded. Otherwise, the bandwidth of VLi
VLi, which is a configurable parameter in the range of 84-1538 could be insufficient. By using ACi as a parameter to measure
bytes), and Si (the frame size of currently received packet on the bandwidth available for use, frame-based traffic policing
VLi). algorithm can effectively regulate traffic on a switch. Carrying
ACi is initially set to Simax(1+Jimax/BAGi), which is also the out further study and design for achieving a proper
upper limit of ACi. Jimax denotes the maximum credit on switch implementation of traffic policing is therefore the major
for VLi. Then ACi is credited as time elapsing and proportional challenge in simulation work.
to Simax/BAGi. This proportion rate is equal to the allowed
2) Switching Function
average flow rate on VLi during each BAGi. AFDX
Each AFDX switch maintains a configuration table, from
technology specifies two kinds of traffic policing account, byte
which the destination MAC address of a received frame can be
based and frame based. An AFDX network can implement
mapped to corresponding output port(s) to which the frame
either of them or both.
should be forwarded. A switch should be capable of receiving
frames on any port, and forward them to any combination of
For byte-based traffic policing:
ports. This is to ensure the integrity of Virtual Link
 If remaining byte ACi is greater than Si, the frame is communication protocols. For example, an End System could
accepted and ACi is debited by Si. send data through a Virtual Link, when a host application on
 If remaining byte ACi is less than Si, the frame is discarded. the sending End System is also one of the recipients. Allowing
ACi will not be changed. an AFDX switch to forward frame to the original sender from
which it was received can increase system’s portability. The
For frame-based traffic policing: AFDX standard also specifies that an AFDX switch can
 If remaining frame ACi is greater than Simax, the frame is accommodate priority based mechanism to manage the
accepted and ACi is debited by Simax. sequence of packet dispatching.
 If remaining frame ACi is less than Simax, the frame is 3) Switch End System Function
discarded. ACi will not be changed. As specified by the AFDX standard, an AFDX switch
should comply with all the requirements designed for an End
System except for the redundancy management.
4) Configuration Tables
Each AFDX switch should support the use of configuration
tables with two models: Default_Configuration_File which is
used when a switch is empty or being dataloaded, and
OPS_Configuration_File which is used when a switch is in
Operational mode. The configuration tables should contain the
parameters for switch to perform filtering and policing
Figure 8 Example of frame based traffic policing with Jitter=BAG/2 function, switching function and End System function.
5) Monitoring Function
The AFDX monitoring function consists of three aspects:
Management Information Base (MIB) for each AFDX
component to record its internal information, Simple Network
Management Protocol (SNMP) operating on each AFDX
component to communicate with the Network Management
Function, and Network Management Function to control and
manage all network related issues.

III. SYSTEM MODELS AND CONFIGURATIONS

This section describes the system models as well as its
default configurations based on the requirements of typical
spacecraft.
A. System Models
The use case system model in the simulation is shown in
Figure 9. Based on the topology provided as representative
one for space domain, the system model consists of 16 AFDX
End Systems (ES) that communicate to On-Board Computer
(OBC). There are 2 Virtual Links (VL) for each ES as
expected by the data profile analysis. OBC will receive 32 VLs
in total. To simplify the simulation, we consider same
messages for all end systems with 2ms Bandwidth Allocation Figure 10 End System Model
Gap (BAG). The simulation will present
1) End System Model
 6 end systems which are ES1 to ES6 (12 TX VLs) As previously presented, there are 16 end systems in the
simulation scenario, which have the same architecture and are
 Another end system (EM) that emulates a switch connected modeled as shown in Figure 10.
to other 10 end systems (20 TX VLs)
The end system consists of several modules for both
 One AFDX switch transmission and reception sides of view. Each module has
 The OBC that will receive all the messages (32 RX VLs) different functions and is dependent from other modules. The
 2 VLs of each end system with a configuration of 2ms BAG. configuration of each module can be read directly from an
external configuration file, such as XML file. The detail of
On the end systems and the switch emulator (also each module is presented as follows.
considered as one end system), one VL will be transmitted on  Partition module acts as a source and destination of
the first 1ms slot and the second VL will be transmitted on the messages. Applications running in the partition module of
second 1ms slot. On the switch, First-In-First-Out queues the transmission side will generate messages regularly
(FIFO) are implemented in all 8 physical ports (7 input ports according to its configuration, such as data frequency,
and 1 output port). The switch’s scheduling technique as the while applications running in the partition module of the
default is Round Robin (RR). The switch processing time is reception side need to know what kind of data is expected
assumed to be 10µs (excluding queuing delay in the switch). to receive and pass them to users.
 TxLogicalPort module is a logical port defined for each
virtual link, which links messages from the partition
module to a TxVLQueue module.
 TxVLQueue module acts as the message buffer before
passing the messages to the traffic regulator. The buffer
size of the TxVLQueue module can be automatically
configured using parameter values from the external XML
configuration file.
 Regulator module regulates the traffic of each virtual link
based on BAG values read from the XML file.
 Scheduler (Multiplexer) module schedules the traffic for
transmission. In our simulation, the scheduler is assumed
Figure 9 Use Case System Model
to be Round Robin.
 Duplicator module makes a copy of all messages before
transmission for redundancy management (RM). Each
copy of the messages will be passed to different
transmission queues waiting for transmission via different
network interfaces. However, if the message redundancy
 management is disabled, the duplicator module will not  PriorityClassifier module takes a responsibility to classify
make any copies of the messages, but only pass the received messages based on their priorities embedded in
original message to the main network interface. the messages, which could be either high or low priority.
 TxQueue Module is used to store messages while waiting According to the use case configuration, there is only low
for an available communication channel. priority messages transmitted in the simulated AFDX
 ESPort modules are physical ports to transmit a message network.
to different physical communication links, once channels  HighPriQueue and LowPriQueue modules are
have been sensed idle, and take messages from the implemented to store messages belonging to different
network according to the corresponding virtual link priorities while waiting for being scheduled.
identification. There are 2 ESPort modules, which are  Scheduler module schedule messages according to high-
ESPort1 and ESPort2 for redundancy management. priority-first policy.
 RxQueue Module is used to store received messages for  ForwardRule module stores forwarding table of messages
integrity check. of all virtual link IDs. The forwarding table is configured
 IntegrityChecker module validates the message integrity directly from the XML configuration file.
and passes only valid messages through the selector  Router module consults with the ForwardRule module to
module. forward messages of different virtual link IDs to
 Selector module is a part of redundancy management to appropriate switch ports to reach the destinations of the
select only one copy of massages which may be received messages accordingly.
twice. The selection policy here is assumed to be first-
B. System Configurations
arrival win policy. The select messages will send to the
upper module. In this section, the simulation of the use case ADFX system
 De-Multiplexer module passes messages of different model has been conducted on OMNeT++ [21] for an
virtual link to the according RxVLQueue module. evaluation of the system performance. There are 3 test
 RxVLQueue module stores messages of each virtual link scenarios in this paper.
and passes them through the appropriate logical port.
 RxLogicalPort module is a logical port defined for each  Synchronized System
virtual link which links messages from the RxVLQueue  Time drift (∆T) is set to 0µs as the system is assumed to
module to the partition module. be synchronized.
 The traffic load is varied from 90% to 100% of the
2) Switch Model network capacity representing by different frame sizes of
There is one switch in the simulation. The architecture of 680 and 760 Bytes. It is noted that the traffic load here
such switch is illustrated in Figure 11. includes all overhead, such as 7-Byte Preamble, 1-Byte
Start Frame Delimiter, and 12-Byte Inter-Frame Space.

 Asynchronized System
 The time drift is randomly introduced on some
transmission slots to represent the asynchronized system.
The time drift will be different and randomized for each
VL. The time drift is generally less than 1µs. For the
worst case evaluation, the time drift is set to 1µs.
Therefore, on each transmission loop either +1µs, 0µs, or
-1µs will be applied for each end system with a
probability of 1/3 each.
 The traffic load is also varied from 90% to 100% of the
network capacity.

 Asynchronized System with 10% of 500µs ES Jitter

Figure 11 Switch Model  The time drift is set to 1µs. Therefore, on each
The switch consists of SWPort, PriorityClassifier, transmission loop either +1µs, 0µs, or -1µs will be
HighPriQueue, LowPriQueue, Scheduler, Router, and applied for each end system with a probability of 1/3
ForwardRule modules. The detail of such modules is given each.
below.  The traffic load is varied from 90% to 100% of the
 SWPort module represents physical ports of each switch network capacity.
which is used to retrieve a message from the  ES jitter of 500µs has also been randomly inserted to each
communication network and forward such message to frame with the rate of 10% of all transmitted frames to
different ports according to its virtual link ID. observe the impact of ES jitter on the communication
performance.
The system performance is evaluated in terms of Bandwidth Allocation Gap 2ms
Maximum Credit of the switch 10 x tx
Number of VLs 32 VLs
 Average Absolute End-to-End Jitter: An average of absolute Communication Link Capacity 100Mbps
values of end-to-end jitter of each virtual link can be
calculated in Equation (3). IV. PERFORMANCE EVALUATION RESULTS AND ANALYSIS
The simulation is conducted according to the pre-defined
Jitter End toEnd  avg( Tete _ i  Tete _ i1 ) use case scenario presented in the previous section. Because
(3) the traffic policy plays a major role on forwarding or dropping
data frames, the value of the maximum credit of the switch of
 Average Reception Rate: Percentage of the number of each VL is crucial and needed to be appropriately calibrated.
successfully received frames by OBC and the total number The following results show the impact of the maximum credit
of all transmitted frames in the system determined in of the switch on the system performance.
Equation (4). A. Impact of the Maximum Credit of the Switch
the number of successfully transmitted frames Figures 12 and 13 show the impact of the maximum credit
Avg _ Re ception _ Rate   100
the total number of transmitted frames of the switch on the system performance in terms of the
(4) average reception rate and the average end-to-end jitter of all
VLs in the system. The results are compared between the
 Average Drop Rate: Percentage of the total number of synchronized and asynchronized systems to observe the impact
frames dropped by the switch due to inadequate account of time drift on the system performance. In this scenario, the
credit for transmission and the total number of all traffic load is set to 90% of the network capacity (680-Byte
transmitted frames in the system shown in Equation (5). The frame).
initial value and the upper limit of the account for VLi (ACi)
by the standard can also be referred to Equation (6).

the number of dropped frames

Avg _ Drop _ Rate   100
the total number of transmitted frames
(5)

 J max 
ACi  Simax 1  i 
 BAG i 

(6)

In addition, as time elapses, ACi is credited with a rate of

Simax.
BAGi
 Maximum Queue Length: The maximum number of frames
waiting in the queue of each switch port. Figure 12 System performance comparisons between the synchronized and
asynchronized systems in term of average reception rate of all VLs
 Average Queue Length: The time average of the number of In Figure 12, the result shows that the synchronized system
frames in the queue of each switch port, which can be achieves the higher reception rate compared to the
determined in Equation (7). asynchronized system. At low value of the maximum credit of
the switch, the reception rate is also low, because there is a
Avg _ queue 
 t  queue _ length 
i i higher chance to discard some arrival frames due to inadequate
 t i account credit. The higher the maximum credit of the switch,
(7) on the other hand, makes the reception rate higher. In the
synchronized system, the reception rate can reach 100% at the
All default parameters in the simulation are summarized in maximum credit of 504µs (9 times the transmission time of
Table II. one frame), while the asynchronized system can achieve 100%
reception rate at the maximum credit of 560µs (10 times the
TABLE II
DEFAULT PARAMETER VALUES IN THE SIMULATION
transmission time of one frame). This value can be explained
Parameters Default Values as follows.
ES scheduler Round Robin On the emulator (EM) which generates 10 frames every
Switch scheduler Round Robin
Switch port scheduler First-In-First-Out
1ms, in the worst case, one frame may be regulated after the
Buffer size 512 frames other 9 frames. Therefore, the maximum ES jitter in this case
Switch processing time 10µs can be up to 9 times the frame transmission time, which is
Traffic Load 90% and 100%
Time drift -1µs, 0µs, and 1µs equal to 504µs. Therefore, the synchronized system requires at
Random ES Jitter 0µs, and 500µs least 504µs as the maximum credit to gain 100% frame
acceptance at the switch. In contrast, the time drift in the ES jitter experiences the lowest reception rate regardless the
asynchronized system causes a time variation in the value of the maximum credit of the switch. The larger ES
transmission, the higher value of the maximum credit is jitter, such as 500µs, causes the larger time variation in the
required, which is 560µs in this case. To avoid unnecessary frame transmission order. Therefore, the inter-arrival time of
frame discarding, the maximum credit of the switch is set to 10 several frames sometimes is too short for the account credit of
times the frame transmission time for the rest of the each VL on the switch to be recovered. As the results, such
simulation. arrival frames have to be discarded by the switch. This results
in the decrease of the average reception rate of the system.

Figure 13 System performance comparisons between the synchronized and

asynchronized systems in term of average end-to-end jitter of all VLs Figure 15 System performance comparisons of the asynchronized systems
with different ES jitters in term of average end-to-end jitter of all VLs
Figure 13 shows the performance comparison between the
synchronized and the asynchronized systems in term of the Figure 15 shows the results in term of the average end-to-
average end-to-end jitter of all VLs. Regardless the value of end jitter as the impact of the ES jitter. It is observed that the
the maximum credit of the switch, the asynchronized system larger ES jitter results in the higher end-to-end jitter. As
experiences larger end-to-end jitter compared to the previously explained, the larger ES jitter causes the larger time
synchronized system, due to the impact of time drift. In variation in the frame transmission order. This also causes the
addition, the larger maximum credit of the switch results in the larger difference in term of the end-to-end delay of two
lower end-to-end jitter in both systems. consecutively received frames of the same VL. Therefore, the
end-to-end jitter becomes larger compared to the other cases.

Figure 14 System performance comparisons of the asynchronized systems

with different ES jitters in term of average reception rate of all VLs Figure 16 System performance comparisons of the synchronized systems with
different traffic loads in term of average reception rate of all VLs
The impact of the ES jitter is also studied in the
asynchronized system with a random insertion of either 250µs Figures 16 and 17 compare the performance of the
or 500µs ES jitter with an average rate of 10% of the total synchronized system with different traffic loads of 90% and
number of transmission frames in the system. The results in 100% of the link capacity in terms of the average reception
terms of the average reception rate and the average end-to-end rate and end-to-end jitter.
jitter of all VLs in the system are shown in Figures 14 and 15, As expected, the higher traffic load (larger frame size)
respectively. makes the reception rate lower especially at the lower value of
In Figure 14, the asynchronized system without ES jitter the maximum credit of the switch. However, by increasing the
gains the highest reception rate, while the system with 500µs
value of the maximum credit, the reception becomes larger and
can reach 100% in both cases as shown in the figure.

Figure 19 Performance evaluations in term of average drop rate of the system

with the total traffic load of 90% of the network capacity
Figure 17 System performance comparisons of the synchronized systems with
different traffic loads in term of average end-to-end jitter of all VLs

The Account Credit of VL31 (AC31)

In term of the average end-to-end jitter, the system with the
higher traffic load causes the larger end-to-end jitter due to the
larger frame size. However, this end-to-end jitter reduces when
the maximum credit increases.
B. Impact of Network Load, Time Drift, and ES Jitter
This section mainly emphasizes on the objectives of this
paper regarding impacts of high network load, loose time Simulation Time (s)
Figure 20 Sample of the account credit of VL31 (AC31) during the first 65ms
synchronization, and unexpected events, which can be of the transmission in the synchronized system
reflected by our proposed parameters; i.e. network load, time
drift, and ES jitter. The detail performance evaluation results
The Account Credit of VL31 (AC31)

as an impact of these parameters are shown as follows.

1) 90% traffic load (680-Byte frame)
This case represents the network with high traffic load of
90% of the network capacity (or 87% data traffic load
excluding all system overhead). The performance evaluation
results in term of the average reception and drop rates of this
heavily-loaded network are shown in Figures 18 and 19,
respectively. It is noted that the maximum credit of the switch Simulation Time (s)
in this case is set to 560µs, which is equal to 10 times of the Figure 21 Sample of the account credit of VL31 (AC31) during the first 65ms
of the transmission in the asynchronized system
frame transmission time as suggested in the previous section.
The Account Credit of VL31 (AC31)

Simulation Time (s)

Figure 22 Sample of the account credit of VL31 (AC31) during the first 65ms
of the transmission in the asynchronized system with 500µs ES jitter

Both the synchronized and asynchronized systems achieve

100% reception rate. When the 500µs ES jitter is randomly
Figure 18 Performance evaluations in term of average reception rate of the inserted into the system, the system experiences some dropped
system with the total traffic load of 90% of the network capacity frames with the maximum drop rate of 1.6% of the total
number of transmission frames. The AFDX traffic policy on
the switch manages frames very well regardless the loose of
time synchronization even in heavily-load network. However,
due to unexpected events such as randomly-inserted 500µs ES
TABLE III
jitter which is huge compared to 1µs time drift in the
PERFORMANCE EVALUATION IN TERM OF QUEUE LENGTH OF THE SYSTEM WITH
asynchronized system, the traffic policy fails to accept all THE TOTAL TRAFFIC LOAD OF 90% OF THE NETWORK CAPACITY
arrival frames at the switch due to inadequate account credit. 680Bytes with Time 680Bytes with Time
The sample of the account credit of VL31 (AC31) during the 680Bytes Drift Drift and ES Jitter
first 65ms of the transmission in the synchronized system, Port Max Average Max Average Max Average
asynchronized system, and asynchronized system with 500µs
0 1 0.00999934 1 0.00831446 1 0.011074355
ES jitter are illustrated in Figures 20 – 22, respectively. It can
be observed that the AC31 is always high enough to accept the 1 1 0.01999848 1 0.017487688 1 0.016842905
next arrival frame in both synchronized and asynchronized
2 1 0.02999742 1 0.026075784 1 0.021923356
systems. In contrast, there is one frame discarded by the switch
at time 53ms in the asynchronized system with 500µs ES jitter. 3 1 0.03999616 1 0.034495723 1 0.028029617
However, the drop rate of the worst case is still less than 1.6%. 4 1 0.049994701 1 0.043243459 1 0.033834786

5 1 0.059993041 1 0.052723937 1 0.040198779

6 1 0.013998236 2 0.035567554 2 0.027063617

7 6 3.972677694 6 3.972459382 6 3.579986591

Figure 23 Performance evaluations in term of average end-to-end jitter of the

system with the total traffic load of 90% of the network capacity

Figure 23 shows the performance evaluation results in term

of the average end-to-end jitter of different simulation
scenarios with the traffic load of 90% of the network capacity.
No end-to-end jitter is observed in the synchronized system. Figure 24 Performance evaluations in term of average reception rate of the
When 1µs time drift is introduced in the asynchronized system, system with the total traffic load of 100% of the network capacity
the end-to-end jitter is observed. Due to the randomly inserted
time drift, the order of transmission frames has been altered,
and hence makes a variation in term of end-to-end delay of all
transmission frames. Therefore, this results in end-to-end jitter.
As expected, the end-to-end jitter is also observed in the
asynchronized system with 500µs ES jitter. Due to the larger
time variation as the result from the ES jitter, the end-to-end
jitter in this case becomes the largest compared to the other
two cases. However, the maximum end-to-end jitter in all
cases of loose time synchronization and unexpected events is
less than 90µs and far less than the recommend end-to-end
jitter in the standard of 500µs.
The performance evaluation in term of the queue length of
different simulation scenarios with the traffic load of 90% is
shown in Table III. Since the transmission time of each frame Figure 25 Performance evaluations in term of average drop rate of the system
is larger than switch processing time (10µs), there is no frame with the total traffic load of 100% of the network capacity
stuck in the input queue of the switch and the maximum queue
length of port 0-6 is always 1 in the synchronized system. 2) 100% traffic load (760-Byte frame)
However, due to time drift and ES jitter, the order of frames This scenario represents the worst case of the heavily-
may be altered and results in a bit larger in term of the loaded network. The traffic load is increased from 90% to
maximum queue length of the port 6 which can be observed in 100% of the network capacity (or from 87% to 97% data
Table III. In addition, the maximum queue length of the switch traffic load excluding all system overhead) to study an impact
output port 7 is equal to 6 frames. The similar trend of the of a fully-loaded network. The performance evaluation results
average queue length can also be observed in Table III. in term of reception and drop rates are shown in Figures 24
and 25. The maximum credit of the switch is increased to The performance evaluation in term of the queue length of
624µs (10 times of the frame transmission time) due to the different simulation scenarios with the traffic load of 100% is
larger frame size of 760 Bytes. also shown in Table IV. The maximum queue length of port 0-
There is no effect of loose time synchronization as both the 6 is always 1 in all systems since the frame transmission time
synchronized and asynchronized systems achieve 100% is larger than switch processing time. The maximum output
reception rate due to the proper calibrating of the maximum queue length is still maintained at 6 frames as in the previous
credit of the switch. In case of unexpected events when the case.
500µs ES jitter is randomly inserted into the system, the
system experiences frame drop rate up to 1.6% of the total V. CONCLUSION
number of transmission frames. Due to the larger ES jitter, the According to the simulation results from the previous
account credit of VLs may not be recovered in time when the chapter, AFDX for space on-board data networks has shown a
new frame arrived at the switch and hence such frame has to promising outcome to provide deterministic communications,
be discarded. which is crucial on satellite and spacecraft communications.
The performance evaluation has been done based on the
impact of different traffic loads, time drifts, and ES jitters. The
performance evaluation results show that the higher traffic
load does not make a significant impact on the system
performance in term of the average reception rate, drop rate
and the average end-to-end jitter if an appropriated value of
the maximum credit of the switch is deployed. For example,
the reception rate can reach 100% in most cases.
The 500µs ES jitter representing unexpected events, in
contrast, can make a small impact on both the average end-to-
end jitter and the average reception rate. Due to a huge time
variation caused by the ES jitter, the switch account credit may
not be recovered fast enough to accept the new arrival frames
and the average end-to-end delay of all frames cannot be
maintained to be constant. For these reasons, it results in the
Figure 26 Performance evaluations in term of average end-to-end jitter of the
system with the total traffic load of 100% of the network capacity larger frame dropping rate and higher average end-to-end
jitter. However, the drop rate is only up to 1.6% even when the
The performance evaluation results in term of the average worst case of the 500µs ES jitter is inserted into the system. In
end-to-end jitter of different simulation scenarios with the addition, the maximum end-to-end jitter experienced by all
traffic load of 100% are shown in Figure 26. The synchronized frames is less than 140µs.
system experiences no end-to-end jitter, while the To get rid of the impact of the 500µs ES jitter on the
asynchronized system with 500µs ES jitter experiences the average reception rate, the larger value of the maximum credit
largest end-to-end jitter. The ES jitter makes the large time on the switch is required. With an implementation of the larger
variation and result in end-to-end jitter compared to the other maximum credit on the AFDX switch, the average end-to-end
systems. The maximum end-to-end jitter in all cases is less delay will be larger as well. This becomes a trade-off between
than 140µs and far less than the recommend end-to-end jitter communication reliability and delay.
in the standard. There are increasing research activities proposed to
investigate further development and application for the future
TABLE IV
space missions. The paper represents an initial activity for the
PERFORMANCE EVALUATION IN TERM OF QUEUE LENGTH OF THE SYSTEM WITH
THE TOTAL TRAFFIC LOAD OF 100% OF THE NETWORK CAPACITY many to follow.
760Bytes with Time 760Bytes with Time
760Bytes Drift Drift and ES Jitter ACKNOWLEDGMENT
Port Max Average Max Average Max Average The authors would like to acknowledge the support from
0 1 0.009999276 1 0.008314406 1 0.018140319
FP7 MISSION, and European Space Agency (ESA) project
within the space programme SatNex III.
1 1 0.019998352 1 0.017487577 1 0.021667653

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CHAKKAPHONG SUTHAPUTCHAKUN member of the « Académie de l'Air et de l'Espace » (ANAE) and author of
([email protected]) received B.Eng. in numerous publications about Aeronautical history in books and specialized
Computer Engineering from King Mongkut’s magazines.
University of Technology Thonburi, Thailand, in 2002.
In 2006, he received his M.Sc. in Electrical and
Computer Engineering from University of