EC258 IV UNIT

Digital DATA FLOW, BEHAVIORAL MODELING

System
Design Using
VHDL
Syllabus for IV Unit:-

Concurrent Signal Assignment – Conditional Signal Assignment - Selected Signal Assignment –

Sequential Statements – Data Flow and Behavioral Modeling
---------------------------------------------------------------------------------------------------------------------

Having Finished Basic Foundations in VHDL, we will go a step further and learn the
main design styles in VHDL. VHDL Supports two main design styles. Both the styles have their
capabilities and will help a designer to describe his own application. The VHDL Code can be
Concurrent (Parallel) or Sequential.

4.1 COMBINATIONAL VS SEQUENTIAL LOGIC

By Definition Combinational Logic is that in which, the output of the circuit solely
depends on the current inputs (Inputs given at the input side). It is clear from the principle that the
system needs no memory and it can be implemented by using conventional Logic gates. In
contrast Sequential Logic is defined as the logic in which the outputs will not only depend on the
present inputs but also past inputs stored in the memory. From this principle we understand that
sequential logic system needs a memory to be used along with conventional logic gates.
Therefore storage elements are required.

Fig 4.1 Combinational Logic Fig 4.2 Sequential Logic

4.2 CONCURRENT VS SEQUENTIAL CODE

VHDL Code is inherently Concurrent (Parallel). Only statements place inside Process,
Functions or Procedures are sequential, though within these blocks execution is sequential, the
block as a whole is concurrent, with any other external statements. A concurrent code is also
called Dataflow Code. A Sequential code is also called Behavioral Code.

A dataflow model specifies the functionality of the entity without explicitly specifying its
structure. This functionality shows the flow of information through the entity, which is expressed
primarily using concurrent signal assignment statements and block statements.

4.3 CONCURRENT SIGNAL ASSIGNMENT STATEMENTS

These statements are used in Dataflow Modeling. There are two types of Concurrent
signal Assignment Statements. They are:

Copyright @ S. Nireekshan Kumar, Lecturer, ECE 1

 EC258 IV UNIT
Digital DATA FLOW, BEHAVIORAL MODELING
System
Design Using
VHDL
1. Conditional Signal Assignment Statements
2. Selected Signal Assignment Statements.

4.3.1 Conditional Signal Assignment Statements

Syntax:

Target _Signal <= <Element> When <Condition> else

<Element> When <Condition> else
……………..
…………….
……………..
<Element> When <Condition>;

Target _Signal <= <Element> When <Condition> or <Value>,

<Element> When <Condition> or <Value>,
……………..
…………….
……………..
<Element> When <Condition> or <Value>,

Examples for Clear Understanding

For Example: Let us consider an Multiplexer in Fig4 .3 and analyze how to write in conditional
signal Assignment Statement

Fig 4.3 4X1 Mux

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 EC258 IV UNIT
Digital DATA FLOW, BEHAVIORAL MODELING
System
Design Using
VHDL
(a) Example for First type of Conditional signal Assignment Statement

(b) Example for Second type of Conditional Signal Assignment Statement

In the above Solution, Sel was given as std_logic, but it can also be configured as Integer. The
following Example will give clear picture of this change

Copyright @ S. Nireekshan Kumar, Lecturer, ECE 3

 EC258 IV UNIT
Digital DATA FLOW, BEHAVIORAL MODELING
System
Design Using
VHDL

4.3.2 Selected Signal Assignment statements

Syntax:

Target_Signal <= Elements when Choices;

Elements when Choices;
…………
…………
…………
Elements when Choices;

For Example: Let us consider a half adder to illustrate Selected Signal Assignment Statements

Library IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

Entity halfadder is

Port (a, b: in std_logic;

Sum, carry: out std_logic);
End halfadder;

Copyright @ S. Nireekshan Kumar, Lecturer, ECE 4

 EC258 IV UNIT
Digital DATA FLOW, BEHAVIORAL MODELING
System
Design Using
VHDL Architecture
Dataflow of halfadder is
Begin
Sum <= a xor b;
Carry<= (a and b);
End;

In Detail Concurrent code can be written in the following Ways:

1. Operators.
2. The When (When/Else or With/Select/When)
3. The Generate Statement *
4. The Block Statement.*

* Not required for UG Level

4.3.3 Concurrent Code using Operators

This is the most basic way of creating concurrent code. Operators (AND, OR, +, -, *, sll, sra,
etc…) can be used to implement any type of Combinational circuit.

For Example: Let us consider Multiplexer in Fig 4.3and understand this Concept

Copyright @ S. Nireekshan Kumar, Lecturer, ECE 5

 EC258 IV UNIT
Digital DATA FLOW, BEHAVIORAL MODELING
System
Design Using
VHDL
4.3.4 Concurrent Code using when (Simple & Selected)

Already Explained in Sec 4.3.2

4.4 SEQUENTIAL STATEMENTS

As mentioned in Concurrent Section VHDL Code is concurrent, Process, Functions and

Procedures are the only sections of code that are executed sequentially. However as a whole any
of these blocks are still concurrent with any other statements placed outside it. One important
aspect of sequential code is that it is not limited to sequential logic. Indeed with it we can build
sequential circuits as well as combinational circuits. Sequential code is also called behavioral
code. The statements discussed in this section are only allowed to be used in Process, Function,
and Procedures. Variables are also restricted to be used in sequential code.

4.4.1 Process

Process is a sequential section of VHDL Code. It is characterized by the presence of if, if else,
Wait, Case, or Loop and by a sensitivity List. A Process must be installed in main code and is
executed every time a signal in sensitivity list changes. Its syntax is given below

Architecture Behavioral of XXX is

begin
Process (Sensitivity List or Clock)
<Variable declaration> {This is optional}
begin
<Sequential Code>
End process
End;

For Example: Let us consider half adder to illustrate Behavioral code for Combinational Ckts

Library IEEE;
USE IEEE.STD_LOGIC_1164.ALL:

Entitiy halfadd is

Port (a, b: in std_logic;

Sum, carry: out std_logic);

End halfadd;

Architecture Behavioral of halfadd is\

<type Declarations> {Optional}

<Signal Declarations> {Optional}

Begin
Process (a,b)
{Variable declarations} {Optional}

Copyright @ S. Nireekshan Kumar, Lecturer, ECE 6

 EC258 IV UNIT
Digital DATA FLOW, BEHAVIORAL MODELING
System
Design Using
VHDL
Begin
<Sequential Code>
End Process;
End;

For Example: Let us take D Flip-flop to Behavioral code for Sequential Circuits

Library IEEE;
USE IEEE.STD_LOGIC_1164.ALL:

Entity dff is

Port (din: in std_logic;

Clk: in std_logic;
Rst: in std_logic;
q: out std_logic);

End dff;

Architecture Behavioral of dff is

<type Declarations> {Optional}

<Signal Declarations> {Optional}

Begin
Process (clk)
{Variable declarations} {Optional}

Begin
<Sequential Code>
End Process;
End;

4.4.2 If Statement

If <Condition> then
<Sequence of Statements>;
End if;

For Example: Let us take only one output of Nand gate

Entity nand1 is

Port (a, b: in std_logic;

Z: out std_logic);

End nand1;

Copyright @ S. Nireekshan Kumar, Lecturer, ECE 7

 EC258 IV UNIT
Digital DATA FLOW, BEHAVIORAL MODELING
System
Design Using
VHDL Architecture Behavioral of nand1 is
Begin
Process (a, b)
Begin
If a=’0’ and b=’0’ then
Z<=1;
End if;
End Process;
End;

4.4.3 If, ElsIf, Else Statements

If <Condition> then
<Sequence of statements>;
Elsif
<Sequence of statements>;
Else
<Sequence of statements>;

End if;

For Example: Let us consider up-down counter.

Entity counter1 is

Port (Clk, Rst, mode: in std_logic;

Count: inout std_logic_vector (2 dowto 0));

End counter1;

Architecture Behavioral of counter1 is

Begin
Process (Clk)
Begin

If Rst=’0’ then
Count<=”000”;

Elsif Clk’event and Clk= ‘1’ then

If mode =’0’ then

Count<=count+1;
Else
Count<=count-1;
End if;
End if;
End Process;
End;

Copyright @ S. Nireekshan Kumar, Lecturer, ECE 8

 EC258 IV UNIT
Digital DATA FLOW, BEHAVIORAL MODELING
System
Design Using
VHDL

4.4.4 Case Statements

Case is another fragment of sequential code along with If, Wait, Loop etc…

Case <Expression/Identifier> is
When <Choice/Value> => Sequence of statements;
When <Choice/Value> => Sequence of statements;
When <Choice/Value> => Sequence of statements;
…………..
………….
When others => <Sequence of Statements>;
End case

For Example: Let us consider Multiplexer

Entity multiplexer is

Port (in1: in std_logic_vector (3 downto 0);

Sel: in std_logic_vector (1 downto 0);
Z: out std_logic);

End multiplexer;

Architecture Behavioral of multiplexer is

Begin
Process (in1, Sel)
Begin

Case Sel is
When “00” => Z <= in1(0);
When “01” => Z <= in1(1);
When “10” => Z <= in1(2);
When “11” => Z <= in1(3);

End case;
End Process;
End;

4.4.5 Wait Statement

The operation of Wait is sometimes is similar to If. However more that one form of wait
is available

4.4.5.1 Wait on Sensitivity List

Wait on signal1, signal2,………

Ex: Wait on a,b;

Copyright @ S. Nireekshan Kumar, Lecturer, ECE 9
 EC258 IV UNIT
Digital DATA FLOW, BEHAVIORAL MODELING
System
Design Using
VHDL

4.4.5.2 Wait until Boolean expression

Wait until Signal_Condition;

Ex: Wait until a=b;

4.4.5.3 Wait for Time

Wait for Time;

Ex Wait for 10ns;

For Example: Let us consider the following

Process (Sensitivity List)

Begin

If a > b then
Q<=’1’;

Else
Q<=’0’;

End if;

Wait on a,b;

End if;
End process;

4.4.6 Loop Statements

As the name says, Loop is useful when a piece of code must be instantiated several times.
Like If, Wait and case. Loop is intended exclusively for Sequential Code. So it too can only be
used inside a process, Function or procedure. There are several ways of using Loop as shown
below.

4.4.6.1 For/Loop:

[Loop_Label] : For <Identifier> in <Discrete range> loop

<Sequential Statements>;
End Loop [Label];

Copyright @ S. Nireekshan Kumar, Lecturer, ECE 10

 EC258 IV UNIT
Digital DATA FLOW, BEHAVIORAL MODELING
System
Design Using
VHDL
For Example:

4.4.6.2 While / Loop

[Loop_Label] : While <Condition> Loop

<Sequential Statements>;
End Loop [Label];

For Example

4.4.6.3 Exit

[Label] : Exit [Label] [When Condition];

For Example

4.4.6.4 Next

[Label] : Next [Loop_Label] [When Condition];

For Example

Copyright @ S. Nireekshan Kumar, Lecturer, ECE 11

 EC258 IV UNIT
Digital DATA FLOW, BEHAVIORAL MODELING
System
Design Using
VHDL

4.5 SUBPROGRAM

Subprograms consist of procedures and functions used to perform common operations.

Packages are mechanisms that allow sharing data among entities. Subprograms, types, and
component declarations are the tools to build designs with, and packages are the toolboxes.

There are two kinds of subprograms:

1. Functions: These are usually used for computing a single value.
2. Procedures: These are used to partition large behavioral descriptions. Procedures can
return zero or more values

1. Subprograms consist of procedures and functions.

2. Subprograms can be defined in 3 places
a. Package
b. Architecture
c. Process.
3. When we call the subprogram more than one time, we call them in Package.
4. Subprogram will have only sequential statements.
5. Wait statements cannot be used in Functions.
6. We cannot write a process in a subprogram.
7. Inside subprogram only variables are allowed.
8. No concurrent statements are allowed in sub program

4.5.1 Function

Functions are used to describe frequently used sequential algorithms that return a single
value. This value is returned to the calling program using a return statement. Some of their
common uses are as resolution functions, and as type conversion functions.

1. Function cannot change argument.

2. Parameter type should be constant or Signal.
3. Default type is constant.
4. Mode should be in only.

A Package using Function will have three constructs in the the code. They are described in
following Syntax:

1. Package Declaration:

Library IEEE;
USE IEEE.STD_LOGIC_1164.ALL:
Library Work;

Package <Package_Name> is

Function <function_Name> (Sensitivity List…….)

Return type;
……….

Copyright @ S. Nireekshan Kumar, Lecturer, ECE 12

 EC258 IV UNIT
Digital DATA FLOW, BEHAVIORAL MODELING
System
Design Using
VHDL ……….
Function <Function_Name> (Sensitivity List……)
Return type;

End <Package_Name>;

2. Package Body

Package body <Package_Name> is

Function <function_Name> (Sensitivity List…….)

Return type is
<Sequence of Statements>;
End <Function_Name>;
……….
……….
Function <Function_Name> (Sensitivity List……)
Return type is
<Sequence of Statements>;
End <Function_Name>;

End <Package_Name>;

3. Entity / Architecture

Library IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE Work.<Package_Name>.all;

Entity <Entity_Name> is

Port(Sensitivity List); {Names of this Sensitivity List should differ the Package sensitivity Names
and should specify all the functions sensitivity List Names without fail}

End <Entity_Name>;

Architecture Behavioral of <Entity_Name> is

Begin
Process (Sensitivity List / Clock)

Begin
<Sequence of Statements>;
Function_Name (Call Package Sensitivity List);
End process;
End;

Copyright @ S. Nireekshan Kumar, Lecturer, ECE 13

 EC258 IV UNIT
Digital DATA FLOW, BEHAVIORAL MODELING
System
Design Using
VHDL
For Example: Let us consider Multiplexer and illustrate the operation in Function Package

Library IEEE;
Use IEEE.STD_LOGIC_1164.ALL;
Use IEEE.STD_LOGIC_ARITH.ALL;
Use IEEE.STD_LOGIC_UNSIGNED.ALL;
Library Work;
------------------------------------------------------------------------------------------------------------
---------
Package Declaration
Package mux_f is

Function con (a, b, c, d: in std_logic;

Sel: in std_logic_vector)
Return std_logic;

End mux_f;
------------------------------------------------------------------------------------------------------------
---------
Package Body
Package body mux_f is

Function con (a, b, c, d: in std_logic;

sel: in std_logic_vector)

Return std_logic is

Begin
if sel="00" then
Return a;
Elsif sel="01" then
Return b;
Elsif sel="10" then
Return c;
Elsif sel="11" then
Return d;

End if;
End con;
End mux_f;
------------------------------------------------------------------------------------------------------------
---------
Entity / Architecture
Library IEEE;
Use IEEE.STD_LOGIC_1164.ALL;

Copyright @ S. Nireekshan Kumar, Lecturer, ECE 14

 EC258 IV UNIT
Digital DATA FLOW, BEHAVIORAL MODELING
System
Design Using
VHDL Use
IEEE.STD_LOGIC_ARITH.ALL;
Use IEEE.STD_LOGIC_UNSIGNED.ALL;
Use WORK.mux_f.ALL;

Entity mux2 is
Port (p, q, r, s: in std_logic;
t: in std_logic_vector;
z: out std_logic);
End mux2;

Architecture Behavioral of mux2 is

Begin
z<=con (p, q, s, t);
End Behavioral;

4.5.2 Procedure

Procedures allow decomposition of large behaviors into modular sections. In contrast to a

function, a procedure can return zero or more values using parameters of mode out and inout.
Procedure will also contain Three Sections like as in Functions. The following is the syntax

1. Package Declaration

Library IEEE;
USE IEEE.STD_LOGIC_1164.ALL:
Library Work;

Package <Package_Name> is

Procedure <Procedure_Name> (Sensitivity List…….);

……….
……….
Procedure <Procedure_Name> (Sensitivity List…….);

End <Package_Name>;

2. Package Body

Package body <Package_Name> is

Procedure <Procedure_Name> (Sensitivity List…….) is

<Sequence of Statements>;
End <Procedure_Name>;
……….
……….
Procedure <Procedure_Name> (Sensitivity List…….) is
<Sequence of Statements>;
End <Procedure_Name>;

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 EC258 IV UNIT
Digital DATA FLOW, BEHAVIORAL MODELING
System
Design Using
VHDL
End <Package_Name>

3. Entity / Architecture

Library IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE Work.<Package_Name>.all;

Entity <Entity_Name> is

Port (Sensitivity List); {Names of this Sensitivity List should differ the Package sensitivity
Names and should specify all the functions sensitivity List Names without fail}

End <Entity_Name>;

Architecture Behavioral of <Entity_Name> is

Begin
Process (Sensitivity List / Clock)

Begin
<Sequence of Statements>;
Procedure_Name (Call Package Sensitivity List);
End process;
End;

For Example: Let us Consider an ALU and illustrate this Procedure Call

Library IEEE;
Use IEEE.STD_LOGIC_1164.ALL;
Use IEEE.STD_LOGIC_ARITH.ALL;
Use IEEE.STD_LOGIC_UNSIGNED.ALL;
Library Work;
------------------------------------------------------------------------------------------------------------
Package Declaration
Package Alu_p is

Procedure Arithemetic (a, b: in std_logic

Sel: in std_logic_vector);

Procedure Logical (,b:in

End mux_f;
------------------------------------------------------------------------------------------------------------
Package Body
Package body mux_f is

Copyright @ S. Nireekshan Kumar, Lecturer, ECE 16

 EC258 IV UNIT
Digital DATA FLOW, BEHAVIORAL MODELING
System
Design Using
VHDL Function con (a, b, c, d: in std_logic;
sel: in std_logic_vector)

Return std_logic is

Begin
if sel="00" then
Return a;
Elsif sel="01" then
Return b;
Elsif sel="10" then
Return c;
Elsif sel="11" then
Return d;

End if;
End con;
End mux_f;
------------------------------------------------------------------------------------------------------------
Entity / Architecture
Library IEEE;
Use IEEE.STD_LOGIC_1164.ALL;
Use IEEE.STD_LOGIC_ARITH.ALL;
Use IEEE.STD_LOGIC_UNSIGNED.ALL;
Use WORK.mux_f.ALL;

Entity mux2 is
Port (p, q, r, s: in std_logic;
t: in std_logic_vector;
z: out std_logic);
End mux2;

Architecture Behavioral of mux2 is

Begin
z<=con (p, q, s, t);

Copyright @ S. Nireekshan Kumar, Lecturer, ECE 17