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DIGITAL LOGIC DESIGN

Ivan Marsic, Rutgers University
Electrical & Computer Engineering
Fall 2013
Lecture #24: Verilog Time Dimension and Test Benches

Verilog Functions and Tasks

[ behavioral style ]

 Verilog function accepts several inputs and returns a

single result module VrSillierXOR ( ... );
module VrSillierXOR ( ... );
port-declarations
function result-type function-name ; port-declarations
function Inhibit ;
function Inhibit ;
input declarations input In, invIn;
input In, invIn;
Inhibit = In & ~invIn;
variable declarations Inhibit = In & ~invIn;
endfunction
endfunction
parameter declarations always @ (in1 or in2)
always @ (in1 or in2)
begin
begin
inh1 = Inhibit (in1, in2);
procedural-statement inh1 = Inhibit (in1, in2);
...
...
endfunction end
end

 Verilog task is similar to a function, except it does not

return a result
 Built-in system tasks and functions:
– $display = prints formatted signal values to “standard output”
(similar to C printf function)
– $write = similar to $display, but no newline char at end
– $monitor = similar to $display, but remain active continuously
and prints the listed signals whenever any one changes
– $time = returns current simulated time
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 Abstract Model Functionality
[ behavioral style ]

 Abstract functionality is
represented using
procedures module FullAdder(input wire a,
input wire b,
 Begin with the keywords input wire ci,
initial or always output reg sum, co);
– An initial procedure
will execute once, initial
beginning at simulated begin
time zero sum = 0;
co = 0;
– always procedures
end
model the continuous
operation of hardware
always @(a or b or ci)
 Procedures contain begin
programming {co, sum} = a + b + ci;
statements end
endmodule
 Multiple statements are
grouped with begin
and end
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Procedural Block Activation

 All concurrent statements (procedures) automatically
become active at time zero
Time 0

initial initial always @(a or b) always @(posedge clk)

initial initial always @(a or b) always @(posedge clk)
begin begin begin begin
begin begin begin begin
a = 0; sum = 0; sum = a + b; q <= sum;
a = 0; sum = 0; sum = a + b; q <= sum;
b = 0; end end end
b = 0; end end end
#10 a = 1;
#10 a = 1;
...
...
end
end

 Note: Verilog procedures are not like software

subroutines, which must be called in order to be activated
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 Verilog Time Scale
[ Verilog time dimension ]

 Default time scale is 1 ps (picoseconds), but can

be changed using the `timescale compiler
directive
`timescale time-unit / time-precision
– Example:
`timescale 1 ns / 100 ps
module Vrprimedly (N, F);
... // Wakerly, Table 5-97, page 330
assign #2 N3L_No = ~N[3];
2 ns delay for the assign statement’s operation
 In procedural blocks of code, delays specified by
writing # symbol and a delay number:
– At the start of an always block (seen in the next slide)
– After the = or <= symbol in a procedural assignment
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Controlling Verilog Procedures

[ Verilog time dimension ]

 initial and always procedures may contain 3 types of timing:

1. Time based delays — the # token
– Delays execution of the next statement for a specific amount of time
always // delayed for 2 simulation time units
#2 sum = a + b;
2. Edge sensitive delays — the @ token
– Delays execution of the next statement until a change occurs on a signal
always // delayed until positive edge of clock
@(posedge clock) sum <= a + b;
3. Level sensitive delays — the wait keyword
– Delays execution of the next statement until a logic test evaluates as TRUE
always // delayed until 'enable' becomes '1'
wait (enable == 1) sum = a + b;
 Each time control delays execution of the next statement or statement
group

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 Verilog Test Benches
 Unit under test (UUT) = the entity/module being tested
– Also called Device under test (DUT)
 Verilog Test Bench consists of:
– UUT
– UUT stimulus, to provide inputs to the UUT
– UUT monitor, to capture and analyze the UUT output

Verilog Test Bench

UUT Verilog UUT

Stimulus UUT Monitor
inputs outputs

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Example Verilog Test Bench (1)

select
 Unit under test: mux2 in0 0
(described in Lecture #23) in1 1
out

/* 2-input multiplexor test bench #1 */ /* 2-input multiplexor in gates */

module mux2 (in0, in1, select, out);
`timescale 1 ns / 100 ps input in0,in1,select;
module mux2_tb1 ( ); output out;
wire s0,w0,w1;
wire m_out; not (s0, select);
reg m_sel, m_in0, m_in1; and (w0, s0, in0),
(w1, select, in1);
or (out, w0, w1);
mux2 m2_uut (m_in0, m_in1, m_sel, m_out); endmodule // mux2

initial begin Two concurrent statements:

m_in0 = 1'b0;  Instance statement
m_in1 = 1'b0;  initial procedure
m_sel = 1'b0;
Both automatically become
$display ("time: %d, output: %d", $time, m_out); active at time zero
#5 // wait 5 ns before continuing
m_in0 = 1'b1; The initial procedure
m_sel = 1'b1; changes the input
$display ("time: %d, output: %d", $time, m_out); values for UUT as it
$finish; // task call ends simulation runs continuously
end Note blocking assignments
endmodule // mux2_tb1
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 Example Verilog Test Bench (2)
select

 Generating Test Vectors in0 0

out
in1 1

/* 2-input multiplexor test bench #2 */ /* 2-input multiplexor in gates */

module mux2 (in0, in1, select, out);
`timescale 1 ns / 100 ps input in0,in1,select;
module mux2_tb2 ( ); output out;
wire m_out; wire s0,w0,w1;
not (s0, select);
reg [2:0] test_vectors; // 3-bit wide test vector and (w0, s0, in0),
integer i; (w1, select, in1);
or (out, w0, w1);
endmodule // mux2
mux2 m2_uut (.in0(test_vectors[2]), .in1(test_vectors[1]),
.select(test_vectors[0]), .out(m_out) );  Now, all the data is
stored in “test_vectors.”
initial begin // initialize all variables  The most significant
test_vectors = 3'b000; bit, is assigned to “in0”,
end the next to “in1” and
the last to “select”.
initial begin  In the second
for (i=0; i<7; i=i+1) begin initial block, we
#5 // wait 5 ns before continuing generate all the test
test_vectors = test_vectors + 1; vectors, 000 through
$display ("time: %d, output: %d", $time, m_out); 111, in a for loop.
end  Note that the #5 waits
end 5 ns before going to
endmodule // mux2_tb2 the next test vector.
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Self-Checking Test Bench

 SystemVerilog assert statement checks if specified condition is true;
if not, it executes the else statement
 The $error system task prints and error message describing the assertion failure
/* 2-input multiplexor test bench #3 */
`timescale 1 ns / 100 ps
module mux2_tb3 ( );
wire m_out;
reg m_sel, m_in0, m_in1;

mux2 m2_uut (m_in0, m_in1, m_sel, m_out);

initial begin
m_in0 = 1'b0;
m_in1 = 1'b0;
m_sel = 1'b0;
assert ( m_out === 0 ) else $error("000 failed");
#5 // wait 5 ns
m_in0 = 1'b1;
m_sel = 1'b1; // selects m_in1, which is 1'b0
assert ( m_out === 0 ) else $error("101 failed");
$finish;
end
endmodule // mux2_tb3
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