PRELIMINARY

Am29F800BT/Am29F800BB
8 Megabit (1 M x 8-Bit/512 K x 16-Bit)
CMOS 5.0 Volt-only Sector Erase Flash Memory

DISTINCTIVE CHARACTERISTICS
■ Single power supply operation ■ Top or bottom boot block configurations
— 5.0 Volt-only operation for read, erase, and available
program operations ■ Embedded Algorithms
— Minimizes system level requirements — Embedded Erase algorithm automatically
■ Manufactured on 0.35 µm process technology preprograms and erases the entire chip or any
combination of designated sectors
— Compatible with 0.5 µm Am29F800 device
— Embedded Program algorithm automatically
■ High performance writes and verifies data at specified addresses
— Access times as fast as 55 ns
■ Minimum 100,000 write cycle guarantee per
■ Low power consumption (typical values at 5 sector
MHz) ■ Package option
— 1 µA standby mode current — 48-pin TSOP
— 20 mA read current in byte mode — 44-pin SO
— 28 mA read current in word mode
■ Compatibility with JEDEC standards
— 30 mA program/erase current
— Pinout and software compatible with single-
■ Flexible sector architecture power supply Flash
— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and — Superior inadvertent write protection
fifteen 64 Kbyte sectors (byte mode)
■ Data# Polling and toggle bits
— One 8 Kword, two 4 Kword, one 16 Kword, and
— Provides a software method of detecting
fifteen 32 Kword sectors (word mode)
program or erase operation completion
— Supports full chip erase
■ Ready/Busy# pin (RY/BY#)
— Sector Protection features:
— Provides a hardware method of detecting
A hardware method of locking a sector to
program or erase cycle completion
prevent any program or erase operations within
that sector ■ Erase Suspend/Erase Resume
Sectors can be locked via programming — Suspends an erase operation to read data from,
equipment or program data to, a sector that is not being
Temporary Sector Unprotect feature allows erased, then resumes the erase operation
code changes in previously locked sectors ■ Hardware reset pin (RESET#)
— Hardware method to reset the device to reading
array data

This document contains information on a product under development at Advanced Micro Devices. The information Publication# 21504 Rev: B Amendment/0
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed Issue Date: October 1997
product without notice.
 PRELIMINARY

GENERAL DESCRIPTION
The Am29F800B is an 8 Mbit, 5.0 volt-only Flash data contents of other sectors. The device is fully
memory organized as 1,048,576 bytes or 524,288 erased when shipped from the factory.
words. The device is offered in 44-pin SO and 48-pin
Hardware data protection measures include a low
TSOP packages. The word-wide data (x16) appears on
VCC detector that automatically inhibits write opera-
DQ15–DQ0; the byte-wide (x8) data appears on DQ7–
tions during power transitions. The hardware sector
DQ0. This device is designed to be programmed in-
protection feature disables both program and erase
system with the standard system 5.0 volt VCC supply.
operations in any combination of the sectors of mem-
A 12.0 V VPP is not required for write or erase opera-
ory. This can be achieved via programming equipment.
tions. The device can also be programmed in standard
EPROM programmers. The Erase Suspend feature enables the user to put
erase on hold for any period of time to read data from,
This device is manufactured using AMD’s 0.35 µm
or program data to, any sector that is not selected for
process technology, and offers all the features and
erasure. True background erase can thus be achieved.
benefits of the Am29F800, which was manufactured
using 0.5 µm process technology. The hardware RESET# pin terminates any operation
in progress and resets the internal state machine to
The standard device offers access times of 55, 70, 90,
reading array data. The RESET# pin may be tied to the
120, and 150 ns, allowing high speed microprocessors
system reset circuitry. A system reset would thus also
to operate without wait states. To eliminate bus conten-
reset the device, enabling the system microprocessor
tion the device has separate chip enable (CE#), write
to read the boot-up firmware from the Flash memory.
enable (WE#) and output enable (OE#) controls.
The system can place the device into the standby
The device requires only a single 5.0 volt power sup-
mode. Power consumption is greatly reduced in
ply for both read and write functions. Internally gener-
ated and regulated voltages are provided for the this mode.
program and erase operations. AMD’s Flash technology combines years of Flash
The device is entirely command set compatible with the memory manufacturing experience to produce the
JEDEC single-power-supply Flash standard. Com- h i g h e s t l e v e l s o f q u a l i ty , r e l i a b i l i t y a n d c o s t
mands are written to the command register using effectiveness. The device electrically erases all
standard microprocessor write timings. Register con- bits within a sector simultaneously via
tents serve as input to an internal state-machine that F o w l e r -N o r d h e i m t u n n e l i n g . T h e d a t a i s
controls the erase and programming circuitry. Write programmed using hot electron injection.
cycles also internally latch addresses and data needed
for the programming and erase operations. Reading
data out of the device is similar to reading from other
Flash or EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithm—an internal algorithm that auto-
matically times the program pulse widths and verifies
proper cell margin.
Device erasure occurs by executing the erase com-
mand sequence. This initiates the Embedded Erase
algorithm—an internal algorithm that automatically pre-
programs the array (if it is not already programmed) be-
fore executing the erase operation. During erase, the
device automatically times the erase pulse widths and
verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, or by reading the DQ7 (Data# Polling) and DQ6
(toggle) status bits. After a program or erase cycle
has been completed, the device is ready to read array
data or accept another command.
The sector erase architecture allows memory sectors
to be erased and reprogrammed without affecting the

2 Am29F800BT/Am29F800BB
 PRELIMINARY

PRODUCT SELECTOR GUIDE

Family Part Number Am29F800B

Ordering Part Number: VCC = 5.0 V ± 5% -55

VCC = 5.0 V ± 10% -70 -90 -120 -150

Max access time, ns (tACC) 55 70 90 120 150

Max CE# access time, ns (tCE) 55 70 90 120 150

Max OE# access time, ns (tOE) 30 30 35 50 55

Note:
See “AC Characteristics” for full specifications.

BLOCK DIAGRAM
RY/BY# DQ0–DQ15 (A-1)
VCC
Sector Switches
VSS
Erase Voltage Input/Output
RESET# Generator Buffers

WE# State
Control
BYTE#
Command
Register PGM Voltage
Generator
Chip Enable Data
Output Enable STB Latch
CE#
OE# Logic

Y-Decoder Y-Gating
STB
Address Latch

VCC Detector Timer

X-Decoder Cell Matrix

A0–A18

21504B-1

Am29F800BT/Am29F800BB 3
 PRELIMINARY

CONNECTION DIAGRAMS

A15 1 48 A16
A14 2 47 BYTE#
A13 3 46 VSS
A12 4 45 DQ15/A-1
A11 5 44 DQ7
A10 6 43 DQ14
A9 7 42 DQ6
A8 8 41 DQ13
NC 9 40 DQ5
NC 10 39 DQ12
WE# 11 38 DQ4
RESET# 12 37 VCC
NC 13 36 DQ11
NC 14 35 DQ3
RY/BY# 15 34 DQ10
A18 16 33 DQ2
A17 17 32 DQ9
A7 18 31 DQ1
A6 19 30 DQ8
A5 20 29 DQ0
A4 21 28 OE#
A3 22 27 VSS
A2 23 26 CE#
A1 24 25 A0

48-Pin TSOP—Standard Pinout

A16 1 48 A15
BYTE# 2 47 A14
VSS 3 46 A13
DQ15/A-1 4 45 A12
DQ7 5 44 A11
DQ14 6 43 A10
DQ6 7 42 A9
DQ13 8 41 A8
DQ5 9 40 NC
DQ12 10 39 NC
DQ4 11 38 WE#
VCC 12 37 RESET#
DQ11 13 36 NC
DQ3 14 35 NC
DQ10 15 34 RY/BY#
DQ2 16 33 A18
DQ9 17 32 A17
DQ1 18 31 A7
DQ8 19 30 A6
DQ0 20 29 A5
OE# 21 28 A4
VSS 22 27 A3
CE# 23 26 A2
A0 24 25 A1

48-Pin TSOP—Reverse Pinout

21504B-2

4 Am29F800BT/Am29F800BB
 PRELIMINARY

CONNECTION DIAGRAMS
SO

RY/BY# 1 44 RESET#
A18 2 43 WE#
A17 3 42 A8
A7 4 41 A9
A6 5 40 A10
A5 6 39 A11
A4 7 38 A12
A3 8 37 A13
A2 9 36 A14
A1 10 35 A15
A0 11 34 A16
CE# 12 33 BYTE#
VSS 13 32 VSS
OE# 14 31 DQ15/A-1
DQ0 15 30 DQ7
DQ8 16 29 DQ14
DQ1 17 28 DQ6
DQ9 18 27 DQ13
DQ2 19 26 DQ5
DQ10 20 25 DQ12
DQ3 21 24 DQ4
DQ11 22 23 VCC

21504B-3

PIN CONFIGURATION LOGIC SYMBOL

A0–A18 = 19 addresses
19
DQ0–DQ14 = 15 data inputs/outputs A0–A18 16 or 8
DQ15/A-1 = DQ15 (data input/output, word mode), DQ0–DQ15
A-1 (LSB address input, byte mode) (A-1)

BYTE# = Selects 8-bit or 16-bit mode

CE#
CE# = Chip enable OE#
OE# = Output enable
WE#
WE# = Write enable RESET#
RESET# = Hardware reset pin, active low BYTE# RY/BY#
RY/BY# = Ready/Busy# output
VCC = +5.0 V single power supply
(see Product Selector Guide for
device speed ratings and voltage 21504B-4
supply tolerances)
VSS = Device ground
NC = Pin not connected internally

Am29F800BT/Am29F800BB 5
 PRELIMINARY

ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is
formed by a combination of the elements below.

Am29F800B T -70 E C

OPTIONAL PROCESSING
Blank = Standard Processing
B = Burn-in
TEMPERATURE RANGE
C = Commercial (0°C to +70°C)
I = Industrial (–40°C to +85°C)
E = Extended (–55°C to +125°C)

PACKAGE TYPE
E = 48-Pin Thin Small Outline Package (TSOP)
Standard Pinout (TS 048)
F = 48-Pin Thin Small Outline Package (TSOP)
Reverse Pinout (TSR048)
S = 44-Pin Small Outline Package (SO 044)

SPEED OPTION
See Product Selector Guide and Valid Combinations

BOOT CODE SECTOR ARCHITECTURE

T = Top Sector
B = Bottom Sector

DEVICE NUMBER/DESCRIPTION
Am29F800B
8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS Flash Memory
5.0 Volt-only Read, Program, and Erase

Valid Combinations Valid Combinations

Valid Combinations list configurations planned to be sup-
Am29F800BT-55, ported in volume for this device. Consult the local AMD sales
EC, EI, FC, FI, SC, SI
Am29F800BB-55 office to confirm availability of specific valid combinations and
Am29F800BT-70, to check on newly released combinations.
Am29F800BB-70

Am29F800BT-90,
Am29F800BB-90 EC, EI, EE, EEB,
FC, FI, FE, FEB,
Am29F800BT-120, SC, SI, SE, SEB
Am29F800BB-120

Am29F800BT-150,
Am29F800BB-150

6 Am29F800BT/Am29F800BB
 PRELIMINARY

DEVICE BUS OPERATIONS

This section describes the requirements and use of the the register serve as inputs to the internal state ma-
device bus operations, which are initiated through the chine. The state machine outputs dictate the function of
internal command register. The command register it- the device. Table 1 lists the device bus operations, the
self does not occupy any addressable memory loca- inputs and control levels they require, and the resulting
tion. The register is composed of latches that store the output. The following subsections describe each of
commands, along with the address and data informa- these operations in further detail.
tion needed to execute the command. The contents of

Table 1. Am29F800B Device Bus Operations

DQ8–DQ15
BYTE# BYTE#
Operation CE# OE# WE# RESET# A0–A18 DQ0–DQ7 = VIH = VIL
Read L L H H AIN DOUT DOUT High-Z
Write L H L H AIN DIN DIN High-Z
CMOS Standby VCC ± 0.5 V X X VCC ± 0.5 V X High-Z High-Z High-Z
TTL Standby H X X H X High-Z High-Z High-Z
Output Disable L H H H X High-Z High-Z High-Z
Reset X X X L X High-Z High-Z High-Z
Temporary Sector Unprotect
X X X VID AIN DIN DIN X
(See Note)

Legend:
L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 ± 0.5 V, X = Don’t Care, DIN = Data In, DOUT = Data Out, AIN = Address In
Note:
See the sections on Sector Protection and Temporary Sector Unprotect for more information.

Word/Byte Configuration
The BYTE# pin controls whether the device data I/O array data. Standard microprocessor read cycles that
pins DQ15–DQ0 operate in the byte or word configura- assert valid addresses on the device address inputs
tion. If the BYTE# pin is set at logic ‘1’, the device is in produce valid data on the device data outputs. The
word configuration, DQ15–DQ0 are active and control- device remains enabled for read access until the
led by CE# and OE#. command register contents are altered.
If the BYTE# pin is set at logic ‘0’, the device is in byte See “Reading Array Data” for more information. Refer
configuration, and only data I/O pins DQ0–DQ7 are ac- to the AC Read Operations table for timing specifica-
tive and controlled by CE# and OE#. The data I/O pins tions and to Figure 9 for the timing diagram. ICC1 in the
DQ8–DQ14 are tri-stated, and the DQ15 pin is used as DC Characteristics table represents the active current
an input for the LSB (A-1) address function. specification for reading array data.

Requirements for Reading Array Data Writing Commands/Command Sequences

To read array data from the outputs, the system must To write a command or command sequence (which in-
drive the CE# and OE# pins to VIL. CE# is the power cludes programming data to the device and erasing
control and selects the device. OE# is the output control sectors of memory), the system must drive WE# and
and gates array data to the output pins. WE# should re- CE# to VIL, and OE# to VIH.
main at VIH. The BYTE# pin determines whether the de-
For program operations, the BYTE# pin determines
vice outputs array data in words or bytes.
whether the device accepts program data in bytes
The internal state machine is set for reading array or words. Refer to “Word/Byte Configuration” for
data upon device power-up, or after a hardware re- more information.
set. This ensures that no spurious alteration of the
An erase operation can erase one sector, multiple sec-
memory content occurs during the power transition.
tors, or the entire device. Tables 2 and 3 indicate the
No command is necessary in this mode to obtain
address space that each sector occupies. A “sector ad-

Am29F800BT/Am29F800BB 7
 PRELIMINARY

dress” consists of the address bits required to uniquely ICC3 in the DC Characteristics table represents the
select a sector. The “Command Definitions” section standby current specification.
has details on erasing a sector or the entire chip, or
suspending/resuming the erase operation. RESET#: Hardware Reset Pin
After the system writes the autoselect command se- The RESET# pin provides a hardware method of reset-
quence, the device enters the autoselect mode. The ting the device to reading array data. When the RE-
system can then read autoselect codes from the inter- SET# pin is driven low for at least a period of tRP, the
nal register (which is separate from the memory array) device immediately terminates any operation in
on DQ7–DQ0. Standard read cycle timings apply in this progress, tristates all output pins, and ignores all
mode. Refer to the Autoselect Mode and Autoselect read/write commands for the duration of the RESET#
Command Sequence sections for more information. pulse. The device also resets the internal state ma-
chine to reading array data. The operation that was in-
ICC2 in the DC Characteristics table represents the ac- terrupted should be reinitiated once the device is ready
tive current specification for the write mode. The “AC to accept another command sequence, to ensure data
Characteristics” section contains timing specification integrity.
tables and timing diagrams for write operations.
Current is reduced for the duration of the RESET#
Program and Erase Operation Status pulse. When RESET# is held at VIL, the device enters
the TTL standby mode; if RESET# is held at VSS±0.5
During an erase or program operation, the system may
V, the device enters the CMOS standby mode.
check the status of the operation by reading the status
bits on DQ7–DQ0. Standard read cycle timings and ICC The RESET# pin may be tied to the system reset cir-
read specifications apply. Refer to “Write Operation cuitry. A system reset would thus also reset the Flash
Status” for more information, and to “AC Characteris- memory, enabling the system to read the boot-up
tics” for timing diagrams. firmware from the Flash memory.
If RESET# is asserted during a program or erase oper-
Standby Mode
ation, the RY/BY# pin remains a “0” (busy) until the in-
When the system is not reading or writing to the device, ternal reset operation is complete, which requires a
it can place the device in the standby mode. In this time of tREADY (during Embedded Algorithms). The
mode, current consumption is greatly reduced, and the system can thus monitor RY/BY# to determine whether
outputs are placed in the high impedance state, inde- the reset operation is complete. If RESET# is asserted
pendent of the OE# input. when a program or erase operation is not executing
The device enters the CMOS standby mode when the (RY/BY# pin is “1”), the reset operation is completed
CE# and RESET# pins are both held at VCC ± 0.5 V. within a time of tREADY (not during Embedded Algo-
(Note that this is a more restricted voltage range than rithms). The system can read data tRH after the RE-
VIH.) The device enters the TTL standby mode when SET# pin returns to VIH.
CE# and RESET# pins are both held at VIH. The device Refer to the AC Characteristics tables for RESET# pa-
requires standard access time (tCE) for read access rameters and to Figure 10 for the timing diagram.
when the device is in either of these standby modes,
before it is ready to read data. Output Disable Mode
The device also enters the standby mode when the When the OE# input is at VIH, output from the device is
RESET# pin is driven low. Refer to the next section, disabled. The output pins are placed in the high imped-
“RESET#: Hardware Reset Pin”. ance state.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.

8 Am29F800BT/Am29F800BB
 PRELIMINARY

Table 2. Am29F800BT Top Boot Block Sector Address Table

Address Range (in hexadecimal)
Sector Size
(Kbytes/ (x16) (x8)
Sector A18 A17 A16 A15 A14 A13 A12 Kwords) Address Range Address Range

SA0 0 0 0 0 X X X 64/32 00000h–07FFFh 00000h–0FFFFh

SA1 0 0 0 1 X X X 64/32 08000h–0FFFFh 10000h–1FFFFh

SA2 0 0 1 0 X X X 64/32 10000h–17FFFh 20000h–2FFFFh

SA3 0 0 1 1 X X X 64/32 18000h–1FFFFh 30000h–3FFFFh

SA4 0 1 0 0 X X X 64/32 20000h–27FFFh 40000h–4FFFFh

SA5 0 1 0 1 X X X 64/32 28000h–2FFFFh 50000h–5FFFFh

SA6 0 1 1 0 X X X 64/32 30000h–37FFFh 60000h–6FFFFh

SA7 0 1 1 1 X X X 64/32 38000h–3FFFFh 70000h–7FFFFh

SA8 1 0 0 0 X X X 64/32 40000h–47FFFh 80000h–8FFFFh

SA9 1 0 0 1 X X X 64/32 48000h–4FFFFh 90000h–9FFFFh

SA10 1 0 1 0 X X X 64/32 50000h–57FFFh A0000h–AFFFFh

SA11 1 0 1 1 X X X 64/32 58000h–5FFFFh B0000h–BFFFFh

SA12 1 1 0 0 X X X 64/32 60000h–67FFFh C0000h–CFFFFh

SA13 1 1 0 1 X X X 64/32 68000h–6FFFFh D0000h–DFFFFh

SA14 1 1 1 0 X X X 64/32 70000h–77FFFh E0000h–EFFFFh

SA15 1 1 1 1 0 X X 32/16 78000h–7BFFFh F0000h–F7FFFh

SA16 1 1 1 1 1 0 0 8/4 7C000h–7CFFFh F8000h–F9FFFh

SA17 1 1 1 1 1 0 1 8/4 7D000h–7DFFFh FA000h–FBFFFh

SA18 1 1 1 1 1 1 X 16/8 7E000h–7FFFFh FC000h–FFFFFh

Note:
Address range is A18:A-1 in byte mode and A18:A0 in word mode. See “Word/Byte Configuration” section for more information.

Am29F800BT/Am29F800BB 9
 PRELIMINARY

Table 3. Am29F800BB Bottom Boot Block Sector Address Table

Address Range (in hexadecimal)
Sector Size
(Kbytes/ (x16) (x8)
Sector A18 A17 A16 A15 A14 A13 A12 Kwords) Address Range Address Range

SA0 0 0 0 0 0 0 X 16/8 00000h–01FFFh 00000h–03FFFh

SA1 0 0 0 0 0 1 0 8/4 02000h–02FFFh 04000h–05FFFh

SA2 0 0 0 0 0 1 1 8/4 03000h–03FFFh 06000h–07FFFh

SA3 0 0 0 0 1 X X 32/16 04000h–07FFFh 08000h–0FFFFh

SA4 0 0 0 1 X X X 64/32 08000h–0FFFFh 10000h–1FFFFh

SA5 0 0 1 0 X X X 64/32 10000h–17FFFh 20000h–2FFFFh

SA6 0 0 1 1 X X X 64/32 18000h–1FFFFh 30000h–3FFFFh

SA7 0 1 0 0 X X X 64/32 20000h–27FFFh 40000h–4FFFFh

SA8 0 1 0 1 X X X 64/32 28000h–2FFFFh 50000h–5FFFFh

SA9 0 1 1 0 X X X 64/32 30000h–37FFFh 60000h–6FFFFh

SA10 0 1 1 1 X X X 64/32 38000h–3FFFFh 70000h–7FFFFh

SA11 1 0 0 0 X X X 64/32 40000h–47FFFh 80000h–8FFFFh

SA12 1 0 0 1 X X X 64/32 48000h–4FFFFh 90000h–9FFFFh

SA13 1 0 1 0 X X X 64/32 50000h–57FFFh A0000h–AFFFFh

SA14 1 0 1 1 X X X 64/32 58000h–5FFFFh B0000h–BFFFFh

SA15 1 1 0 0 X X X 64/32 60000h–67FFFh C0000h–CFFFFh

SA16 1 1 0 1 X X X 64/32 68000h–6FFFFh D0000h–DFFFFh

SA17 1 1 1 0 X X X 64/32 70000h–77FFFh E0000h–EFFFFh

SA18 1 1 1 1 X X X 64/32 78000h–7FFFFh F0000h–FFFFFh

Note:
Address range is A18:A-1 in byte mode and A18:A0 in word mode. See “Word/Byte Configuration” section for more information.

Autoselect Mode Table 4. In addition, when verifying sector protection,

the sector address must appear on the appropriate
The autoselect mode provides manufacturer and de-
highest order address bits (see Tables 2 and 3). Table
vice identification, and sector protection verification,
4 shows the remaining address bits that are don’t care.
through identifier codes output on DQ7–DQ0. This
When all necessary bits have been set as required, the
mode is primarily intended for programming equipment
programming equipment may then read the corre-
to automatically match a device to be programmed with
sponding identifier code on DQ7–DQ0.
its corresponding programming algorithm. However,
the autoselect codes can also be accessed in-system To access the autoselect codes in-system, the host
through the command register. system can issue the autoselect command via the
command register, as shown in Table 5. This method
When using programming equipment, the autoselect
does not require VID. See “Command Definitions” for
mode requires VID (11.5 V to 12.5 V) on address pin
details on using the autoselect mode.
A9. Address pins A6, A1, and A0 must be as shown in

10 Am29F800BT/Am29F800BB
 PRELIMINARY

Table 4. Am29F800B Autoselect Codes (High Voltage Method)

A18 A11 A8 A5 DQ8 DQ7
to to to to to to
Description Mode CE# OE# WE# A12 A10 A9 A7 A6 A2 A1 A0 DQ15 DQ0

Manufacturer ID: AMD L L H X X VID X L X L L X 01h

Device ID: Word L L H 22h D6h

Am29F800B X X VID X L X L H
(Top Boot Block) Byte L L H X D6h

Device ID: Word L L H 22h 58h

Am29F800B X X VID X L X L H
(Bottom Boot Block) Byte L L H X 58h

01h
X
Sector Protection (protected)
L L H SA X VID X L X H L
Verification 00h
X
(unprotected)

L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.

Sector Protection/Unprotection
The hardware sector protection feature disables both START
program and erase operations in any sector. The
hardware sector unprotection feature re-enables
both program and erase operations in previously pro- RESET# = VID
tected sectors. (Note 1)
Sector protection/unprotection must be implemented
using programming equipment. The procedure re- Perform Erase or
quires a high voltage (VID) on address pin A9 and the Program Operations
control pins. Details on this method are provided in a
supplement, publication number 20374. Contact an
AMD representative to obtain a copy of this document. RESET# = VIH

The device is shipped with all sectors unprotected.

AMD offers the option of programming and protecting
Temporary Sector
sectors at its factory prior to shipping the device
Unprotect Completed
through AMD’s ExpressFlash™ Service. Contact an (Note 2)
AMD representative for details.
It is possible to determine whether a sector is protected
or unprotected. See “Autoselect Mode” for details. 21504B-5
Notes:
Temporary Sector Unprotect 1. All protected sectors unprotected.
This feature allows temporary unprotection of previ- 2. All previously protected sectors are protected once
ously protected sectors to change data in-system. again.
The Sector Unprotect mode is activated by setting the
RESET# pin to VID. During this mode, formerly pro- Figure 1. Temporary Sector Unprotect Operation
tected sectors can be programmed or erased by se-
lecting the sector addresses. Once VID is removed
from the RESET# pin, all the previously protected Hardware Data Protection
sectors are protected again. Figure 1 shows the algo-
rithm, and Figure 17 shows the timing diagrams, for The command sequence requirement of unlock cycles
this feature. for programming or erasing provides data protection
against inadvertent writes (refer to Table 5 for com-
mand definitions). In addition, the following hardware
data protection measures prevent accidental erasure
or programming, which might otherwise be caused by

Am29F800BT/Am29F800BB 11
 PRELIMINARY

spurious system level signals during VCC power-up Logical Inhibit

and power-down transitions, or from system noise. Write cycles are inhibited by holding any one of OE#
Low VCC Write Inhibit = VIL, CE# = V IH or WE# = VIH. To initiate a write cy-
cle, CE# and WE# must be a logical zero while OE#
When VCC is less than VLKO, the device does not ac-
is a logical one.
cept any write cycles. This protects data during VCC
power-up and power-down. The command register and Power-Up Write Inhibit
all internal program/erase circuits are disabled, and the If WE# = CE# = V IL and OE# = V IH during power
device resets. Subsequent writes are ignored until VCC up, the device does not accept commands on the
is greater than VLKO. The system must provide the rising edge of WE#. The internal state machine is
proper signals to the control pins to prevent uninten- a u to m a ti c a l l y r e s e t to r e ad i n g a rr a y d a t a o n
tional writes when VCC is greater than VLKO. power-up.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.

COMMAND DEFINITIONS
Writing specific address and data commands or se- Reset Command
quences into the command register initiates device op-
Writing the reset command to the device resets the de-
erations. Table 5 defines the valid register command
vice to reading array data. Address bits are don’t care
sequences. Writing incorrect address and data val-
for this command.
ues or writing them in the improper sequence resets
the device to reading array data. The reset command may be written between the se-
quence cycles in an erase command sequence before
All addresses are latched on the falling edge of WE# or
erasing begins. This resets the device to reading array
CE#, whichever happens later. All data is latched on
data. Once erasure begins, however, the device ig-
the rising edge of WE# or CE#, whichever happens
nores reset commands until the operation is complete.
first. Refer to the appropriate timing diagrams in the
“AC Characteristics” section. The reset command may be written between the se-
quence cycles in a program command sequence be-
Reading Array Data fore programming begins. This resets the device to
The device is automatically set to reading array data reading array data (also applies to programming in
after device power-up. No commands are required to Erase Suspend mode). Once programming begins,
retrieve data. The device is also ready to read array however, the device ignores reset commands until the
data after completing an Embedded Program or Em- operation is complete.
bedded Erase algorithm. The reset command may be written between the se-
After the device accepts an Erase Suspend command, quence cycles in an autoselect command sequence.
the device enters the Erase Suspend mode. The sys- Once in the autoselect mode, the reset command must
tem can read array data using the standard read tim- be written to return to reading array data (also applies
ings, except that if it reads at an address within erase- to autoselect during Erase Suspend).
suspended sectors, the device outputs status data. If DQ5 goes high during a program or erase operation,
After completing a programming operation in the Erase writing the reset command returns the device to read-
Suspend mode, the system may once again read array ing array data (also applies during Erase Suspend).
data with the same exception. See “Erase Sus-
pend/Erase Resume Commands” for more information See “AC Characteristics” for parameters, and to Figure
on this mode. 10 for the timing diagram.

The system must issue the reset command to re-ena- Autoselect Command Sequence
ble the device for reading array data if DQ5 goes high,
The autoselect command sequence allows the host
or while in the autoselect mode. See the “Reset Com-
system to access the manufacturer and devices codes,
mand” section, next.
and determine whether or not a sector is protected.
See also “Requirements for Reading Array Data” in the Table 5 shows the address and data requirements.
“Device Bus Operations” section for more information. This method is an alternative to that shown in Table 4,
The Read Operations table provides the read parame- which is intended for PROM programmers and requires
ters, and Figure 9 shows the timing diagram. VID on address bit A9.

12 Am29F800BT/Am29F800BB
 PRELIMINARY

The autoselect command sequence is initiated by

writing two unlock cycles, followed by the autoselect
command. The device then enters the autoselect START
mode, and the system may read at any address any
number of times, without initiating another command
sequence. A read cycle at address XX00h or retrieves
the manufacturer code. A read cycle at address Write Program
XX01h in word mode (or 02h in byte mode) returns the Command Sequence
device code. A read cycle containing a sector address
(SA) and the address 02h in word mode (or 04h in
byte mode) returns 01h if that sector is protected, or
Data Poll
00h if it is unprotected. Refer to Tables 2 and 3 for from System
valid sector addresses. Embedded
Program
The system must write the reset command to exit the algorithm
autoselect mode and return to reading array data. in progress

Verify Data?
Word/Byte Program Command Sequence No
The system may program the device by word or byte,
depending on the state of the BYTE# pin. Program- Yes
ming is a four-bus-cycle operation. The program com-
mand sequence is initiated by writing two unlock write No
cycles, followed by the program set-up command. The Increment Address Last Address?
program address and data are written next, which in
turn initiate the Embedded Program algorithm. The
Yes
system is not required to provide further controls or tim-
ings. The device automatically provides internally gen- Programming
erated program pulses and verify the programmed cell Completed
margin. Table 5 shows the address and data require-
ments for the byte program command sequence. 21504B-6

When the Embedded Program algorithm is complete, Note:

the device then returns to reading array data and ad- See Table 5 for program command sequence.
dresses are no longer latched. The system can deter-
mine the status of the program operation by using Figure 2. Program Operation
DQ7, DQ6, or RY/BY#. See “Write Operation Status”
for information on these status bits.
Any commands written to the device during the Em- Chip Erase Command Sequence
bedded Program Algorithm are ignored. Note that a Chip erase is a six-bus-cycle operation. The chip erase
hardware reset immediately terminates the program- command sequence is initiated by writing two unlock
ming operation. The Byte Program command se- cycles, followed by a set-up command. Two additional
quence should be reinitiated once the device has reset unlock write cycles are then followed by the chip erase
to reading array data, to ensure data integrity. command, which in turn invokes the Embedded Erase
Programming is allowed in any sequence and across algorithm. The device does not require the system to
sector boundaries. A bit cannot be programmed preprogram prior to erase. The Embedded Erase algo-
from a “0” back to a “1”. Attempting to do so may halt rithm automatically preprograms and verifies the entire
the operation and set DQ5 to “1”, or cause the Data# memory for an all zero data pattern prior to electrical
Polling algorithm to indicate the operation was suc- erase. The system is not required to provide any con-
cessful. However, a succeeding read will show that the trols or timings during these operations. Table 5 shows
data is still “0”. Only erase operations can convert a “0” the address and data requirements for the chip erase
to a “1”. command sequence.
Any commands written to the chip during the Embed-
ded Erase algorithm are ignored. Note that a hardware
reset during the chip erase operation immediately ter-
minates the operation. The Chip Erase command se-
quence should be reinitiated once the device has
returned to reading array data, to ensure data integrity.

Am29F800BT/Am29F800BB 13
 PRELIMINARY

The system can determine the status of the erase When the Embedded Erase algorithm is complete, the
operation by using DQ7, DQ6, DQ2, or RY/BY#. device returns to reading array data and addresses are
See “Write Operation Status” for information on no longer latched. The system can determine the sta-
these status bits. When the Embedded Erase algo- tus of the erase operation by using DQ7, DQ6, DQ2, or
rithm is complete, the device returns to reading RY/BY#. (Refer to “Write Operation Status” for informa-
array data and addresses are no longer latched. tion on these status bits.)
Figure 3 illustrates the algorithm for the erase opera- Figure 3 illustrates the algorithm for the erase opera-
tion. See the Erase/Program Operations tables in “AC tion. Refer to the Erase/Program Operations tables in
Characteristics” for parameters, and to Figure 13 for the “AC Characteristics” section for parameters, and to
timing diagrams. Figure 13 for timing diagrams.

Sector Erase Command Sequence Erase Suspend/Erase Resume Commands

Sector erase is a six bus cycle operation. The sector The Erase Suspend command allows the system to in-
erase command sequence is initiated by writing two terrupt a sector erase operation and then read data
unlock cycles, followed by a set-up command. Two ad- from, or program data to, any sector not selected for
ditional unlock write cycles are then followed by the ad- erasure. This command is valid only during the sector
dress of the sector to be erased, and the sector erase erase operation, including the 50 µs time-out period
command. Table 5 shows the address and data re- during the sector erase command sequence. The
quirements for the sector erase command sequence. Erase Suspend command is ignored if written during
the chip erase operation or Embedded Program algo-
The device does not require the system to preprogram
rithm. Writing the Erase Suspend command during the
the memory prior to erase. The Embedded Erase algo-
Sector Erase time-out immediately terminates the
rithm automatically programs and verifies the sector for
time-out period and suspends the erase operation. Ad-
an all zero data pattern prior to electrical erase. The
dresses are “don’t-cares” when writing the Erase Sus-
system is not required to provide any controls or tim-
pend command.
ings during these operations.
When the Erase Suspend command is written during a
After the command sequence is written, a sector erase
sector erase operation, the device requires a maximum
time-out of 50 µs begins. During the time-out period,
of 20 µs to suspend the erase operation. However,
additional sector addresses and sector erase com-
when the Erase Suspend command is written during
mands may be written. Loading the sector erase buffer
the sector erase time-out, the device immediately ter-
may be done in any sequence, and the number of sec-
minates the time-out period and suspends the erase
tors may be from one sector to all sectors. The time be-
operation.
tween these additional cycles must be less than 50 µs,
otherwise the last address and command might not be After the erase operation has been suspended, the
accepted, and erasure may begin. It is recommended system can read array data from or program data to
that processor interrupts be disabled during this time to any sector not selected for erasure. (The device “erase
ensure all commands are accepted. The interrupts can suspends” all sectors selected for erasure.) Normal
be re-enabled after the last Sector Erase command is read and write timings and command definitions apply.
written. If the time between additional sector erase Reading at any address within erase-suspended sec-
commands can be assumed to be less than 50 µs, the tors produces status data on DQ7–DQ0. The system
system need not monitor DQ3. Any command other can use DQ7, or DQ6 and DQ2 together, to determine
than Sector Erase or Erase Suspend during the if a sector is actively erasing or is erase-suspended.
time-out period resets the device to reading array See “Write Operation Status” for information on these
data. The system must rewrite the command sequence status bits.
and any additional sector addresses and commands.
After an erase-suspended program operation is com-
The system can monitor DQ3 to determine if the sector plete, the system can once again read array data within
erase timer has timed out. (See the “DQ3: Sector non-suspended sectors. The system can determine the
Erase Timer” section.) The time-out begins from the status of the program operation using the DQ7 or DQ6
rising edge of the final WE# pulse in the command se- status bits, just as in the standard program operation.
quence. See “Write Operation Status” for more information.
Once the sector erase operation has begun, only the The system may also write the autoselect command
Erase Suspend command is valid. All other commands sequence when the device is in the Erase Suspend
are ignored. Note that a hardware reset during the mode. The device allows reading autoselect codes
sector erase operation immediately terminates the op- even at addresses within erasing sectors, since the
eration. The Sector Erase command sequence should codes are not stored in the memory array. When the
be reinitiated once the device has returned to reading device exits the autoselect mode, the device reverts to
array data, to ensure data integrity. the Erase Suspend mode, and is ready for another

14 Am29F800BT/Am29F800BB
 PRELIMINARY

valid operation. See “Autoselect Command Sequence”

for more information.
START
The system must write the Erase Resume command
(address bits are “don’t care”) to exit the erase suspend
mode and continue the sector erase operation. Further
writes of the Resume command are ignored. Another Write Erase
Erase Suspend command can be written after the de- Command Sequence
vice has resumed erasing.

Data Poll
from System
Embedded
Erase
algorithm
in progress
No
Data = FFh?

Yes

Erasure Completed

21504B-7

Notes:
1. See Table 5 for erase command sequence.
2. See “DQ3: Sector Erase Timer” for more information.

Figure 3. Erase Operation

Am29F800BT/Am29F800BB 15
 PRELIMINARY

Table 5. Am29F800B Command Definitions

Bus Cycles (Notes 2–5)

Cycles
Command
Sequence First Second Third Fourth Fifth Sixth
(Note 1) Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read (Note 6) 1 RA RD
Reset (Note 7) 1 XXX F0
Word 555 2AA 555
Manufacturer ID 4 AA 55 90 X00 01
Byte AAA 555 AAA
Autoselect (Note 8)

Device ID, Word 555 2AA 555 X01 22D6

4 AA 55 90
Top Boot Block Byte AAA 555 AAA X02 D6
Device ID, Word 555 2AA 555 X01 2258
4 AA 55 90
Bottom Boot Block Byte AAA 555 AAA X02 58
(SA) XX00
Word 555 2AA 555
Sector Protect Verify X02 XX01
4 AA 55 90
(Note 9) (SA) 00
Byte AAA 555 AAA
X04 01
Word 555 2AA 555
Program 4 AA 55 A0 PA PD
Byte AAA 555 AAA
Word 555 2AA 555 555 2AA 555
Chip Erase 6 AA 55 80 AA 55 10
Byte AAA 555 AAA AAA 555 AAA
Word 555 2AA 555 555 2AA
Sector Erase 6 AA 55 80 AA 55 SA 30
Byte AAA 555 AAA AAA 555
Erase Suspend (Note 10) 1 XXX B0
Erase Resume (Note 11) 1 XXX 30

Legend:
X = Don’t care PD = Data to be programmed at location PA. Data latches on the
RA = Address of the memory location to be read. rising edge of WE# or CE# pulse, whichever happens first.

RD = Data read from location RA during read operation. SA = Address of the sector to be verified (in autoselect mode) or
erased. Address bits A17–A12 uniquely select any sector.
PA = Address of the memory location to be programmed.
Addresses latch on the falling edge of the WE# or CE# pulse,
whichever happens later.

Notes:
1. See Table 1 for description of bus operations. 8. The fourth cycle of the autoselect command sequence is a
2. All values are in hexadecimal. read cycle.

3. Except when reading array or autoselect data, all bus cycles 9. The data is 00h for an unprotected sector and 01h for a
are write operations. protected sector. See “Autoselect Command Sequence” for
more information.
4. Data bits DQ15–DQ8 are don’t cares for unlock and
command cycles. 10. The system may read and program in non-erasing sectors, or
enter the autoselect mode, when in the Erase Suspend
5. Address bits A17–A11 are don’t cares for unlock and mode. The Erase Suspend command is valid only during a
command cycles, unless SA or PA required. sector erase operation.
6. No unlock or command cycles required when reading array 11. The Erase Resume command is valid only during the Erase
data. Suspend mode.
7. The Reset command is required to return to reading array
data when device is in the autoselect mode, or if DQ5 goes
high (while the device is providing status data).

16 Am29F800BT/Am29F800BB
 PRELIMINARY

WRITE OPERATION STATUS

The device provides several bits to determine the sta- Table 6 shows the outputs for Data# Polling on DQ7.
tus of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7, Figure 4 shows the Data# Polling algorithm.
and RY/BY#. Table 6 and the following subsections de-
scribe the functions of these bits. DQ7, RY/BY#, and START
DQ6 each offer a method for determining whether a
program or erase operation is complete or in progress.
These three bits are discussed first.
Read DQ7–DQ0
DQ7: Data# Polling Addr = VA
The Data# Polling bit, DQ7, indicates to the host
system whether an Embedded Algorithm is in
progress or completed, or whether the device is in
Erase Suspend. Data# Polling is valid after the ris- Yes
ing edge of the final WE# pulse in the program or DQ7 = Data?
erase command sequence.
During the Embedded Program algorithm, the device No
outputs on DQ7 the complement of the datum pro-
grammed to DQ7. This DQ7 status also applies to pro-
gramming during Erase Suspend. When the No DQ5 = 1?
Embedded Program algorithm is complete, the device
outputs the datum programmed to DQ7. The system
must provide the program address to read valid status Yes
information on DQ7. If a program address falls within a
protected sector, Data# Polling on DQ7 is active for ap-
proximately 2 µs, then the device returns to reading Read DQ7–DQ0
array data. Addr = VA

During the Embedded Erase algorithm, Data# Polling

produces a “0” on DQ7. When the Embedded Erase al-
gorithm is complete, or if the device enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7. Yes
DQ7 = Data?
This is analogous to the complement/true datum output
described for the Embedded Program algorithm: the
erase function changes all the bits in a sector to “1”; No
prior to this, the device outputs the “complement,” or
“0.” The system must provide an address within any of PASS
FAIL
the sectors selected for erasure to read valid status in-
formation on DQ7.
Notes:
After an erase command sequence is written, if all sec-
1. VA = Valid address for programming. During a sector
tors selected for erasing are protected, Data# Polling erase operation, a valid address is an address within any
on DQ7 is active for approximately 100 µs, then the de- sector selected for erasure. During chip erase, a valid
vice returns to reading array data. If not all selected address is any non-protected sector address.
sectors are protected, the Embedded Erase algorithm
2. DQ7 should be rechecked even if DQ5 = “1” because
erases the unprotected sectors, and ignores the se- DQ7 may change simultaneously with DQ5.
lected sectors that are protected.
When the system detects DQ7 has changed from the 21504B-8
complement to true data, it can read valid data at DQ7–
Figure 4. Data# Polling Algorithm
DQ0 on the following read cycles. This is because DQ7
may change asynchronously with DQ0–DQ6 while
Output Enable (OE#) is asserted low. Figure 14, Data#
Polling Timings (During Embedded Algorithms), in the
“AC Characteristics” section illustrates this.

Am29F800BT/Am29F800BB 17
 PRELIMINARY

RY/BY#: Ready/Busy# Table 6 shows the outputs for Toggle Bit I on DQ6. Fig-
ure 5 shows the toggle bit algorithm. Figure 15 in the
The RY/BY# is a dedicated, open-drain output pin that
“AC Characteristics” section shows the toggle bit timing
indicates whether an Embedded Algorithm is in
diagrams. Figure 16 shows the differences between
progress or complete. The RY/BY# status is valid after
DQ2 and DQ6 in graphical form. See also the subsec-
the rising edge of the final WE# pulse in the command
tion on DQ2: Toggle Bit II.
sequence. Since RY/BY# is an open-drain output, sev-
eral RY/BY# pins can be tied together in parallel with a
DQ2: Toggle Bit II
pull-up resistor to VCC.
The “Toggle Bit II” on DQ2, when used with DQ6, indi-
If the output is low (Busy), the device is actively erasing cates whether a particular sector is actively erasing
or programming. (This includes programming in the (that is, the Embedded Erase algorithm is in progress),
Erase Suspend mode.) If the output is high (Ready), or whether that sector is erase-suspended. Toggle Bit
the device is ready to read array data (including during II is valid after the rising edge of the final WE# pulse in
the Erase Suspend mode), or is in the standby mode. the command sequence.
Table 6 shows the outputs for RY/BY#. Figures 10, 13 DQ2 toggles when the system reads at addresses
and 13 shows RY/BY# for reset, program, and erase within those sectors that have been selected for eras-
operations, respectively. ure. (The system may use either OE# or CE# to control
the read cycles.) But DQ2 cannot distinguish whether
DQ6: Toggle Bit I the sector is actively erasing or is erase-suspended.
Toggle Bit I on DQ6 indicates whether an Embedded DQ6, by comparison, indicates whether the device is
Program or Erase algorithm is in progress or complete, actively erasing, or is in Erase Suspend, but cannot
or whether the device has entered the Erase Suspend distinguish which sectors are selected for erasure.
mode. Toggle Bit I may be read at any address, and is Thus, both status bits are required for sector and mode
valid after the rising edge of the final WE# pulse in the information. Refer to Table 6 to compare outputs for
command sequence (prior to the program or erase op- DQ2 and DQ6.
eration), and during the sector erase time-out.
Figure 5 shows the toggle bit algorithm in flowchart
During an Embedded Program or Erase algorithm op- form, and the section “DQ2: Toggle Bit II” explains the
eration, successive read cycles to any address cause algorithm. See also the DQ6: Toggle Bit I subsection.
DQ6 to toggle. (The system may use either OE# or Figure 15 shows the toggle bit timing diagram. Figure
CE# to control the read cycles.) When the operation is 16 shows the differences between DQ2 and DQ6 in
complete, DQ6 stops toggling. graphical form.
After an erase command sequence is written, if all
Reading Toggle Bits DQ6/DQ2
sectors selected for erasing are protected, DQ6 tog-
gles for approximately 100 µs, then returns to reading Refer to Figure 5 for the following discussion. When-
array data. If not all selected sectors are protected, ever the system initially begins reading toggle bit sta-
the Embedded Erase algorithm erases the unpro- tus, it must read DQ7–DQ0 at least twice in a row to
tected sectors, and ignores the selected sectors that determine whether a toggle bit is toggling. Typically,
are protected. the system would note and store the value of the tog-
gle bit after the first read. After the second read, the
The system can use DQ6 and DQ2 together to deter- system would compare the new value of the toggle bit
mine whether a sector is actively erasing or is erase- with the first. If the toggle bit is not toggling, the device
suspended. When the device is actively erasing (that has completed the program or erase operation. The
is, the Embedded Erase algorithm is in progress), DQ6 system can read array data on DQ7–DQ0 on the fol-
toggles. When the device enters the Erase Suspend lowing read cycle.
mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing However, if after the initial two read cycles, the system
or erase-suspended. Alternatively, the system can use determines that the toggle bit is still toggling, the sys-
DQ7 (see the subsection on DQ7: Data# Polling). tem also should note whether the value of DQ5 is high
(see the section on DQ5). If it is, the system should
If a program address falls within a protected sector, then determine again whether the toggle bit is toggling,
DQ6 toggles for approximately 2 µs after the program since the toggle bit may have stopped toggling just as
command sequence is written, then returns to reading DQ5 went high. If the toggle bit is no longer toggling,
array data. the device has successfully completed the program or
DQ6 also toggles during the erase-suspend-program erase operation. If it is still toggling, the device did not
mode, and stops toggling once the Embedded Pro- completed the operation successfully, and the system
gram algorithm is complete. must write the reset command to return to reading
array data.

18 Am29F800BT/Am29F800BB
 PRELIMINARY

The remaining scenario is that the system initially de- DQ5: Exceeded Timing Limits
termines that the toggle bit is toggling and DQ5 has not
DQ5 indicates whether the program or erase time has
gone high. The system may continue to monitor the
exceeded a specified internal pulse count limit. Under
toggle bit and DQ5 through successive read cycles, de-
these conditions DQ5 produces a “1.” This is a failure
termining the status as described in the previous para-
condition that indicates the program or erase cycle was
graph. Alternatively, it may choose to perform other
not successfully completed.
system tasks. In this case, the system must start at the
beginning of the algorithm when it returns to determine The DQ5 failure condition may appear if the system
the status of the operation (top of Figure 5). tries to program a “1” to a location that is previously
programmed to “0.” Only an erase operation can
change a “0” back to a “1.” Under this condition, the
device halts the operation, and when the operation has
START exceeded the timing limits, DQ5 produces a “1.”
Under both these conditions, the system must issue
the reset command to return the device to reading
Read DQ7–DQ0
array data.

DQ3: Sector Erase Timer

After writing a sector erase command sequence, the
Read DQ7–DQ0 (Note 1) system may read DQ3 to determine whether or not an
erase operation has begun. (The sector erase timer
does not apply to the chip erase command.) If addi-
tional sectors are selected for erasure, the entire time-
Toggle Bit No out also applies after each additional sector erase
= Toggle? command. When the time-out is complete, DQ3
switches from “0” to “1.” If the time between additional
Yes sector erase commands from the system can be as-
sumed to be less than 50 µs, the system need not
monitor DQ3. See also the “Sector Erase Command
No Sequence” section.
DQ5 = 1?
After the sector erase command sequence is written,
the system should read the status on DQ7 (Data# Poll-
Yes ing) or DQ6 (Toggle Bit I) to ensure the device has ac-
cepted the command sequence, and then read DQ3. If
(Notes DQ3 is “1”, the internally controlled erase cycle has be-
Read DQ7–DQ0
Twice 1, 2) gun; all further commands (other than Erase Suspend)
are ignored until the erase operation is complete. If
DQ3 is “0”, the device will accept additional sector
erase commands. To ensure the command has been
Toggle Bit No accepted, the system software should check the status
= Toggle? of DQ3 prior to and following each subsequent sector
erase command. If DQ3 is high on the second status
check, the last command might not have been ac-
Yes
cepted. Table 6 shows the outputs for DQ3.
Program/Erase
Operation Not Program/Erase
Complete, Write Operation Complete
Reset Command
Notes:
1. Read toggle bit twice to determine whether or not it is
toggling. See text.
2. Recheck toggle bit because it may stop toggling as DQ5
changes to “1” . See text.
21504B-9

Figure 5. Toggle Bit Algorithm

Am29F800BT/Am29F800BB 19
 PRELIMINARY

Table 6. Write Operation Status

DQ7 DQ5 DQ2
Operation (Note 2) DQ6 (Note 1) DQ3 (Note 2) RY/BY#
Standard Embedded Program Algorithm DQ7# Toggle 0 N/A No toggle 0
Mode Embedded Erase Algorithm 0 Toggle 0 1 Toggle 0
Reading within Erase
1 No toggle 0 N/A Toggle 1
Erase Suspended Sector
Suspend Reading within Non-Erase
Data Data Data Data Data 1
Mode Suspended Sector
Erase-Suspend-Program DQ7# Toggle 0 N/A N/A 0
Notes:
1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
See “DQ5: Exceeded Timing Limits” for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.

20 Am29F800BT/Am29F800BB
 PRELIMINARY

ABSOLUTE MAXIMUM RATINGS OPERATING RANGES

Storage Temperature Commercial (C) Devices
Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C Ambient Temperature (TA) . . . . . . . . . . .0°C to +70°C
Ambient Temperature Industrial (I) Devices
with Power Applied . . . . . . . . . . . . . –55°C to +125°C
Ambient Temperature (TA) . . . . . . . . .–40°C to +85°C
Voltage with Respect to Ground
Extended (E) Devices
VCC (Note 1) . . . . . . . . . . . . . . . . –2.0 V to +7.0 V
Ambient Temperature (TA) . . . . . . . .–55°C to +125°C
A9, OE#, and
RESET# (Note 2). . . . . . . . . . . . –2.0 V to +12.5 V VCC Supply Voltages

All other pins (Note 1) . . . . . . . . . –0.5 V to +7.0 V VCC for ± 5% devices . . . . . . . . . . +4.75 V to +5.25 V

Output Short Circuit Current (Note 3) . . . . . . 200 mA VCC for± 10% devices. . . . . . . . . . . . +4.5 V to +5.5 V
Notes: Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
1. Minimum DC voltage on input or I/O pins is –0.5 V. During
voltage transitions, input or I/O pins may undershoot VSS
to –2.0 V for periods of up to 20 ns. See Figure 6.
Maximum DC voltage on input or I/O pins is VCC +0.5 V.
During voltage transitions, input or I/O pins may
overshoot to VCC +2.0 V for periods up to 20 ns. See
Figure 7.
2. Minimum DC input voltage on pins A9, OE#, and RESET#
is –0.5 V. During voltage transitions, A9, OE#, and
RESET# may undershoot VSS to –2.0 V for periods of up
to 20 ns. See Figure 6. Maximum DC input voltage on pin
A9 is +12.5 V which may overshoot to +13.5 V for periods
up to 20 ns.
3. No more than one output may be shorted to ground at a
time. Duration of the short circuit should not be greater
than one second.
4. Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device at these or any other conditions above those in-
dicated in the operational sections of this data sheet is
not implied. Exposure of the device to absolute maxi-
mum rating conditions for extended periods may affect
device reliability.

20 ns 20 ns 20 ns
+0.8 V VCC
+2.0 V
–0.5 V VCC
+0.5 V
–2.0 V
2.0 V
20 ns
20 ns 20 ns

21504B-10 21504B-11

Figure 6. Maximum Negative Overshoot Figure 7. Maximum Positive Overshoot

Waveform Waveform

Am29F800BT/Am29F800BB 21
 PRELIMINARY

DC CHARACTERISTICS
TTL/NMOS Compatible
Parameter Description Test Conditions Min Typ Max Unit

ILI Input Load Current VIN = VSS to VCC, VCC = VCC max ±1.0 µA

ILIT A9 Input Load Current VCC = VCC max; A9 = 12.5 V 35 µA

ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC max ±1.0 µA

CE# = VIL, OE# = VIH, VCC = VCC max, ,

19 40 mA
f = 5 MHz, Byte Mode
VCC Active Read Current
ICC1
(Note 1) CE# = VIL, OE# = VIH, VCC = VCC max,
19 50 mA
f = 5 MHz, Word Mode
VCC Active Write Current
ICC2 CE# = VIL, OE# = VIH, VCC = VCC max 36 60 mA
(Notes 2 and 3)

CE#, OE#, and RESET# = VIH,

ICC3 VCC Standby Current 0.4 1 mA
VCC = VCC max,

VIL Input Low Voltage –0.5 0.8 V

VCC
VIH Input High Voltage 2.0 V
+ 0.5

Voltage for Autoselect and

VID VCC = 5.0 V 11.5 12.5 V
Temporary Sector Unprotect

VOL Output Low Voltage IOL = 5.8 mA, VCC = VCC min 0.45 V

VOH Output High Voltage IOH = –2.5 mA, VCC = VCC min 2.4 V

Low VCC Lock-Out Voltage

VLKO 3.2 4.2 V
(Note 3)

Notes:
1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH.
2. ICC active while Embedded Erase or Embedded Program is in progress.
3. Not 100% tested.

22 Am29F800BT/Am29F800BB
 PRELIMINARY

DC CHARACTERISTICS
CMOS Compatible
Parameter Description Test Conditions Min Typ Max Unit

VIN = VSS to VCC,

ILI Input Load Current ±1.0 µA
VCC = VCC max

VCC = VCC max;

ILIT A9 Input Load Current 35 µA
A9 = 12.5 V

VOUT = VSS to VCC,

ILO Output Leakage Current ±1.0 µA
VCC = VCC max

CE# = VIL, OE# = VIH,

VCC = VCC max, f = 5 MHz 20 40 mA
Byte Mode
ICC1 VCC Active Read Current
CE# = VIL, OE# = VIH,
VCC = VCC max, f = 5 MHz 28 50 mA
Word Mode

VCC Active Write Current CE# = VIL, OE# = VIH,

ICC2 30 50 mA
(Notes 1 and 2) VCC = VCC max

CE# and RESET# = VCC±0.5 V,

ICC3 VCC Standby Current 0.3 5 µA
OE# = VIH, VCC = VCC max

VIL Input Low Voltage –0.5 0.8 V

VIH Input High Voltage 0.7 x VCC VCC + 0.3 V

Voltage for Autoselect and

VID VCC = 5.0 V 11.5 12.5 V
Temporary Sector Unprotect

VOL Output Low Voltage IOL = 5.8 mA, VCC = VCC min 0.45 V

VOH1 IOH = –2.5 mA, VCC = VCC min 0.85 VCC V

Output High Voltage
VOH2 IOH = –100 µA, VCC = VCC min VCC–0.4 V

Low VCC Lock-Out Voltage

VLKO 3.2 4.2 V
(Note 2)

Notes:
1. ICC active while Embedded Erase or Embedded Program is in progress.
2. Not 100% tested.

Am29F800BT/Am29F800BB 23
 PRELIMINARY

TEST CONDITIONS
Table 7. Test Specifications
5.0 V
All
Test Condition -55 others Unit
2.7 kΩ
Device Output Load 1 TTL gate
Under
Test Output Load Capacitance, CL
30 100 pF
(including jig capacitance)
CL 6.2 kΩ
Input Rise and Fall Times 5 20 ns

Input Pulse Levels 0.0–3.0 0.45–2.4 V

Input timing measurement

1.5 0.8, 2.0 V
reference levels
Note:
Diodes are IN3064 or equivalents. Output timing measurement
1.5 0.8, 2.0 V
reference levels
21504B-12
Figure 8. Test Setup

KEY TO SWITCHING WAVEFORMS

WAVEFORM INPUTS OUTPUTS

Must Be Will Be
Steady Steady

May Will Be
Change Changing
from H to L from H to L

May Will Be
Change Changing
from L to H from L to H

Don’t Care, Changing,

Any Change State
Permitted Unknown

Does Not Center

Apply Line is High-
Impedance
“Off” State
KS000010

24 Am29F800BT/Am29F800BB
 PRELIMINARY

AC CHARACTERISTICS
Read Operations
Parameter Speed Option

JEDEC Std Description Test Setup -55 -70 -90 -120 -150 Unit

tAVAV tRC Read Cycle Time (Note 1) Min 55 70 90 120 150 ns

CE# = VIL
tAVQV tACC Address to Output Delay Max 55 70 90 120 150 ns
OE# = VIL

tELQV tCE Chip Enable to Output Delay OE# = VIL Max 55 70 90 120 150 ns

tGLQV tOE Output Enable to Output Delay Max 30 30 35 50 55 ns

Chip Enable to Output High Z (Note

tEHQZ tDF Max 20 20 20 30 35 ns
1)

Output Enable to Output High Z

tGHQZ tDF Max 20 20 20 30 35 ns
(Note 1)

Output Enable Read Min 0 ns

tOEH Hold Time Toggle and
(Note 1) Min 10 ns
Data# Polling

Output Hold Time From

tAXQX tOH Addresses, CE# or OE#, Min 0 ns
Whichever Occurs First (Note 1)

Notes:
1. Not 100% tested.
2. See Figure 8 and Table 7 for test specifications.

tRC

Addresses Addresses Stable

tACC
CE#

tDF
tOE
OE#
tOEH

WE# tCE
tOH
HIGH Z HIGH Z
Outputs Output Valid

RESET#

RY/BY#
0V

21504B-13
Figure 9. Read Operations Timings

Am29F800BT/Am29F800BB 25
 PRELIMINARY

AC CHARACTERISTICS
Hardware Reset (RESET#)
Parameter

JEDEC Std Description Test Setup All Speed Options Unit

RESET# Pin Low (During Embedded

tREADY Max 20 µs
Algorithms) to Read or Write (See Note)

RESET# Pin Low (NOT During Embedded

tREADY Max 500 ns
Algorithms) to Read or Write (See Note)

tRP RESET# Pulse Width Min 500 ns

tRH RESET# High Time Before Read (See Note) Min 50 ns

tRB RY/BY# Recovery Time Min 0 ns

Note:
Not 100% tested.

RY/BY#

CE#, OE#
tRH

RESET#

tRP
tReady

Reset Timings NOT during Embedded Algorithms

Reset Timings during Embedded Algorithms

tReady
RY/BY#

tRB

CE#, OE#

RESET#

tRP

21504B-14
Figure 10. RESET# Timings

26 Am29F800BT/Am29F800BB
 PRELIMINARY

AC CHARACTERISTICS
Word/Byte Configuration (BYTE#)
Parameter

JEDEC Std. Description -55 -70 -90 -120 -150 Unit

tELFL/tELFH CE# to BYTE# Switching Low or High Max 5 ns

tFLQZ BYTE# Switching Low to Output HIGH Z Max 20 20 20 30 35 ns

tFHQV BYTE# Switching High to Output Active Min 55 70 90 120 150 ns

CE#

OE#

BYTE#

tELFL
BYTE# DQ0–DQ14 Data Output Data Output
Switching (DQ0–DQ14) (DQ0–DQ7)
from word
to byte
mode DQ15/A-1 DQ15 Address
Output Input

tFLQZ

tELFH
BYTE#

BYTE#
Switching
from byte DQ0–DQ14 Data Output Data Output
to word (DQ0–DQ7) (DQ0–DQ14)
mode
DQ15/A-1 Address DQ15
Input Output

tFHQV

21504B-15
Figure 11. BYTE# Timings for Read Operations

CE#

The falling edge of the last WE# signal

WE#

BYTE#
tSET
(tAS)
tHOLD (tAH)

Note:
Refer to the Erase/Program Operations table for tAS and tAH specifications.
21504B-16
Figure 12. BYTE# Timings for Write Operations

Am29F800BT/Am29F800BB 27
 PRELIMINARY

AC CHARACTERISTICS
Erase/Program Operations
Parameter

JEDEC Std. Description -55 -70 -90 -120 -150 Unit

tAVAV tWC Write Cycle Time (Note 1) Min 55 70 90 120 150 ns

tAVWL tAS Address Setup Time Min 0 ns

tWLAX tAH Address Hold Time Min 45 45 45 50 50 ns

tDVWH tDS Data Setup Time Min 30 30 45 50 50 ns

tWHDX tDH Data Hold Time Min 0 ns

tOES Output Enable Setup Time (Note 1) Min 0 ns

Read Recovery Time Before Write

tGHWL tGHWL Min 0 ns
(OE# High to WE# Low)

tELWL tCS CE# Setup Time Min 0 ns

tWHEH tCH CE# Hold Time Min 0 ns

tWLWH tWP Write Pulse Width Min 35 35 45 50 50 ns

tWHWL tWPH Write Pulse Width High Min 20 ns

Byte Typ 7
tWHWH1 tWHWH1 Programming Operation (Note 2) µs
Word Typ 14

tWHWH2 tWHWH2 Sector Erase Operation (Notes 1, 2) Typ 1 sec

tVCS VCC Setup Time Min 50 µs

tRB Recovery Time from RY/BY# Min 0 ns

tBUSY Program/Erase Valid to RY/BY# Delay Min 30 30 35 50 55 ns

Notes:
1. Not 100% tested.
2. The duration of the program or erase operation is variable and is calculated in the internal algorithms.

28 Am29F800BT/Am29F800BB
 PRELIMINARY

AC CHARACTERISTICS
Program Command Sequence (last two cycles) Read Status Data (last two cycles)
tWC tAS

Addresses 555h PA PA PA
tAH

CE#
tCH
tGHWL
OE#

tWP tWHWH1

WE#
tWPH
tCS
tDS
tDH

Data A0h PD Status DOUT

tBUSY tRB

RY/BY#
tVCS

VCC
21504B-17
Notes:
1. PA = program address, PD = program data, DOUT is the true data at the program address.
2. Illustration shows device in word mode.
Figure 13. Program Operation Timings

Erase Command Sequence (last two cycles) Read Status Data

tWC tAS
Addresses 2AAh SA VA VA
555h for chip erase
tAH
CE#
tGHWL
OE# tCH

tWP
WE#
tWPH tWHWH2
tCS
tDS
tDH
In
Data 55h 30h Progress Complete

10 for Chip Erase

tBUSY tRB

RY/BY#
tVCS
VCC
21504B-18
Notes:
1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”).
2. Illustration shows device in word mode.

Figure 13. Chip/Sector Erase Operation Timings

Am29F800BT/Am29F800BB 29
 PRELIMINARY

AC CHARACTERISTICS
tRC
Addresses VA VA VA
tACC
tCE
CE#

tCH
tOE
OE#
tOEH tDF
WE#
tOH
High Z
DQ7 Complement Complement True Valid Data

High Z
DQ0–DQ6 Status Data Status Data True Valid Data

tBUSY

RY/BY#

Note:
VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read
cycle.
21504B-18
Figure 14. Data# Polling Timings (During Embedded Algorithms)

tRC
Addresses VA VA VA VA
tACC
tCE
CE#

tCH
tOE
OE#
tOEH tDF
WE#
tOH
High Z
DQ6/DQ2 Valid Status Valid Status Valid Status Valid Data
(first read) (second read) (stops toggling)
tBUSY

RY/BY#

Note:
VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle,
and array data read cycle.
21504B-19
Figure 15. Toggle Bit Timings (During Embedded Algorithms)

30 Am29F800BT/Am29F800BB
 PRELIMINARY

AC CHARACTERISTICS
Enter
Embedded Erase Enter Erase Erase
Erasing Suspend Suspend Program Resume

WE# Erase Erase Suspend Erase Erase Suspend Erase Erase

Read Suspend Read Complete
Program

DQ6

DQ2

Note:
The system may use OE# or CE# to toggle DQ2 and DQ6. DQ2 must be read at an address within the erase-suspended sector.
21504B-20
Figure 16. DQ2 vs. DQ6

Temporary Sector Unprotect

Parameter

JEDEC Std. Description All Speed Options Unit

tVIDR VID Rise and Fall Time Min 500 ns

RESET# Setup Time for Temporary Sector

tRSP Min 4 µs
Unprotect

12 V

RESET#
0 or 5 V 0 or 5 V
tVIDR tVIDR
Program or Erase Command Sequence

CE#

WE#
tRSP

RY/BY#

21504B-21
Figure 17. Temporary Sector Unprotect Timing Diagram

Am29F800BT/Am29F800BB 31
 PRELIMINARY

AC CHARACTERISTICS
Alternate CE# Controlled Erase/Program Operations
Parameter

JEDEC Std. Description -55 -70 -90 -120 -150 Unit

tAVAV tWC Write Cycle Time (Note 1) Min 55 70 90 120 150 ns

tAVEL tAS Address Setup Time Min 0 ns

tELAX tAH Address Hold Time Min 45 45 45 50 50 ns

tDVEH tDS Data Setup Time Min 30 30 45 50 50 ns

tEHDX tDH Data Hold Time Min 0 ns

tOES Output Enable Setup Time Min 0 ns

Read (Note 1) Min 0 ns

Output Enable
tOEH Toggle and Data#
Hold Time Min 10 ns
Polling (Note 1)

Read Recovery Time Before Write

tGHEL tGHEL Min 0 ns
(OE# High to WE# Low)

tWLEL tWS WE# Setup Time Min 0 ns

tEHWH tWH WE# Hold Time Min 0 ns

tELEH tCP CE# Pulse Width Min 35 35 45 50 50 ns

tEHEL tCPH CE# Pulse Width High Min 20 ns

Programming Operation Byte Typ 7

tWHWH1 tWHWH1 µs
(Note 2) Word Typ 14

tWHWH2 tWHWH2 Sector Erase Operation (Notes 2, 3) Typ 1 sec

Notes:
1. Not 100% tested.
2. The duration of the program or erase operation is variable and is calculated in the internal algorithms.
3. Does not include the preprogramming time.

32 Am29F800BT/Am29F800BB
 PRELIMINARY

AC CHARACTERISTICS
555 for program PA for program
2AA for erase SA for sector erase
555 for chip erase
Data# Polling

Addresses PA
tWC tAS
tAH
tWH

WE#
tGHEL
OE#
tCP tWHWH1 or 2

CE#
tWS tCPH
tBUSY
tDS
tDH
DQ7# DOUT
Data
tRH A0 for program PD for program
55 for erase 30 for sector erase
10 for chip erase

RESET#

RY/BY#

Notes:
1. PA = Program Address, PD = Program Data, SA = Sector Address, DQ7# = Complement of Data Input, DOUT = Array Data.
2. Figure indicates the last two bus cycles of the command sequence, with the device in word mode.
21504B-22
Figure 18. Alternate CE# Controlled Write Operation Timings

Am29F800BT/Am29F800BB 33
 PRELIMINARY

ERASE AND PROGRAMMING PERFORMANCE

Parameter Typ (Note 1) Max (Note 3) Unit Comments

Sector Erase Time 1.0 8 s Excludes 00h programming

Chip Erase Time (Note 2) 19 s prior to erasure (Note 4)

Byte Programming Time 7 300 µs

Word Programming Time 12 500 µs Excludes system level

Byte Mode 7.2 21.6 s overhead (Note 5)
Chip Programming Time
(Note 2) Word Mode 6.3 18.6 s

Notes:
1. Typical program and erase times assume the following conditions: 25°C, 5.0 V VCC, 100,000 cycles. Additionally,
programming typicals assume checkerboard pattern.
2. Under worst case conditions of 90°C, VCC = 4.5 V, 100,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum program times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the four-bus-cycle sequence for the program command. See Table 5
for further information on command definitions.
6. The device has a typical erase and program cycle endurance of 1,000,000 cycles. 100,000 cycles are guaranteed.

LATCHUP CHARACTERISTICS
Description Min Max

Input voltage with respect to VSS on all pins except I/O pins
–1.0 V 12.5 V
(including A9, OE#, and RESET#)

Input voltage with respect to VSS on all I/O pins –1.0 V VCC + 1.0 V

VCC Current –100 mA +100 mA

Includes all pins except VCC. Test conditions: VCC = 5.0 V, one pin at a time.

TSOP AND SO PIN PACKAGE CAPACITANCE

Parameter
Symbol Parameter Description Test Setup Typ Max Unit

CIN Input Capacitance VIN = 0 6 7.5 pF

COUT Output Capacitance VOUT = 0 8.5 12 pF

CIN2 Control Pin Capacitance VIN = 0 7.5 9 pF

Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.

DATA RETENTION
Parameter Test Conditions Min Unit

150°C 10 Years
Minimum Pattern Data Retention Time
125°C 20 Years

34 Am29F800BT/Am29F800BB
 PRELIMINARY

PHYSICAL DIMENSIONS
TS 048
48-Pin Standard Thin Small Outline Package (measured in millimeters)
0.95
1.05

Pin 1 I.D.
1 48

11.90
12.10

0.50 BSC

24 25

18.30 0.05
18.50 0.15

19.80
20.20

16-038-TS48-2
0.08 TS 048
1.20 0.20 DT95
MAX 8-8-96 lv
0.10
0.21
0°
0.25MM (0.0098") BSC 5°

0.50
0.70

TSR048
48-Pin Reverse Thin Small Outline Package (measured in millimeters)
0.95
1.05

Pin 1 I.D.
1 48

11.90
12.10

0.50 BSC

24 25

18.30 0.05
18.50 0.15

19.80 SEATING PLANE

20.20

16-038-TS48
TSR048
0.08 DT95
1.20 0.20 8-8-96 lv
MAX 0.10
0.21
0°
0.25MM (0.0098") BSC 5°

0.50
0.70

Am29F800BT/Am29F800BB 35
 PRELIMINARY

PHYSICAL DIMENSIONS
SO 044
44-Pin Small Outline Package (measured in millimeters)
44 23

13.10 15.70
13.50 16.30

1 22
1.27 NOM.

TOP VIEW

28.00
28.40

2.17 0.10
2.80 0.21
2.45 MAX.
0°
SEATING 8° 0.60
0.35 0.10 PLANE 1.00
0.50 0.35
END VIEW
SIDE VIEW 16-038-SO44-2
SO 044
DA82
11-9-95 lv

36 Am29F800BT/Am29F800BB
 PRELIMINARY

REVISION SUMMARY FOR AM29F800B Erase Suspend Command

Global Changed to indicate that the device suspends the
erase operation a maximum of 20 µs after the rising
Added -55 speed option. Changed data sheet designa-
edge of WE#.
tion from Advance Information to Preliminary.
DC Characteristics
Sector Protection/Unprotection
Changed to indicate VID min and max values are 11.5
Corrected text to indicate that these functions can only
to 12.5 V, with a VCC test condition of 5.0 V. Added
be implemented using programming equipment.
typical values to TTL table. Revised CMOS typical
Table 1, Device Bus Operations standby current (ICC3).
Revised to indicate inputs for both CE# and RESET# Figure 14: Chip/Sector Erase Operation Timings;
are required for standby mode. Figure 19: Alternate CE# Controlled Write
Program Command Sequence Operation TImings

Changed to indicate Data# Polling is active for 2 µs Corrected hexadecimal values in address and data
after a program command sequence if the sector spec- waveforms. In Figure 19, corrected data values for chip
ified is protected. and sector erase.

Sector Erase Command Sequence and DQ3: Sector Erase and Programming Performance
Erase Timer Corrected word and chip programming times.
Corrected sector erase timeout to 50 µs.

Copyright © 1997 Advanced Micro Devices, Inc. All rights reserved.

AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

Am29F800BT/Am29F800BB 37