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CSC 1002 Computer Architecture Second Assignment

The document discusses the basic instruction cycle and bus architecture. It explains the fetch and execute cycles of the basic instruction cycle. It also describes the address, data and control lines of the bus and their functions. It discusses the benefits of multiple bus architecture over single bus architecture and distinguishes between dedicated and multiplexed bus types.

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Achyut Neupane
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67 views

CSC 1002 Computer Architecture Second Assignment

The document discusses the basic instruction cycle and bus architecture. It explains the fetch and execute cycles of the basic instruction cycle. It also describes the address, data and control lines of the bus and their functions. It discusses the benefits of multiple bus architecture over single bus architecture and distinguishes between dedicated and multiplexed bus types.

Uploaded by

Achyut Neupane
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Programme Name: BCS

Course Code: CSC 1002

Course Name: Computer Architecture

Assignment: Second

Date of Submission: 12 December 2021

Submitted By: Submitted To:

Student Name: Achyut Neupane Faculty Name: Amar Subedi

IUKL ID: Department: PO

Semester: 1st Semester

Intake: September 2021


Q. 1. The Central Processing Unit (CPU) processes all instruction in computers.
A
(a) Draw the diagram of basic instruction cycle.
Þ

Fig: Basic instruction cycle

(b) Explain the basic instruction cycle based on your diagram in (a).
Þ The processing that is going on during the execution of an instruction is
called basic instruction cycle. The CPU execute the cycle for each instruction
at a time. The basic instruction cycle is subdivided into two major cycles:
Fetch cycle and Execute cycle. The CPU execute the cycle at first by
fetching the instruction and then execute it. The process followed by the
basic instruction cycle are:
i. The processor fetches each instruction to be executed from memory at a
time.
ii. The CPU interprets the opcode and executes the fetched instruction
accordingly.

Q. 2. A bus is a communication pathway connecting two or more devices. A key


characteristic of a bus is that it is a shared transmission medium.
A
(a) Draw Bus Interconnection Scheme. Label each related computer components and
channel of bus/lines.
Þ

Fig: Bus interconnection scheme


(b) Describe THREE (3) channels bus lines functions.
Þ
i. Address Lines
® Address lines are the connection between CPU and main memory and
are used to identify address location in the main memory.
® No. of wires(width) determine the amount of memory a system can
address.
® They are unidirectional.
ii. Data Lines
® Data lines are the pathway used to move data and instructions among
system modules.
® No. of wires(width) determine the speed of data travelling.
® They are bi-directional.
iii. Control Lines
® Control lines are the physical connection between CPU and other
component and are used to access, control, and use the data and address
lines.
® They carry the information and status of various devices.
® They are unidirectional.

(c) Explain the TWO (2) benefits of using multiple bus architecture compared to a single
bus architecture.
Þ In the use of single bus architecture, one common bus is used to
communicate from one component to other. This created the bottleneck that
was eliminated by multiple bus architecture. In multiple bus architecture,
local bus connects the processor to cache memory and the cache is
connected to the system bus.
The two benefits of using multiple bus architecture compared to single bus
architecture are:
i. Propagation Delays
® Propagation delay mean the time taken by the connected device to
use the bus. The propagation delay was high when the devices
connected was larger in size. Since the cache is connected in
between, multiple devices can be connected simultaneously. This
leads to reducing the delays by increasing the access frequency
from CPU to main memory.
ii. Low Performance
® In single bus architecture, the main memory stores every information
and when needed, the processor accesses the main memory to
retrieve the stored information. With cache introduced in multiple
architecture, the cache stores the important information that can
be required in the next process. This reduces the need of main
memory for every CPU processes.
(d) Distinguish between Dedicated and Multiplexed Bus types.
Þ
Dedicated bus type Multiplexed bus type
• A single bus is assigned to one • A single bus is assigned to
function permanently. multiple functions.
• There are higher number of bus • There are fewer number of bus
lines. lines.
• High cost of transmission. • Low cost of transmission.
• Simple circuit design. • Complex circuit design.

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