Switching Power Supply Design: A Concise Practical Handbook: February 2022
Switching Power Supply Design: A Concise Practical Handbook: February 2022
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All content following this page was uploaded by Lazar Rozenblat on 18 February 2022.
OUTPUT POWER
DUTY CYCLE
In steady-state fixed frequency operation:
�2Po ∙ Lμ ∙ F/η
D=
Vin
Switching Power Supply Design: A Concise Practical Handbook
where D=t1/T (D<1).
OUTPUT VOLTAGE
TRANSFORMER
Peak primary current: I1PK =√(2Po/η·Lµ·F).
Peak secondary current: I2PK =I1pk∙N1/N2,
where N1/N2 - primary to secondary turns ratio.
η ∙ VIN_MIN2 · DLL 2
Lμ <
2Po ∙ F
where DLL – desired maximum duty cycle at low line (DLL <Dmax,
where Dmax – maximum duty cycle of PWM).
In most controllers Dmax is 0.45 to 0.99. If Dmax is close to 1.0, it is
common to set DLL around 0.7 to limit maximum FET voltage.
For selected Lμ, duty cycle at low line:
�2Po ∙ Lμ ∙ F/η
DLL =
VIN_MIN
Turns ratio is usually selected such that at low line and full load the
transformer will be near the boundary of DCM and CCM:
N1 DLL ∙ VIN_MIN
≈
N2 Vout ∙ (1 − DLL)
The core’s reset time (the time it takes the transformer to completely
demagnetize) is given by:
Lμ ∙ I1 pk
tRESET =
(N1/N2) ∙ Vout
4 8 ∙ Po3
I1_RMS_MAX = �
9 ∙ Lμ ∙ F ∙ η3 ∙ VIN_MIN2
SWITCH Q
Switching Power Supply Design: A Concise Practical Handbook
Peak current: IQ_PK=I1PK;
Conduction losses: PQ_COND= I1rms 2∙Rdson, where Rdson - drain to
source resistance of Q in on-state.
Peak plateau voltage: VQ_pk=VIN_MAX+ Vout·N1/N2.
RECTIFIER D1
Peak current: ID_ PK =I2PK;
Average current: ID_av=Iout;
Reverse voltage plateau: VD_PK= Vout+VIN_MAX∙N2/N1.
OUTPUT CAPACITOR Co
RMS current:
Ic_rms = �I2 rms 2 − Iout2
INPUT CURRENT
Average input current: IIN_AV=Vout∙Iout/(η·Vin);
AC component of input current, which is current through input
capacitor (not shown on the diagram): IIN_AC_RMS = I1_AC_RMS.