1.1 About The AXI Protocol: 1-2 Arm Ihi 0022B

The AXI protocol is designed for high-performance systems and includes features like separate address/control and data phases, burst transactions, multiple outstanding addresses, and out-of-order completion. It aims to enable high bandwidth and low latency while meeting requirements for a wide range of components.

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1.1 About The AXI Protocol: 1-2 Arm Ihi 0022B

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Introduction

1.1 About the AXI protocol

The AMBA AXI protocol is targeted at high-performance, high-frequency system
designs and includes a number of features that make it suitable for a high-speed
submicron interconnect.

The objectives of the latest generation AMBA interface are to:

• be suitable for high-bandwidth and low-latency designs
• enable high-frequency operation without using complex bridges
• meet the interface requirements of a wide range of components
• be suitable for memory controllers with high initial access latency
• provide flexibility in the implementation of interconnect architectures
• be backward-compatible with existing AHB and APB interfaces.

The key features of the AXI protocol are:

• separate address/control and data phases
• support for unaligned data transfers using byte strobes
• burst-based transactions with only start address issued
• separate read and write data channels to enable low-cost Direct Memory Access
(DMA)
• ability to issue multiple outstanding addresses
• out-of-order transaction completion
• easy addition of register stages to provide timing closure.

As well as the data transfer protocol, the AXI protocol includes optional extensions that
cover signaling for low-power operation.

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1.1 About The AXI Protocol: 1-2 Arm Ihi 0022B

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1.1 About The AXI Protocol: 1-2 Arm Ihi 0022B

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Introduction

1.1 About the AXI protocol

The objectives of the latest generation AMBA interface are to:

The key features of the AXI protocol are:

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