CY7C199D

256-Kbit (32K × 8) Static RAM

256-Kbit (32K × 8) Static RAM

Features Functional Description

■ Temperature range The CY7C199D is a high performance CMOS static RAM
❐ –40 °C to 85 °C organized as 32,768 words by 8-bits. Easy memory expansion is
provided by an active LOW chip enable (CE), an active LOW
■ Pin and function compatible with CY7C199C output enable (OE) and tri-state drivers. This device has an
■ High speed automatic power-down feature, reducing the power consumption
when deselected. The input and output pins (I/O0 through I/O7)
❐ tAA = 10 ns
are placed in a high impedance state when the device is
■ Low active power deselected (CE HIGH), the outputs are disabled (OE HIGH), or
❐ ICC = 80 mA at 10 ns during a write operation (CE LOW and WE LOW).
■ Low CMOS standby power Write to the device by taking chip enable (CE) and write enable
(WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7)
❐ ISB2 = 3 mA
is then written into the location specified on the address pins (A0
■ 2.0 V data retention through A14).
■ Automatic power-down when deselected Read from the device by taking chip enable (CE) and output
enable (OE) LOW while forcing write enable (WE) HIGH. Under
■ Complementary metal oxide semiconductor (CMOS) for these conditions, the contents of the memory location specified
optimum speed/power by the address pins appears on the I/O pins.
■ Transistor-transistor logic (TTL) compatible inputs and outputs The CY7C199D device is suitable for interfacing with processors
that have TTL I/P levels. It is not suitable for processors that
■ Easy memory expansion with CE and OE features require CMOS I/P levels. Please see Electrical Characteristics
■ Available in Pb-free 28-pin 300-Mil-wide molded small outline on page 4 for more details and suggested alternatives.
J-lead package (SOJ) and 28-pin thin small outline package For a complete list of related documentation, click here.
(TSOP) I packages

Logic Block Diagram

I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 38-05471 Rev. *N Revised March 22, 2019
 CY7C199D

Contents
Pin Configurations ........................................................... 3 Ordering Information ...................................................... 10
Selection Guide ................................................................ 3 Ordering Code Definitions ......................................... 10
Maximum Ratings ............................................................. 4 Package Diagrams .......................................................... 11
Operating Range ............................................................... 4 Acronyms ........................................................................ 13
Electrical Characteristics ................................................. 4 Document Conventions ................................................. 13
Capacitance ...................................................................... 5 Units of Measure ....................................................... 13
Thermal Resistance .......................................................... 5 Document History Page ................................................. 14
AC Test Loads and Waveforms ....................................... 5 Sales, Solutions, and Legal Information ...................... 16
Data Retention Characteristics ....................................... 6 Worldwide Sales and Design Support ....................... 16
Data Retention Waveform ................................................ 6 Products .................................................................... 16
Switching Characteristics ................................................ 7 PSoC® Solutions ...................................................... 16
Switching Waveforms ...................................................... 8 Cypress Developer Community ................................. 16
Truth Table ...................................................................... 10 Technical Support ..................................................... 16

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 CY7C199D

Pin Configurations
Figure 1. 28-pin SOJ pinout (Top View) Figure 2. 28-pin TSOP I pinout (Top View)

OE 22 21 A0
A1 23 20 CE
A2 24 19
A5 1 28 VCC I/O7
A3 25 18
A6 2 27 WE I/O6
A4 26 17 I/O5
A7 3 26 A4
A8 WE 27 16 I/O4
4 25 A3 VCC TSOP I
A9 28 15 I/O3
5 24 A2 A5 Top View
A10 A1 1 (not to scale) 14 GND
6 23 A6
A11 2 13 I/O2
7 22 OE A7
A12 3 12 I/O1
8 21 A0 A8
A13 4 11 I/O0
9 20 CE A9 5
A14 I/O7 10 A14
10 19 A10 6
I/O0 9 A13
11 18 I/O6 A11 7
I/O1 8 A12
12 17 I/O5
I/O2 13 16 I/O4
GND 14 15 I/O3

Selection Guide
Description -10 (Industrial) Unit
Maximum access time 10 ns
Maximum operating current 80 mA
Maximum CMOS standby current 3 mA

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 CY7C199D

Maximum Ratings DC input voltage [1] ............................. –0.5 V to VCC + 0.5 V

Output current into outputs (LOW) ............................. 20 mA
Exceeding the maximum ratings may impair the useful life of the
device. These user guidelines are not tested. Static discharge voltage
(per MIL-STD-883, method 3015) ........................ > 2,001 V
Storage temperature ................................ –65 C to +150 C
Latch-up current ................................................... > 140 mA
Ambient temperature
with power applied ................................... –55 C to +125 C
Operating Range
Supply voltage
Range Ambient Temperature VCC Speed
on VCC to relative GND [1] ...........................–0.5 V to +6.0 V
Industrial –40 C to +85 C 5 V  0.5 V 10 ns
DC voltage applied to outputs
in high Z State [1] ................................ –0.5 V to VCC + 0.5 V

Electrical Characteristics
Over the operating range

CY7C199D-10
Parameter Description Test Conditions Unit
Min Max
VOH Output HIGH voltage IOH = –4.0 mA 2.4 – V
IOH = –0.1mA [2]
– 3.4
VOL Output LOW voltage IOL = 8.0 mA – 0.4 V
VIH Input HIGH voltage [1] 2.2 VCC + 0.5 V
VIL [1]
Input LOW voltage –0.5 0.8 V
IIX Input leakage current GND < VI < VCC –1 +1 µA
IOZ Output leakage current GND < VO < VCC, output disabled –1 +1 µA
ICC VCC operating supply current VCC = VCC(max), IOUT = 0 mA, 100 MHz – 80 mA
f = fmax = 1/tRC
83 MHz – 72 mA
66 MHz – 58 mA
40 MHz – 37 mA
ISB1 Automatic CE power-down VCC = VCC(max), CE > VIH, – 10 mA
current – TTL Inputs VIN > VIH or VIN < VIL, f = fmax
ISB2 Automatic CE power-down VCC = VCC(max), CE > VCC – 0.3 V, – 3 mA
current – CMOS Inputs VIN > VCC – 0.3 V or VIN < 0.3 V, f = 0

Note
1. VIL(min) = –2.0 V and VIH(max) = VCC + 1 V for pulse durations of less than 5 ns.
2. Please note that the maximum VOH limit does not exceed minimum CMOS VIH of 3.5 V. If you are interfacing this SRAM with 5 V legacy processors that require a
minimum VIH of 3.5 V, please refer to Application Note AN6081 for technical details and options you may consider.

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 CY7C199D

Capacitance
Parameter [3] Description Test Conditions Max Unit
CIN Input capacitance TA = 25 C, f = 1 MHz, VCC = 5.0 V 8 pF
COUT Output capacitance 8 pF

Thermal Resistance
Parameter [3] Description Test Conditions 28-pin SOJ 28-pin TSOP I Unit
JA Thermal resistance Still air, soldered on a 3 × 4.5 inch, 59.16 54.65 C/W
(junction to ambient) four-layer printed circuit board
JC Thermal resistance 40.84 21.49 C/W
(junction to case)

AC Test Loads and Waveforms

Figure 3. AC Test Loads and Waveforms [4]

Z = 50  ALL INPUT PULSES

OUTPUT 3.0 V
90% 90%
50  10% 10%
30pF*
GND
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE 1.5 V
TEST ENVIRONMENT Rise Time: 3 ns Fall Time: 3 ns
(a) (b)

High Z characteristics:
R1 480 
5V
OUTPUT

R2
5 pF
255 
INCLUDING
JIG AND SCOPE
(c)

Notes
3. Tested initially and after any design or process changes that may affect these parameters.
4. AC characteristics (except high Z) are tested using the load conditions shown in Figure 3 (a). High Z characteristics are tested for all speeds using the test load
shown in Figure 3 (c).

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 CY7C199D

Data Retention Characteristics

Over the operating range

Parameter Description Conditions Min Max Unit

VDR VCC for data retention 2.0 – V
ICCDR Data retention current VCC = VDR = 2.0 V, CE > VCC – 0.3 V, – 3 mA
VIN > VCC – 0.3 V or VIN < 0.3 V
tCDR [5] Chip deselect to data retention 0 – ns
time
tR [6] Operation recovery time 15 – ns

Data Retention Waveform

Figure 4. Data Retention Waveform
DATA RETENTION MODE
VCC 4.5 V VDR > 2 V 4.5 V
tCDR tR
CE

Notes
5. Tested initially and after any design or process changes that may affect these parameters.
6. Full device operation requires linear VCC ramp from VDR to VCC(min) > 50 µs or stable at VCC(min) > 50 µs.

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 CY7C199D

Switching Characteristics
Over the operating range
CY7C199D-10
Parameter [7] Description Unit
Min Max
Read Cycle
tpower [8] VCC(typical) to the first access 100 – s
tRC Read cycle time 10 – ns
tAA Address to data valid – 10 ns
tOHA Data hold from address change 3 – ns
tACE CE LOW to data valid – 10 ns
tDOE OE LOW to data valid – 5 ns
tLZOE [9] OE LOW to low Z 0 – ns
tHZOE [9, 10] OE HIGH to high Z – 5 ns
tLZCE [9] CE LOW to low Z 3 – ns
tHZCE [9, 10] CE HIGH to high Z – 5 ns
tPU [11] CE LOW to power-up 0 – ns
tPD [11] CE HIGH to power-down – 10 ns
Write Cycle [12, 13]
tWC Write cycle time 10 – ns
tSCE CE LOW to write end 7 – ns
tAW Address setup to write end 7 – ns
tHA Address hold from write end 0 – ns
tSA Address setup to write start 0 – ns
tPWE WE pulse width 7 – ns
tSD Data setup to write end 6 – ns
tHD Data hold from write end 0 – ns
tHZWE [9] WE LOW to high Z – 5 ns
tLZWE [9, 10] WE HIGH to low Z 3 – ns

Notes
7. Test conditions assume signal transition time of 3 ns or less for all speeds, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the
specified IOL/IOH and 30-pF load capacitance.
8. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed.
9. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
10. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of Figure 3 on page 5. Transition is measured 200 mV from steady-state voltage.
11. This parameter is guaranteed by design and is not tested.
12. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write
by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the write.
13. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.

Document Number: 38-05471 Rev. *N Page 7 of 16

 CY7C199D

Switching Waveforms
Figure 5. Read Cycle No. 1 (Address Transition Controlled) [14, 15]
tRC

ADDRESS

tAA
tOHA

DATA OUT PREVIOUS DATA VALID DATA VALID

Figure 6. Read Cycle No. 2 (OE Controlled) [15, 16]

tRC
CE

tACE
OE

tDOE tHZOE
tHZCE
tLZOE HIGH
HIGH IMPEDANCE IMPEDANCE
DATA OUT DATA VALID
tLZCE
tPD
tPU
VCC ICC
SUPPLY 50% 50%
CURRENT ISB

Notes
14. Device is continuously selected. OE, CE = VIL.
15. WE is HIGH for read cycle.
16. Address valid prior to or coincident with CE transition LOW.

Document Number: 38-05471 Rev. *N Page 8 of 16

 CY7C199D

Switching Waveforms (continued)

Figure 7. Write Cycle No. 1 (CE Controlled) [17, 18, 19]
tWC

ADDRESS

CE tSCE
tSA
tAW tHA

WE
tSD tHD

DATA I/O DATA IN VALID

Figure 8. Write Cycle No. 3 (WE Controlled, OE LOW) [19, 20]

tWC

ADDRESS

CE

tAW tHA
tSA
WE

tSD tHD

DATA IO NOTE 21 DATAIN VALID

tHZWE tLZWE

Notes
17. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate
a write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the write.
18. Data I/O is high impedance if OE = VIH.
19. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
20. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
21. During this period the I/Os are in the output state and input signals should not be applied.

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 CY7C199D

Truth Table
CE WE OE Inputs/Outputs Mode Power
H X X High Z Deselect/power-down Standby (ISB)
L H L Data out Read Active (ICC)
L L X Data in Write Active (ICC)
L H H High Z Deselect, output disabled Active (ICC)

Ordering Information
Cypress offers other versions of this type of product in many different configurations and features. The following table contains only
the list of parts that are currently available. For a complete listing of all options, visit the Cypress website at http://www.cypress.com
and refer to the product summary page at http://www.cypress.com/products or contact your local sales representative.
Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives and distributors. To find the office
closest to you, visit us at http://www.cypress.com/go/datasheet/offices.
Speed Package Operating
Package Type
(ns) Ordering Code Diagram Range
10 CY7C199D-10VXI 51-85031 28-pin Molded SOJ (300 Mils) (Pb-free) Industrial
CY7C199D-10ZXI 51-85071 28-pin TSOP I (Pb-free)
Please contact your local Cypress sales representative for availability of these parts.

Ordering Code Definitions

CY 7 C 1 9 9 D - XX X X I

Temperature Grade:
I = Industrial
Pb-free
Package Type: V or Z
V = 28 pin Molded SOJ (300 Mils)
Z = 28 pin TSOP I
Speed Grade: 10 ns
Process Technology: D = 90 nm
Bus Width: 9 = × 8
Density: 9 = 256K
Family Code: 1 = Fast SRAM Family
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress

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 CY7C199D

Package Diagrams
Figure 9. 28-pin SOJ (300 Mils) V28.3 (Molded SOJ V21) Package Outline, 51-85031

51-85031 *F

Document Number: 38-05471 Rev. *N Page 11 of 16

 CY7C199D

Package Diagrams (continued)

Figure 10. 28-pin TSOP I (8 × 13.4 × 1.2 mm) Z28R (Standard) Package Outline, 51-85071

51-85071 *J

Document Number: 38-05471 Rev. *N Page 12 of 16

 CY7C199D

Acronyms Document Conventions

Acronym Description Units of Measure
CE Chip Enable Symbol Unit of Measure
CMOS Complementary Metal Oxide Semiconductor °C degree Celsius
I/O Input/Output µA microampere
OE Output Enable µs microsecond
SOJ Small Outline J-lead mA milliampere

SRAM Static Random Access Memory mm millimeter

ns nanosecond
TSOP Thin Small Outline Package
pF picofarad
TTL Transistor-Transistor Logic
V volt
WE Write Enable
W watt

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 CY7C199D

Document History Page

Document Title: CY7C199D, 256-Kbit (32K × 8) Static RAM
Document Number: 38-05471
Orig. of Submission
Revision ECN Description of Change
Change Date
** 201560 SWI 01/09/2004 Advance Information data sheet for C9 IPP.
*A 233728 RKF 06/14/2004 DC parameters modified as per EROS (spec 01-02165).
Updated Ordering Information:
Updated part numbers.
*B 262950 RKF 09/11/2004 Changed status from Advance Information to Preliminary.
Removed 28-pin LCC related information in all instances across the document.
Updated Data Retention Characteristics:
Updated details in “Min” and “Max” columns corresponding to ICCDR and tR
parameters.
Updated Data Retention Waveform:
Updated Figure 4.
Updated Switching Characteristics:
Added tpower parameter and its corresponding details.
Updated Ordering Information:
No change in part numbers.
Shaded the table.
Updated Package Diagrams:
spec 51-85014 – Changed revision from *C to *D.
Removed spec 51-80067 **.
*C 307594 RKF 01/12/2005 Removed 20 ns speed bin related information in all instances across the
document.
*D 820660 VKN 03/07/2007 Changed status from Preliminary to Final.
Removed 12 ns and 15 ns speed bins related information in all instances
across the document.
Removed Commercial Temperature Range related information in all instances
across the document.
Removed 28-pin PDIP and 28-pin SOIC Packages related information in all
instances across the document.
Updated Selection Guide:
Removed “L” related information from the part numbers.
Updated Electrical Characteristics:
Updated Note 1.
Referred Note 1 in description of VIH and VIL parameters.
Updated details in “Test Conditions”, “Min” and “Max” columns corresponding
to ICC parameter.
Updated Thermal Resistance:
Replaced TBD with values for 28-pin SOJ and 28-pin TSOP I packages.
Updated Ordering Information:
Updated part numbers.
Updated to new template.
*E 2745093 VKN 07/28/2009 Added 28-pin SOIC Package related information in all instances across the
document.
Added Automotive-E Temperature Range related information in all instances
across the document.
Added 25 ns speed bin related information in all instances across the
document.
Updated Electrical Characteristics:
Changed minimum value of VIH parameter from 2.0 V to 2.2 V corresponding
to 10 ns speed bin.

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 CY7C199D

Document History Page (continued)

Document Title: CY7C199D, 256-Kbit (32K × 8) Static RAM
Document Number: 38-05471
Orig. of Submission
Revision ECN Description of Change
Change Date
*E (cont.) 2745093 VKN 07/28/2009 Updated Switching Characteristics:
Changed minimum value of tSD parameter from 5 ns to 6 ns corresponding to
10 ns speed bin.
Changed maximum value of tHZWE parameter from 6 ns to 5 ns corresponding
to 10 ns speed bin.
*F 2897087 AJU 03/22/2010 Updated Ordering Information:
Updated part numbers.
Updated Package Diagrams:
spec 51-85031 – Changed revision from *C to *D.
Removed spec 51-85026 *D.
spec 51-85071 – Changed revision from *G to *H.
*G 3023234 RAME 09/06/2010 Updated Switching Characteristics:
Changed maximum value of tDOE parameter from 10 ns to 11 ns corresponding
to 25 ns speed bin.
Updated Ordering Information:
Updated part numbers.
Added Ordering Code Definitions.
Added Acronyms and Units of Measure.
*H 3130763 PRAS 01/07/2011 Removed Automotive-E Temperature Range related information in all
instances across the document.
Dislodged Automotive information to a new datasheet (001-65530).
Completing Sunset Review.
*I 3271782 PRAS 06/02/2011 Updated Functional Description:
Updated description.
Updated Package Diagrams:
spec 51-85071 – Changed revision from *H to *I.
Removed spec 51-85026 *E.
Updated to new template.
*J 4033580 MEMJ 06/19/2013 Updated Functional Description:
Updated description.
Updated Electrical Characteristics:
Added one more Test Condition “IOH = –0.1 mA” for VOH parameter and added
maximum value corresponding to that Test Condition.
Added Note 2 and referred the same note in maximum value for VOH parameter
corresponding to Test Condition “IOH = –0.1 mA”.
Updated Package Diagrams:
spec 51-85031 – Changed revision from *D to *E.
*K 4347624 MEMJ 04/15/2014 Updated Package Diagrams:
spec 51-85071 – Changed revision from *I to *J.
Completing Sunset Review.
*L 4576526 MEMJ 11/21/2014 Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
*M 5725425 VINI 05/04/2017 Updated Package Diagrams:
spec 51-85031 – Changed revision from *E to *F.
Updated to new template.
Completing Sunset Review.
*N 6518606 VINI 03/22/2019 Updated to new template.
Completing Sunset Review.

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 CY7C199D

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Document Number: 38-05471 Rev. *N Revised March 22, 2019 Page 16 of 16