INTEGRATED CIRCUITS

AN214
74F extended octal-plus family applications

June 1988
(Revised June 1996)


 
 
Philips Semiconductors Application note

74F extended octal-plus family applications AN214

74F Extended Octal-Plus Family Features “light-load” inputs, “broadside” design and high functional
• 8-, 9-, and 10-bit “Light-Load” bus products density/performance of the family make this product line ideal for
buffering the limited drive capabilities of standard, custom and
– Buffers/Drivers semicustom MOS VLSI devices to the rigorous environments of
With and without latches or registers today’s leading edge high performance logic designs. The family
With and without 8-bit parity checker/generator also is an excellent choice for all general interface applications.
– Transceivers
“Flow-Through” Design
With and without dual registers The “flow-through” or “broadside” chip layout/package design is
With and without 8-bit parity checker/generator illustrated in Figure 1 showing the block diagrams and pin
• Patented “Light-Load” inputs: configurations of the 74F828 10-bit Inverting buffer. Note that all of
these “broadside” designs allow logic signals to flow into one side
– Input Current = ±20µA per input and out of the other without crossing or folding back on signal paths
– Transceiver I/O pins = ±70µA such as the 74F240 Octal Buffers (Figure 2). If you compare the
• High performance output drive currents: physical layout requirements of the path of PC board bus lines for
the 74F828 to that of the 74F240’s “zig-zag” path, you will see the
– IOL = 64mA/48mA @ ±5%/10% VCC significant advantages of the 74F Extended Octal-Plus Family’s
– IOH = –15mA/–3mA @ ±5%/10% VCC “flow-through” design in simplifying the design and layout of large,
• “Flow-through” or “broadside” I/O pin configuration high density, bus-oriented PC boards.

• Ideal for MOS CPU, peripherals and semi-custom bus interface The 24-pin, 300mil-wide, Slip-DIP Solution
With the advent of advanced Schottky TTL technology came the
• 24-pin, 300mil-wide, plastic slim-DIPs ability to significantly increase the functional density of standard
• High performance buffers — tP(max) = 7.5ns logic building blocks. However, not until the development of the
24-pin, 300mil-wide, Slim-DIP package was it possible to take full
• High performance latches/registers — fT = 100MHz advantage of these new chip densities. The entire family provides
significant advantages in package count, pin count and packing
Introduction density when compared to older technologies. Further density
The 74F Extended Octal-Plus Family incorporates all of the latest enhancements can be achieved by using Philips surface mounted
Philips Semiconductors octal, 9-bit and 10-bit buffer, transceiver, packages.
latch and register functions. all devices in this family utilize the
By combining high functional density into a 24-pin 300mil-wide
Philips Semiconductors patented “Light-Load” NPN, ±20µA input
Slim-DIP package, the Philips Semiconductors 74F Extended
current structure and have “flow-through” or “broadside” input/output
Octal-Plus Family allows the reduction of PC board parts count and
pin configurations where the inputs and outputs are lined-up on
cost while optimizing layout with “broadside” chip designs, reducing
opposite sides of a standard 24-pin Slim-DIP package. The
total system power dissipation and increasing system reliability.

OE0 1 24 VCC

D0 2 23 O0 OEa 1 20 VCC
D1 3 22 O1 Ia0 2 19 OEb
D2 4 21 O2 Yb0 3 18 Ya0
D3 5 20 O3 Ia1 4 17 Ib0
D4 6 19 O4 Yb1 5 16 Ya1
D5 7 18 O5 Ia2 6 15 Ib1
D6 8 17 O6 Yb2 7 14 Ya2
D7 9 16 O7 Ia3 8 13 Ib2
D8 10 15 O8 Yb3 9 12 Ya3
D9 11 14 O9 GND 10 11 Ib3
GND 12 13 OE1

SF01329 SF01330

Figure 1. 74F828 Broadside Pin Configuration Figure 2. 74F240 ’Zig-Zag” Pin Configuration

June 1988 2 Revised: June 1996

Philips Semiconductors Application note

74F extended octal-plus family applications AN214

EN VCC

D5 D6 D13

R1 R9 R10 R11 R14

6K 2.8K 2.8K 2.8K

D9 Q12

D8 Q13

D10
YIN Q1 D4 YOUT
Q8 Q9 Q10
Q1A
Q2 IOLoptions:
D3 1) If IOH/IOL = –15/64 mA
D7 R14 = 12 Ω
R11 = 2.8K Ω
R5 R6 R7
Q11
R10 = 2.8K Ω
5K 6K 7.5K R12 = 500 Ω
2) If IOH/IOL = –3/24 mA
R12 R13
Q4 Q6 500 10K R14 = 30 Ω
R11 = 5K Ω
D1 D2 Q3 Q5 R8 D11 R10 = 5K Ω
D12
2K R12 = 2K Ω
R2 R3 R4 Q7
50 10K 50

SF01331

Figure 3. 74F455 Buffer/Drive Cell Circuit Diagram

The 8-, 9-, and 10-bit Series 24-pin Solution Input Structures
Whether your system requires an 8–, 9-, or 10-bit bus interface, the Referring to Figure 3, the 74F455 Inverting Buffer/Driver Cell Circuit
Extended Octal-Plus Family has standardized solutions in Diagram is an example of the family’s input and output circuitry. The
24-pin/Slim-DIP/Broadside input/output packages with corner power patented Philips Semiconductors “Light-Load” NPN input structure
supply pins (12 & 24) and standard designations for common control (Q1/23/4/5, R1/2/3/4/5/6 and D4) and turn-OFF speed-up circuit (Q2
functions located at or near the package corners. Octals offer more and D2/3) are used throughout the 74F Extended Octal-Plus Family.
mode control inputs than do the 9- or 10-bit products. Virtually all the “Light-Load” NPN input is actually a high speed, differential
family devices with 3-State outputs are guaranteed to source/sink amplifier with the reference side, the anode of D4, clamped at two
–15/64mA @ VOH/VOL = 2.0/0.55V (except for the 74F841–846 diode voltage drops above ground (BE junctions of Q8/9/10 and Q
Latched Drivers, which are spec’ed at –15mA/48mA). The AN port 11 of
1.4V at 25°C). When the VIH rises above this clamp voltage,
outputs of several of the family’s transceivers are guaranteed to the BE junction of Q1 is forward based allowing beta amplified, CE
supply –3mA/48mA). current to flow into the <1.0mA constant current source, Q3 (driven
by Q4/5 and R2/3/4/5/6). The beta of Q1 is guaranteed, by design,
The Octal Parity Bus Series offers several notable exceptions to the
to be >50, thereby guaranteeing that the input base bias current will
above standard pinouts. This series has three parts with two
be <20µA. The emitter of Q1 rises to 1VBE (
300mV) below the
center-package ground pins to minimize ground-bounce noise. All
VIH, reverse biasing D4 and permitting C8/9/10 base bias current to
outputs (except the AN port of the 74F657 Parity Bus Transceiver
flow through R1.
spec’ed at –3mA/24mA) are guaranteed to source/sink more than
–15mA/64mA. The patented turn-OFF circuit consisting of Q2 and D2/3 produces a
dynamic speed to help turn Q8/9/10 OFF quickly. During the time
Current PC board, multi-layer technology make is possible to take
that the Q1 is turned-ON (input = VIH >2.0V), the revers-biased
into consideration the physical location of input/output pins,
Schottky diode, D2, acting as a capacitor, will be charged to the
transmission line characteristics and supply power distribution.
voltage at the emitter of Q1A or 1VBE voltage drop below the input
Lining up all inputs and output on opposite sides of the package
(>2.0 – 1VBE). When the input is switched to <VIL (or <0.8V), the D2
allows the address, data and control bus signal to flow in a direct
stored charge discharges through the BE of Q2. Q2 CE current
physical path from the µP CPU through the bus interface chips and
through D3 rapidly turns Q8/9/10 OFF.
onto the appropriate bus. This “broadside” bus design approach
produces very clean PC board layouts and may, in fact eliminate These circuit innovations produce high performance, very low input
and entire PC board interconnection layer. Standardization of power bias current (±20µA) gate inputs. This input leakage represents a
supply, mode control and input/output pins, whether 8-, 9-, or 10-bit 30X reduction over the standard 74F family’s 600µA input current
bus functions, permits simplified, structured PC board layout. with virtually no loss in speed. The 74F Extended Octal-Plus

June 1988 3
Philips Semiconductors Application note

74F extended octal-plus family applications AN214

Transceivers have an input loading current of ±70µA, which is the output structures. These diodes block leakage current from flowing
combination of the “Light-Load” NPN input structure’s ±20µA and the into the outputs when VCC is either open or shorted to ground.
3-State Hi-Z output’s ±50µA leakage current.
This gives a very important advantage of being able to power down
The low “Light-Load” input current and high speed performance a PCB (or several PCBs) without disabling the bus and even without
makes this family ideal for interfacing to low drive capability, slower producing any glitching on the bus due to an undesired change in
MOS CPU, peripherals and semi-custom chips used in most of the output state of the device being powered down.
today’s state-of-the-art logic designs. Besides very low input current
The output short-circuit (IOS) limiting resistor (R14), the
requirements, this “Light-Load” input has another significant
anode-to-cathode resistance/voltage drop of D13 and the
advantage over “traditional” input structures: Very low input
collector-to-emitter/base-to-emitter resistance/voltage drop of Q13
capacitance (smaller stored charge) due to very small device
limit the amount of current that can be sourced from a HIGH level
geometries. Therefore, when Extended Octal-Plus devices are
output at a specified VOH. For most of the parts in the family, R14 is
connected to a bus, they present less AC bus loading and do not
equal to 12Ω. the AN port of several of the transceivers utilize an
significantly lower the characteristic impedance of the bus to the
R14 of 30Ω producing IOH (@ VOH = 20V) of –6mA versus –15mA
extent “traditional” input structures do. Thus, the amount of the AC
from the BN ports 12Ω R14.
current a bus driver has to produce to change the state of the bus is
lowered and in many cases can make a difference between incident The output HIGH level sourcing current, IOH, at a specified output
wave switching of the bus versus losing time waiting for a reflected voltage, VOH, can be calculated by subtracting the voltage drops of
wave. D13, the pull-up darlington transistor, Q12/13, and the desired VOH
level from VCC and dividing by the value of R14 plus the
The Philips Semiconductors 74F “Light-Load” input structure is
anode-to-cathode resistance of D13 and the collector-to-emitter/
discussed in more detail in Application Note AN215.
base-to-emitter resistance.
Output Drive Capabilities Assumptions:
Virtually all devices in the EXtended Octal-Plus Family are VD13
0.5V @ RON = 3Ω @ 25°C),
guaranteed to source/sink more than –15mA/64mA @ VOHVOL = VQ12/13
1.2V @ RON = 8Ω @ 25°C)
2.0/0.55V. One exception is the 74F841-thru-846 Series of Bus IOH = 1[VCC–(VD13 + VQ12/Q13 + VOH)]/(R14 + RD13 + RQ13).
Interface Latches which are specified at –15/48mA. Several of the IOH(R14 = 12Ω) = –[4.5V–(0.5V + 1.2V + 2.0V)]/23Ω = –35mA
family’s transceiver products have lower AN output drive capabilities IOH(R14 = 30Ω) = –[4.5V–(0.5V + 1.2V + 2.0V)]/41Ω = –20mA
to reduce package power dissipation. Refer to Tables 1 and 3. IOS = IOH @ VOH = 0.0V and VCC = 5.5V
For example, the 74F657 Parity Bus Transceiver has two output IOS(R14 = 12Ω) = –[5.5V–(0.5V + 1.2V)]/23Ω = –165mA
ports with different capacities: The AN port is guaranteed to IOS(R14 = 30Ω) = –[5.5V–(0.5V + 1.2V)]/41Ω = –93mA
source/sink –3mA/24mA (IOH/IOL = 2.4/0.50V), and the BN port has Obviously, we have been very conservative in the IOH specification
an output drive capability of –15mA/64mA at 2.0V/0.55V. The to guardband against all conditions of temperature and
74F657’s AN port is designed to interface the chip side of the PC input/output/supply voltage levels. The RON resistances of the
board to the backplane bus, while the BN port is capable of driving a output pullup transistors and blocking diode are large enough to
transmission line or bus backplane line. prevent IOS from exceeding –225mA for R14 = 12Ω and –150mA for
Referring to Figure 3, all of the Family’s 3-State, totem-pole output R14 = 30Ω. (Refer to Table 1.)
structures have a schottky blocking diode, D13, in their pull-up

Table 1. Family Output Drive Capabilities Using the 74F657 Parity Bus Transceiver
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions, VIL = MAX and VIH = MIN)
SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IOH = –3mA ±10% VCC 2.4 V
All outputs
IOH = –3mA ±5% VCC 2.7 3.4 V
VOH
O High level output voltage
High-level
IOH = –15mA ±10% VCC 2.0 V
BN port,
port PARITY
PARITY, ERROR
IOH = –15mA ±5% VCC 2.0 V
IOL = 24mA ±10% VCC 0.35 0.50 V
AN port
IOL = 24mA ±5% VCC 0.35 0.50 V
VOL
O Low level output voltage
Low-level
IOL = 48mA ±10% VCC 0.40 0.55 V
BN port,
port PARITY
PARITY, ERROR
IOL = 48mA ±5% VCC 0.40 0.55 V
AN output High level short circuit current (R14 = 30Ω) VCC = MAX –150 mA
IOS
BN output High level short circuit current (R14 = 12Ω) VCC = MAX –225 mA

June 1988 4
Philips Semiconductors Application note

74F extended octal-plus family applications AN214

F821/2 F823/4 F825/6 F825/6 F823/4 F821/2

F841/2 F843/4 F845/6 F845/6 F843/4 F841/2

OE OE OE0 1 24 VCC VCC VCC

D0 D0 OE1 2 23 OE2 O0/O0 O0/O0

D1 D1 D0 3 D Q 22 O0/O0 O1/O1 O1/O1

C R
D2 D2 D1 4 D Q 21 O1/O1 O2/O2 O2/O2
C R
D3 D3 D2 5 D Q 20 O2/O2 O3/O3 O3/O3
C R
D4 D4 D3 6 D Q 19 O3/O3 O4/O4 O4/O4
C R
D5 D5 D4 7 D Q 18 O4/O4 O5/O5 O5/O(5
C R
D6 D6 D5 8 D Q 17 O5/O5 O6/O6 O6/O6
C R
D7 D7 D6 9 D Q 16 O6/O6 O7/O7 O7/O7
C R
D8 D8 D7 10 D Q 15 O7/O7 O8/O8 O8/O8
C R
D9 MR MR 11 14 EN EN O9/O9

CP→821–6
GND GND GND 12 13 CP/LE CP/LE CP/LE LE→841–6

SF01332

Figure 4. 74F82X and 74F84X Registered/Latched Buffer Pin Configurations

F827/8 F861/2 F863/4 F863/4 F861/2 F827/8

Buffers Xcvrs Xcvrs Xcvrs Xcvrs Buffers
10-bit 10-bit 9-bit 9-bit 10-bit 10-bit

OE0 OEBA OEBA0 1 24 VCC VCC VCC

D0 A0 A0 2 23 B0/B0 B0/B0 O0/O0

D1 A1 A1 3 22 B1/B1 B1/B1 O1/O1

D2 A2 A2 4 21 B2/B2 B2/B2 O2/O2

D3 A3 A3 5 20 B3/B3 B3/B3 O3/O3

D4 A4 A4 6 19 B4/B4 B4/B4 O4/O4

D5 A5 A5 7 18 B5/B5 B5/B5 O5/O(5

D6 A6 A6 8 17 B6/B6 B6/B6 O6/O6

D7 A7 A7 9 16 B7/B7 B7/B7 O7/O7

D8 A8 A8 10 15 B8/B8 B8/B8 O8/O8

D9 A9 OEBA1 11 14 OEAB0 B9/B9 O9/O9

GND GND GND 12 13 OEAB1 CP/LE CP/LE

SF01333

Figure 5. 74F827/8 and 74F861–4 Buffers and Transceivers Pin Configurations

June 1988 5
Philips Semiconductors Application note

74F extended octal-plus family applications AN214

74F646A–649A 74F651A–654A
21 (74F646A shown) (74F651A shown)
OE
21
3 OEBA
DIR
23 OEAB 3
CPBA
22 CPBA 23
SBA
22
CPAB 1 SBA
CPAB 1
2 2
SAB SAB

I OF 8 CHANNELS D I OF 8 CHANNELS D
C C

4
4 A0 20
A0 20 B0
B0 D
D
C
C

TO 7 OTHER CHANNELS TO 7 OTHER CHANNELS

SF01334

Figure 6. 74F646A–649A and 74F651A–654A Registered Transceivers Simplified Logic Block Diagrams

F646A/7A F648A/9A F651A/3A F652A/4A F652A/4A F651A/3A F648A/9A F646A/7A

3-St/OC 3-St/OC 3-St/OC 3-St/OC 3-St/OC 3-St/OC 3-St/OC 3-St/OC
CPAB CPAB OEBA OEBA0 1 24 VCC VCC VCC VCC

SAB SAB SAB SAB 2 23 CPBA CPBA CPBA CPBA

DIR DIR OEAB OEAB 3 22 SBA SBA SBA SBA

A0 A0 A0 A0 4 21 OEBA OEBA OE OE
SEE BLOCK DIAGRAM

A1 A1 A1 A1 5 20 B0 B0 B0 B0

A2 A2 A2 A2 6 19 B1 B1 B1 B1

A3 A3 A3 A3 7 18 B2 B2 B2 B2

A4 A4 A4 A4 8 17 B3 B3 B3 B3

A5 A5 A5 A5 9 16 B4 B4 B4 B4

A6 A6 A6 A6 10 15 B5 B5 B5 B5

A7 A7 A7 A7 11 14 B6 B6 B6 B6

GND GND GND GND 12 13 B7 B7 B7 B7

SF01335

Figure 7. 74F646A–649A and 74F651A–654A Dual Registered Transceivers Pin configurations

June 1988 6
Philips Semiconductors Application note

74F extended octal-plus family applications AN214

REAL TIME BUS TRANSFER REAL TIME BUS TRANSFER STORAGE FROM TRANSFER STORED DATA
BUS B TO BUS A BUS A TO BUS B A, B, OR A AND B TO A AND/OR B

BUS A BUS B BUS A BUS B BUS A BUS B BUS A BUS B

OEAB OEBA CPAB CPBA SAB SBA OEAB OEBA CPAB CPBA SAB SBA OEAB OEBA CPAB CPBA SAB SBA OEAB OEBA CPAB CPBA SAB SBA

L L X X X L H H X X L X X H ↑ X X X H L H or L H or L H H
L X X ↑ X X
L H ↑ ↑ X X
SF00409

Figure 8. 74F651A–654A Registered Transceivers Storage Options (74F646A–649A not shown)

Table 2. Parity Bus Family versus the Competition

TOTAL # tPDmax* tPDmax* POWER BROADSIDE
PART NUMBER DESCRIPTION ICCmax**
OF PINS IN to OUT IN to PARITY PINS DESIGN
74F455/F456 24 7.5ns 16.0ns 110mA Center Yes
vs
vs. Octal Parity Buffer
74F240/F244 + 74F280 38 7.5ns 14.5ns 125mA Corner No
74F655A/F656A 24 7.5ns 16.0ns 110mA Corner Yes
vs
vs. Octal Parity Buffer
74F240/F244 + 74F280 38 7.5ns 14.5ns 125mA Corner No

74F657 24 7.5ns 16.0ns 110mA Center Yes

vs.
Octal Parity Transceiver
74F240/F245 + 74F280
+ 1 AND gate 38 8.0ns 14.5ns 125mA Corner No
NOTES:
* Propagation delays of DATA IN-to-DATA OUT and IN-to-PARITY OUT, Tamb = 0°C to 70°C, VCC = +5.0V ±10%,
Output Load = CL = 50pF, and RL = 500Ω.
** Worst case power, Tamb = 0°C to 70°C, VCC = +5.0V ±10%, Output Load = CL = 50pF, and RL = 500Ω.

74F821–74F863 Series Registered Transceiver Series

The 74F821 through 74F863 Series of Octal 9-bit and 10-bit Buffers, the 74F646A–649A and 74F651A–654A Octal Dual-Registered
Latch Buffers, Register Buffers and Transceivers are standardized Transceivers offer a “Light-Load” combination of a 74F245 type
around the AMD 298XX series with one significant difference—the transceiver with two 74F373/374 type octal registers within a 24-pin
Philips Semiconductors “Light-Load” NPN input offers a 50:1 Slim-DIP broadside input/output package. This series offers a
reduction in input loading (1000µA vs. 20µA). This series illustrates significant 6:1 package count reduction advantage over older
the standardized on 24-pin/300mil-wide Slim-DIP packages, technologies.
“broadside” input/output pinouts and control function pins. All
Figure 6 shows the 74F646A and 74F651A Transceivers Simplified
74F8XX 3-State outputs are guaranteed to source/sink
Block Diagrams, and this series’ pin configurations are depicted in
–15mA/64mA, except for the 74F84X Latched Buffers, which are
Figure 7. Figure 8 graphically illustrates four optional storage and
specified at –15mA/48mA.
transfer modes of the 74F651A Octal, Non-Inverting, 3-State,
The logic diagram and pin configurations of the 74F828 Dual-Registered Transceiver. The 74F654A will be used to explain
Non-Inverting 10-bit Buffer (Figure 1) and the 74F821–826 and the operation of the entire series. The 74F646A/648A (3-State,
74F841–846 Registered/Latched Buffers (Figure 4) are excellent INV/NINV) and the 74F647/649 (O.C., INV/NINV) Octal
illustrations of the standardized pin configuration illustrating Dual-Registered Transceivers offer optional signal direction control
“broadside” chip design. logic and output enable to the 74F651A–654A series.
Figure 5 shows the pinouts of the 74F827/828 buffers and This series allows you to store or real-time transfer data in either
74F861–864 Transceivers. There currently are no 9-bit buffer direction through the transceiver function. Data at the AN port can be
offerings in this series. stored in either the AN port register or the BN register and, then, can

June 1988 7
Philips Semiconductors Application note

74F extended octal-plus family applications AN214

be transferred either from the AN port register to the BN port outputs Parity Bus Series Advantages
or from the BN port register to the AN port outputs. The increased functional density of the Parity Bus Series produces a
The same capabilities are available to data presented to the B–port. 2:1 package reduction (plus 1 AND gate) and, therefore, 38:24 pin
When a port’s output buffers are enabled (OE = LOW and reduction. Power dissipation savings of 82.5mW for the
DIR = LOW for AN outputs enabled or HIGH for BN outputs 74F455/456/655A/656A Drivers and 137.5mW for the 74F657 are
enabled), the SXX select inputs (SAB and SBA) control the two also achieved through shared internal logic. Table 2 shows the
EX-OR gates allowing the output port data to come either directly package/pin advantage as well as the worst case propagation
from the other port (real-time transfer) or from the other port’s input delays and ICC of the Family versus their competition.
storage register. Figure 9 is a summary of the pin configurations of the entire Parity
The CPABN and CPBA inputs are the LOW-to-HIGH edge-triggered Bus Drivers and Transceiver Series.
clock inputs for the AN port register and BN port register. Data The 74F455/456/655A/656A Octal Parity Bus Drivers and the
presented to either port’s inputs can be clocked into its input register 74F657 Octal Parity Bus Transceiver Series combines the popular
on a LOW-to-HIGH CPXX input regardless of the logic levels on any Philips Semiconductors 74F24X buffer/transceiver functions with the
of the other mode control inputs. 74F280B 9-bit Parity Generator/Checker, “Broadside” input/output
The 74F651A–654A’s OEAB and OEBA output enable inputs may pin configurations, “Light-Load” inputs and an increased guaranteed
be tied together to enable the B outputs when HIGH or AN outputs sink/source capabilities of –15mA/64mA for low impedance bus
when held LOW or can be used separately to independently control environments. The 74F445/446 Drivers with their multiple
the two output ports. Tying the 74F651A–654A’s OEAB and OEBA center-package ground supply pins are logically identical to the
together is logically equivalent to the DIR input of the 74F655A/656A Drivers, except for the latter’s single corner-package
74F646A–649A. supply pins and an additional Output Enable input. The 74F657
Parity Bus Transceiver allows the parity to be generated and
checked in both directions in a single package replacing one 74F245
Transceiver, 20-pin DIP and two 74F280, 16-pin DIPs plus a couple
of gates.

F657 F655/6A F455/6 F455/6 F655/6A F657

Xcvr Buffer Buffer Buffer Buffer Xcvr
T/R OE1 OE1 1 24 ΣO VCC OE

A0 OE3 OE2 2 23 ΣE OE2 B0

A1 PI PI 3 22 Y0/Y0 ΣO B1

A2 I0 I0 4 21 Y1/Y1 ΣE B2
SEE BLOCK DIAGRAM

A3 I1 I1 5 20 Y2/Y2 Y0/Y0 B3

A4 I2 I2 6 19 GND Y1/Y1 GND

VCC I3 VCC 7 18 GND Y2/Y2 GND

A5 I4 I3 8 17 Y3/Y3 Y3/Y3 B4

A6 I5 I4 9 16 Y4/Y4 Y4/Y4 B5

A7 I6 I5 10 15 Y5/Y5 Y5/Y5 B6

O/E I7 I6 11 14 Y6/Y6 Y6/Y6 B7

ERROR GND I7 12 13 Y7/Y7 Y7/Y7 PARITY

SF01336

Figure 9. 74F Octal Parity Drivers/Transceiver Pin Configurations

June 1988 8
Philips Semiconductors Application note

74F extended octal-plus family applications AN214

74F657 Operation EO
The 74F657 Parity Bus Transceiver, as shown in its simplified logic
T/R
diagram, Figure 10, is a combination of a 74F245 Octal Transceiver
and a 74F280B 9-bit Parity Generator/Checker plus one AND gate.
Figure 11 expands the logic block diagram of the Family’s Parity
Tree Logic (inside the dashed line of Figure 10).
AN 8X BN
During TRANSMIT mode (AN = Hi-Z), the PARITY and ERROR A0–A7) 8L 8L (B0–B7)
outputs are generated from the AN input/output port. In the 8L
RECEIVE mode, the BN port is the input from the system or mother
board bus (B-port outputs = Hi-Z).
For best speed performance, PARITY should always be generated ⊕
from the AN port for the BN port (TRANSMIT mode), and parity
ERROR should always be checked for data coming in on the B-port
(RECEIVE mode). EVEN or ODD parity generation and checking is
determined by the EVEN/ODD input (EVEN = HIGH, and RE ⊕
TE
ODD = LOW).
ERROR PARITY
In the TRANSMIT mode (T/R = HIGH), transmitted data travels from
the A-port to the B-port in less than 8.0ns generating a PARITY bit
SF01337
output in less than 16.0ns. Whereas, in the RECEIVE mode
(T/R = LOW), received data traverses from the B-port to the A-port Figure 10. 74F657 Simplified Block Diagram
path in, again, less than 8.0ns, but then the ERROR checking
output, being generated from the output data presented to the A-port
and the PARITY input, takes an additional 16.5ns or less to stabilize. The 74F588 IEEE-488 Octal Transceiver
Therefore, the total RECEIVEd-data-to-ERROR checking output The 74F588 is a non-inverting IEEE-488 standard transceiver
propagation time is the sum of the BN-to-AN delay (8ns) and the contains eight bidirectional 3-State buffers. The BN port outputs can
AN/PARITY-to-ERROR output delay (16.5ns) or 22.5ns. source/sink –15mA/64mA (guaranteed) and have series termination
However, in many cases, the propagation delay that has to be taken resistors as specified in the IEEE-488 specification. The AN port,
into consideration does not have to include parity calculation time which interfaces to the PC board or system logic bus, is guaranteed
and could be equal to that of just the transceiver part (8ns). This is to source/sink –3mA/24mA. The 74F588 pinout is identical to that of
due to the fact that it may not be too late to interrupt whatever needs the 74F545 Octal Transceiver with the IEEE-488 termination
to be interrupted in case of a parity error after the data has already resistors in series with the BN port.
gone by (i.e., via late bus error).

Parity Tree Analysis

The basic 3-input Comparator Cell, inside the dashed line in
Figure 11, is used throughout the Parity Bus Series. If there are an
even number of HIGH inputs (0 or 2) the output of the 3-Input
Comparator Cell will be HIGH, while an odd number (1 or 3) will
produce an output LOW. The 74F657’s Parity Tree Logic, combines
four of the 3-Input Comparators with a 2-input comparator, a 2-input
AND gate and output buffers for PARITY and ERROR to produce
the complete parity generator/checker logic.

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A0

A1

A2

A3

A4

A5

TE
A6
PARITY

A7 RE

RE

O/E

ERROR
SF01338

Figure 11. 74F657 Parity Tree Logic Diagram

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Metastability in Latches and Registers metastable state can easily last more than 50ns with today’s high
Interfacing a basically asynchronous real-world with synchronous performance logic families and WILL cause systems to “crash” if
logic systems can and does cause many circuit designer great care is not taken with asynchronous, real-world interfacing.
headaches. The problem: latches and registers which are normally The D-type latch shown in Figure 12 has DATA applied to NAND
considered to have only two stable states (High and Low) actually gate 1 and DATA applied to NAND gate 2. When the LE (Latch
have a third—The METASTABLE State. This third operating point Enable) input is LOW, gates 1 and 2 outputs are HIGH and the G3/4
occurs when the corss-coupled latch is exactly balanced. This state R-S latch is latched and stable. When LE is HIGH, the latch appears
is only stable when there is no noise on the chip which would tend to to be transparent to the DATA input—Q equals DATA. On the
destabilize the perfect energy balance between the bi-stable states HIGH-to-LOW transition of LE, the DATA logic level that meets the
of the latch. Refer to Figure 12. latch’s setup and hold time is stored in the latch.
Metastability can occur when input data violate the setup time or If DATA changes during the setup time to hold time period, it is
hold time specifications at the clocking or strobing edge of the possible for both outputs of gates 1 and 2 to be in the input
synchronizing clock input. With no system noise, the latch cannot thresholds region of gates 3 and 4, respectively. Under these
decide “yes or no”, so it is possible for the latch to “go metastable” conditions, the latch (gates 3 and 4) could be perfectly balanced in
or “maybe”. With noise on the chip, random energy will “nudge” the the METASTABLE state. Eventually, chip and system noise will
latch toward one of its “bi-stable” states—HIGH or LOW. This cause the latch to be forced into a HIGH/LOW stable state.
metastable state time can range from nanoseconds to milliseconds.
With today’s very high performance logic families, the metastable The Extended Octal-Puls Family, while not entirely immune, has
condition can last for, perhaps, 1000 times the latch’s normal been made metastable resistant by using design techniques which
propagation delay time. A metastable latch has an unpredictable force the latch toward a stable state much more quickly than older
delay time during which the output is between logic levels. This bus interface families.

DATA
G1
G3 Q
5.0

4.0
G4 Q
G2
LE

3.0

METASTABLE POINT VOUT — OUTPUT VOLTAGE

2.0
VOG3 = VIG4 VOG3 = VIG4
↓ ↓
VTH = 1.35V VTH = 1.35V
1.0
↑ ↑
ENERGY ENERGY

0
0 0.5 1.0 1.5 2.0 2.5
LOW HIGH VIN — INPUT VOLTAGE

SF01339

Figure 12. Metastability in Latches and Registers

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Dual-Registered Transceiver Applications Parity Bus Transceiver Applications

Figure 13 illustrates how the 74F646A-649A and 74F651A-654A can Figure 14 illustrates the functional density advantages of the Parity
be used to either synchronize data transfer between two systems, or Bus Series using the 74F657 in a typical microprocessor/data bus
pipeline data. Data is stored in a register, then, while retrieving more transceiver application. Note the 74F245 + 74F280B version would
data, the first data is read. When the second is available, it can still require a 2-input AND gate and 3-State buffers for the PARITY
either be stored or read directly. Two slower systems can be and ERROR outputs. And, of course, it would require an order of
multiplexed into a high speed system in the same way. magnitude higher input current than a single 74F657 would, and
would also introduce much higher capacitive loading (for both the
bus and the microcontroller).

1 24

74F652A/654A DUAL-REGISTER XCVR

2 23

3 22

4 21

CPAB

SYSTEM 3
5 20
1 24 VCC
6 19
SAB
2 23
CPBA 8L 8L
74F652A/654A DUAL-REGISTER XCVR

7 18

OEAB SBA 1 24 8 17
3 22

74F652A/654A DUAL-REGISTER XCVR

2 23 9 16
A0 OEBA
4 21 3 22 10 15

A1 B0 4 21 11 14
5 20
SYSTEM 1
SYSTEM 1

SYSTEM 2

5 20 12 13
A2 B1
6 19 6 19
8L 8L
A3 B2 7 18
7 18
8 17 1 24
A4 B3

74F652A/654A DUAL-REGISTER XCVR

8 17 9 16 2 23

A5 B4 10 15 3 22
9 16
11 14 4 21
A6 B5
10 15

SYSTEM 2
12 13 5 20

A7 B6 6 19
11 14 8L 8L
7 18
B7
GND 12 13 8 17

9 16

10 15

11 14

12 13

SF01340

Figure 13. 74F Extended Octal-Plus Dual-Registered Transceiver Applications

T/R T/R
74F657 PARITY BUS TRANSCEIVER
MOS MICROPROCESSOR/CONTROLLER

MOS MICROPROCESSOR/CONTROLLER
74F245 OCTAL TRANSCEIVER

B0 B0

B1 B1

B2 B2

B3 B3

B4
OR B4

B5 B5

B6 B6

B7 B7
ERROR
74F280B 9-BIT COMPARATOR PARITY PARITY
OR
ERROR
ODD/EVEN
ODD/EVEN
SF01341

Figure 14. 74F657 Parity Bus Transceiver Applications

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Table 3. The Extended Octal-Plus Family Capabilities Summary

Part # Broad- IOH/IOL
Polarity Output Storage Speed Parity Comments
Number Bits side MIN
“Light-Load” buffer and Line Driver Functions
74F455/456 8-bit INV/NINV 3-St Yes –15/64mA None 7.5ns Yes Multiple/Ctr Pkg. GND Pins, ΣE, ΣO = –15/64mA
74F540/541 8-bit INV/NINV 3-St Yes –15/64mA None 7.5ns No Broadside pinout of 74F240
74F655A/656A 8-bit INV/NINV 3-St Yes –15/64mA None 7.5ns Yes ΣE, ΣO = –15/64mA
74F827/828 10-bit NINV/INV 3-St Yes –15/64mA None 9.0ns No

“Light-Load” Register and Latch Functions

74F821/822 10-bit NINV/INV 3-St Yes –15/64mA Reg 100MHz No Data, MR, OE, & Clock EN Inputs
74F823/824 9-bit NINV/INV 3-St Yes –15/64mA Reg 100MHz No Data, MR, OE, & Clock EN Inputs
74F825/826 8-bit NINV/INV 3-St Yes –15/64mA Reg 100MHz No Data, MR, OE, & Clock EN Inputs
74F841/842 10-bit NINV/INV 3-St Yes –15/48mA Latch 100MHz No Data, MR, OE, & LE Enable Inputs
74F843/844 9-bit NINV/INV 3-St Yes –15/48mA Latch 100MHz No Data, MR, OE, & LE Enable Inputs
74F845/846 8-bit NINV/INV 3-St Yes –15/48mA Latch 100MHz No Data, MR, OE, & LE Enable Inputs

“Light-Load” Transceiver Functions

74F545 8-bit NINV AN 3-St Yes –3/24mA None 7.0ns No
BN 3-St Yes –15/64mA None 7.0ns No
74F550/551 8-bit NINV/INV BN 3-St Yes –15/64mA BN-Reg 10.5ns No AN → BN, ERROR, status registers, 50MHz
AN 3-St Yes –3/24mA AN-Reg 10.5ns No BN → AN, Multiple/Center Pkg. GND pins **
74F552 8-bit NINV BN 3-St Yes –15/64mA BN-Reg 10.5ns Yes AN → BN, PARITY, ERROR, status registers
AN 3-St Yes –3/24mA AN-Reg 10.5ns Yes BN → AN, Multiple/Center Pkg. GND pins **
74F588 8-bit NINV AN = 3-St Yes –3/24mA None 7.5ns No
BN 3-St Yes –15/64mA None 7.5ns No IEEE-488/GPIB w/line term. resistors
74F620/623 8-bit INV/NINV BN 3-St Yes –15/64mA None 7.5ns No AN → BN
AN 3-St Yes –3/24mA None 7.5ns No BN → AN
74F621/622 8-bit NINV/INV BN OC Yes OC/64mA None 13.0ns No AN → BN
AN OC Yes OC/24mA None 12.5ns No BN → AN
74F640 8-bit INV A/B 3-St Yes –15/64mA None 7.5ns No AN ↔ BN
74F641/642 8-bit NINV/INV BN OC Yes OC/64mA None 13.0ns No AN → BN
AN OC Yes OC/20mA None 12.0ns No BN → AN
74F646A/648A 8-bit NINV/INV A/B 3-St Yes –15/48mA 2 Reg 11.0ns No AN ↔ BN, registers for AN & BN ports, 80MHz (min.)
74F647/649 8-bit NINV/INV AB OC Yes OC/64mA 2 Reg 19.5ns No AN ↔ BN, registers for AN & BN ports, 40MHz (min.)
74F651A/652A 8-bit INV/NINV A/B 3-St Yes –15/48mA 2 Reg 11.5ns No AN ↔ BN, registers for AN & BN ports, 80MHz (min.)
74F653/654 8-bit NINV/INV BN 3-St Yes –15/64mA BN-Reg 11.0ns No AN → BN, BN port = 85MHz (min.)
AN OC Yes OC/64mA AN-Reg 20.0ns No BN → AN, AN port = 45MHz (min.)
74F657 8-bit NINV BN 3-St Yes –15/64mA None 8.0ns Yes AN → BN, PARITY, ERROR = –15/64mA
AN 3-St Yes –3/24mA None 8.0ns No BN → AN, Multiple/Center Pkg. GND pins
74F861/862 10-bit NINV/INV A/B 3-St Yes –15/64mA None 10.0ns No AN ↔ BN
74F863/864 9-bit NINV/INV A/B 3-St Yes –15/64mA None 10.0ns No AN ↔ BN
74F1245 8-bit NINV BN 3-St Yes –15/64mA None 8.0ns No AN → BN, “Light-Load” pin-for-pin ’F245 replacement
AN 3-St Yes –3/24mA None 8.0ns No BN → AN
74F2951/2952 8-bit INV/NINV A/B 3-St Yes –15/64mA 2 Reg 12.5ns No AN ↔ BN, registers for AN & BN ports, 80MHz (min.) **
NOTES:
All parameters are worst-case, unless otherwise specified.
3-St = 3-State
OC = Open Collector
Reg = LOW-to-HIGH edge clocked D-type register
Latch = HIGH logic level on the Latch Enable logic, data passes directly through D-type latch,
HIGH-to-LOW logic level transition of the Latch Enable, data is stored in the D-type latch.
** = These devices utilize standard FAST input structures producing input currents of +20µA and –0.6mA.
MR = Master Reset
OE = Output Enable

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Data sheet status

Data sheet Product Definition [1]
status status

Objective Development This data sheet contains the design target or goal specifications for product development.
specification Specification may change in any manner without notice.

Preliminary Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date.
specification Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
Product Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make
specification changes at any time without notice in order to improve design and supply the best possible product.

[1] Please consult the most recently issued datasheet before initiating or completing a design.

Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.

Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.

Philips Semiconductors  Copyright Philips Electronics North America Corporation 1998

811 East Arques Avenue All rights reserved. Printed in U.S.A.
P.O. Box 3409
Sunnyvale, California 94088–3409 Date of release: 03-98
Telephone 800-234-7381
Document order number: 9397 750 03682


 
 
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