BACH KHOA UNIVERSITY OF TECHNOLOGY 

FACULTY OF ELECTRICAL & ELECTRONICS ENGINEERING

DIGITAL SYSTEMS LABORATORY 

PRELAB 4 FINITE STATE MACHINE
Group: TT06

Full Name Stu. ID

Tạ Minh Anh 2051085

EXERCISE 1:
Objective: Create state diagram and build the circuit for a finite state machine.
Requirement: Consider following state diagram and one-hot state assignment

Figure 1: A state diagram for the FSM Table 1: One-hot codes for the FSM
Instruction: 
1. Write VHDL assignment statements for all flip-flops of the FSM
2. Based on above statements, implement the circuit using flip-flops and logic gates.
Check: Your report has to show two results:
 Nine assignment statements for 9 flip-flops.
 The circuit diagram. 

EXERCISE 2:
Objective: Describe FSM using VHDL behavioral expressions.
Requirement: The state table of a FSM is also described by using a VHDL CASE statement in a
PROCESS block and use another PROCESS block to instantiate the state flip-flops. The
output z can be specified by using a third PROCESS block or simple assignment statements.
Instruction: 
Below is a suggested skeleton of the VHDL code. Write VHDL code which describe the FSM in
exercise 1, which has state code shown in table 2.
 Table 2: Binary codes for the FSM

LIBRARY ieee; 
USE ieee.std_logic_1164.all; 
ENTITY part2 IS PORT ( . . . define input and output ports 
. . .); 
END part2; 
ARCHITECTURE Behavior OF part2 IS 
. . . declare signals 
TYPE State_type IS (A, B, C, D, E, F, G, H, I); 
– Attribute to declare a specific encoding for the states 
attribute syn_encoding : string; 
attribute syn_encoding of State_type : type is "0000 0001 0010 0011 0100 0101 0110 0111 1000"; 

SIGNAL y_Q, Y_D : State_type; - - y_Q is present state, y_D is next state 
BEGIN 
. . . 
PROCESS (w, y_Q) - - state table 
BEGIN 
case y_Q IS 
WHEN A IF (w = ’0’) THEN Y_D <= B; 
ELSE Y_D <= F; 
END IF;
. . . other states 
END CASE; 
END PROCESS; - - state table 

PROCESS (Clock) - - state flip-flops 

BEGIN 
. . . 
END PROCESS; 
. . . assignments for output z and the LEDs END Behavior;
END Behavior;
Check: Your report has to show VHDL description for the FSM.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY prelab42 IS PORT (w, clock, reset: in std_logic; output: out std_logic );
END prelab42;
ARCHITECTURE Behavior OF prelab42 IS
TYPE State_type IS (A, B, C, D, E, F, G, H, I);
attribute syn_encoding : string;
attribute syn_encoding of State_type : type is "0000 0001 0010 0011 0100 0101 0110
0111 1000";

SIGNAL y_Q, Y_D : State_type;

BEGIN
PROCESS (w, y_Q)
BEGIN
case y_Q IS
WHEN A => IF w = '0' THEN Y_D <= B;
ELSE Y_D <= F;
END IF;

when B => if (w='0') then y_d <= c;

else y_d <= f;
end if;

when c => if (w = '0') then y_d <= d;

else y_d <= f;
end if;

when d => if ( w='0') then y_d <= e;

else y_d <= f;
end if;

when e => if (w ='1') then y_d <= f;

else y_d <= e;
 end if;

when g => if w='1' then y_d <= h;

else y_d <= b;
end if;

when i => if w='1' then y_d <= i;

else y_d <= b;
end if;

when f => if w='1' then y_d <= g;

else y_d <= b;
end if;

when h => if w='1' then y_d <= i;

else y_d <= b;
end if;

END CASE;
END PROCESS;

PROCESS(clock, reset)
BEGIN
IF reset = '1' THEN y_q <= a;
ELSIF (clock = '1' and clock'event) THEN
y_q <= y_d;
END IF;
END PROCESS;

PROCESS (w, y_Q)

BEGIN
case y_Q IS
 WHEN D => if w='0' then output <= '1';
else output <= '0';
end if;
when H => if w= '1' then output <= '1';
else output <= '0';
end if;
when E => if w='0' then output <= '1';
else output <='0';
end if;
when I => if w='1' then output <= '1';
else output <= '0';
end if;
when others => output <= '0';
end case;
end process;

END Behavior;

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_signed.all;

entity Dff1 is
port (inD, clkD , rstD , prtD: in std_logic ; outD : out std_logic);
end Dff1;

architecture behave of Dff1 is

begin

process (clkD,inD,rstD,prtD)
begin
if rstD ='0' then
outD <= '0';
else
if clkD'event and clkD ='1' then
outD <= inD;
else null;
end if;
end if;
end process;
end behave;

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_signed.all;

entity prelab43 is
port (input, clk, button: in std_logic ; output : out std_logic);
end prelab43;

architecture struct of prelab43 is

signal in1, in2, in3, out4: std_logic ;

component dff1
port (inD, clkD , rstD , prtD: in std_logic ; outD : out std_logic);
end component;

begin
Q0: dff1 port map (input, clk, button, '0', in1);

Q1: dff1 port map (in1, clk, button, '0', in2);

Q2: dff1 port map (in2, clk, button, '0', in3);

Q3: dff1 port map (in3, clk, button, '0', out4);
output <= in1;
end struct;

EXERCISE 3
Objective: Implement a shift register.
Requirement: Write a VHDL program which describes following shift register:

Figure 3: Shift register.

The output L L L L equals “0000” when Reset = 0. Otherwise, input value will be shifted from
4 3 2 1

L1 to L4.
Instruction:
1. Create a new Quartus project for your circuit.
2. Write a VHDL file that instantiates the four flip-flops in the circuit.
3. Compile the code. Use the Quartus RTL Viewer tool to examine the gate-level circuit
produced from the code.
4. Simulate the behavior of your VHDL code by using the simulation feature provided in
the Quartus software. Test the functionality of your design by inputting various data
values and observing the generated outputs.
Check: Your report has to show two results:
 The waveform to prove the circuit works correctly.
  The result of RTL viewer.

EXERCISE 4
Objective: Implement a periodic signal.
Requirement: Write a VHDL program which create an enable signal that is asserted once every
second.
Instruction:
1. Create a new Quartus project for your circuit.
2. Write a VHDL file that create an enable signal that is asserted once every 0.5 of a second.
3. Compile and simulate the behavior of your VHDL code by using the simulation feature
provided in the Quartus software. Test the functionality of your design.
Check: Your report has to show two results:
 The waveform to prove the circuit works correctly.

EXERCISE 4
Objective: Know how to implement a digital circuit using an FSM.
Requirement: The Morse code uses patterns of short and long pulses to represent a message.
Each letter is represented as a sequence of dots (a short pulse), and dashes (a long pulse). For
example, the first eight letters of the alphabet have the following representation: 
A•—
B—•••
C—•—•
D—••
E•
F••—•
G——•
H••••
Design and implement a Morse-code encoder circuit using an FSM.
Instruction:
1. Assign dot as ‘0’ and dash as ‘1’, we have:
Letter SW 2-0 Morse Morse Length
code
A 000 0010 010
B 001 0001 100
C 010 0101 100
D 011 0001 011
E 100 0000 001
F 101 0100 100
G 110 0011 011
H 111 0000 100

1. In order to construct the FSM, follow these notes:

- When KEY1 is pressed, the system begins to store the Morse code to be sent in a shift register
(data = Morse_code), and its length in a counter (size = Morse_length). Otherwise, the system is
idle. (notes: Morse_code and Morse_length depend on SW value.)
2-0

- After loading data and size, the system starts to send LSB bit of data:
 If data(0) = 0, a LEDR will be on for 1 second. After a second, the data is right shifted and
its size decreased by one.
If data(0) = 1, a LEDG will be on for 1 second. After a second, the data is right shifted and
its size decreased by one.
- The process continues to display data on LED using new data and size value until data size
equal 1.
Check: Your report has to show the FSM diagram.