The Printed Circuit Designer’s Guide to...

™
High Performance Materials
Michael J. Gay

Isola

© 2022 BR Publishing, Inc.

All rights reserved.

BR Publishing, Inc.
dba: I-Connect007
942 Windermere Dr. NW
Salem, OR 97304
U.S.A.

ISBN: 978-1-7370232-9-6
Visit I-007eBooks.com for more books in this series.

I-Connect007.com
 PEER REVIEWER

This book has been reviewed for technical accuracy by the following expert.

Mark Thompson
Engineering Manager
Out of the Box

Mark has been in the electronics

industry for over 39 years. He began
his career as a PCB fabrication engi-
neer in California, then moved to
Redmond, Washington, to begin
working for Prototron Circuits, where
he spent the next 25 years. Most
recently, Mark was a board designer/fab expert for Monsoon Solutions
in Bellevue. Currently, he is an Engineering Manager at Out of the Box, an
assembly company located in Renton, Washington.

Mark is the author of a popular column published at PCB007 called “The

Bare Board Truth.” He is also author of the I-007eBook, The Printed Circuit
Designer’s Guide to... Producing the Perfect Data Package, downloaded by
nearly 2,000 readers, as well as co-author of a book for EMA called The
Hitchhiker’s Guide to PCB Design.

Mark has also been a guest editor for I-Connect007’s Real Time with… video
program series, interviewing key electronics industry leaders including
material manufacturers, component manufacturers, and PCB equipment
manufacturers.

With a passion for aerobatics and jazz, Mark is also a licensed pilot, artist,
historian and musician.
 MEET THE AUTHOR

Michael J. Gay
Director
Isola

Michael J. Gay currently holds the posi-

tion of Director, High Performance
Products, with Isola. He has been with
Isola for 20 years and has 25 years of
experience in the laminate and PCB
manufacturing industries. Michael
has held various positions at Isola,
including Technical Sales Manager and
Director of Emerging Products–Asia Pacific region, where his responsibili-
ties ranged from new product introduction, PCB process development,
technical support, and troubleshooting for Isola customers.

Since returning to the U.S. from his role in Asia, Michael has worked closely
with major industry OEMs to develop and qualify Isola materials for the
next generation of technology. In his current position, he provides product
application training, collaborative design support, and design reviews for
selecting the right material across a wide range of applications, including
high-speed digital, high energy/voltage, CAF resistance, and RF/microwave.

Michael is active in various PCB industry organizations where he currently

provides technical expertise to industry-critical committees and projects.
He received his bachelor’s degree in mechanical engineering and master’s
degree in business administration from Portland State University.
Contents
1 Introduction

5 Chapter 1: The Resin System

11 Chapter 2: Glass Fabric

21 Chapter 3: All About Construction Tables

31 Chapter 4: Copper Foil

43 Chapter 5: Control of Electrical Performance

47 Chapter 6: Automotive Electrification

52 Conclusion

54 References & Acknowledgments

55 Glossary of Acronyms

57 About Isola
 Introduction
Choosing the right material for your application can be a major challenge.
There are “cost to performance” decisions that need to be made in order to
select material that will meet the expected performance requirements and
the desired cost targets. Selecting a material that meets cost targets, but fails
to perform in prototype development testing, results in costly revision spins,
increases cost, and results in delays to market.

From the resin type, the styles and types of glass fabrics, and various types
of copper foils, the reader can have a clearer picture of what to know when
selecting which material is most desirable for their upcoming products. This
book does not provide answers to all things laminate, but the hope is to
provide a solid base for making material selection decisions and, along the
way, answer some key questions like these:

• Why is PPO resin better than epoxy resin for electrical

performance?

• Why could flat glass fabrics reduce the skew and ease for
laser drilling?

• Why is very low-profile copper foil preferred for high-speed

applications?

• What is the impact of raw material on data rate or on signal

integrity testing?

When designs require high voltage CAF performance, thermal robustness,

or high-speed massive data transmission rates, laminate materials must be
selected to suit your requirements for printed circuit boards. The components
used to make the laminates must be studied to know the influence on these
kinds of applications.

1
This book was generated by key technical resources at Isola Group. Each of
the contributing technical experts have 25–35 years of industry experience in
laminate raw materials, laminate and prepreg manufacturing, laminate mate-
rial development, new product introduction, PCB fabrication, and OEM appli-
cations. These individuals have contributed many years of tacit knowledge and
experience, which are the basis for this book. We hope that this fundamental
knowledge can help design engineers to narrow down the selection range for
their design project.

Let’s Get Started

We will start by taking a look at the evolution of rigid copper-clad laminate
materials and what a designer will need to know about new materials in order
to make informed decisions that can shorten the design cycle. We will cover
many of the commonly asked questions and explain why data beyond the
product data sheet is needed to create advanced designs.

Enabling the next generation of electronic products is the main goal for an
electronics supplier. To accomplish this goal, products must be novel develop-
ments or incremental improvements on existing products in order to provide
the necessary performance needed for the next generation of systems. Collab-
oration through the supply chain provides the necessary feedback of target
performance characteristics which are then passed on to R&D, and the work
begins. In reality, this work is integrated into the ongoing and never-ending
search for ways to meet or exceed those targets and improve the products.

For a manufacturer of copper-clad laminate, the targets have been focused on

the next generation of materials. These are materials that can be applied to
wired and wireless systems such as 5G, high-energy and high-voltage systems
for automotive electrification, high-end computing systems for AI, autono-
mous driving systems, data management, analysis, and much more. Copper-
clad laminate material is the foundation for today’s electronics and the chal-
lenge of meeting new performance targets is an ongoing effort where millions
of dollars of R&D investment is made.

The Basics
Copper-clad laminate and prepreg materials have not changed much over the
years. Some form of resin system, glass fabric, and copper foil are still the

2
main components of a good rigid laminate system. Looking at the material
from a purely physical appearance, it would seem that not much has changed
in the last 50 or so years. The glass fabric is still impregnated in large scale,
using high-volume treater systems to make B-stage or prepreg. The B-stage is
mated with copper foil and pressed in large batch lamination presses to make
the laminate material.

There has been a significant number of developments in how the raw mate-
rials are designed, developed, manufactured, and then integrated into lami-
nate products to provide the PCB and system designers subtle, incremental
improvements in functional performance. These improvements allow us to
push rigid PCB materials beyond what we knew only a few years ago. Under-
standing the subtle changes and how they enable improved performance
makes choosing the right material for an application more critical. More than
ever, PCB and system designers need to understand how these materials
interact to create a functional system so they can achieve specific design goals
without over-specifying the material.

A technical data sheet can provide basic information about the materials to
choose from. A designer can make basic comparisons of properties and deter-
mine a class of material in the spectrum of available products that will meet
the general performance requirements.

In addition to selecting a material for an application based on the material

properties, there are other PCB-related properties that need to be considered
as well. Ease of processing, large format HDI capability, CAF resistance, signal
integrity performance, thermal cycling performance, and high-temperature
and high-voltage capability are some of the most important attributes. Navi-
gating material choices requires collaboration with knowledgeable technical
experts to enable an in-depth understanding of the laminate material options
and capabilities to reduce time to market.

Before we start digging into selection of material, let’s look at the main compo-
nents and how they have evolved to enable new technology and enhance our
lives.

3
 Chapter 1

The Resin System

Evolution of the Resin System

Most basic resin systems have been around for a long time. Here is a little
timeline of developments through more recent introductions.

• In 1907, the first laminate was made with pure phenolic resin
by Westinghouse in Pittsburgh, Pennsylvania. Formica became
the first true sheet laminate.1

• The first application—a radio by Paul Eisler in 1936—led to

practical manufacturing for military radios in the U.S., and use
of single-sided copper-clad phenolic laminate started in about
1943 using paper and cotton as the structural component.
Epoxy resin was introduced shortly after in 1947.2

• Still reigning as the lowest loss resin system, a PTFE, RT/

Duroid® was introduced in 1949.3

• The first polyimide was discovered in 1908 by Bogart and

Renshaw. However, the high heat-resistant polyimide lami-
nate material was brought to the market in 1951.4

• Isola began production of copper-clad laminate in 1956.

• Epoxy-based laminate systems followed around 1960 and

used woven E-glass fabric.5

• Shortly after, G-10 epoxy laminate (non-flame retardant epoxy

resin plus E-glass) and a flame-retardant epoxy version called
FR-4 (flame-retardant epoxy resin plus E-glass) were intro-
duced in 1968.

5
From that time forward, there have been various blends, such as PPO (poly-
phenylene oxide)/epoxy, CE (cyanate ester)/epoxy, and polyimide/epoxy,
that were created to balance properties of pure resin systems to achieve
specific enhanced properties. Each new resin system was built on learning
from previous products. Resin system developments for high heat applica-
tions such as LED lighting, ultra-thin non-reinforced films for capacitance and
halogen-free systems to meet RoHS and REACH environmental requirements,
continue to be developed to address the
performance and reliability needs. With
The process of each new need, laminate material manu-
facturers go into the lab and see what new
developing a new raw material can be used to improve resin
resin system system performance.

requires deep The process of developing a new resin

knowledge of system requires deep knowledge of how the

PCB will be manufactured. PCB designers
how the PCB will are most concerned with assembly process
be manufactured. capability, long term reliability, thermal
cycling performance, CAF resistance, and
electrical performance, therefore, all these
attributes must be balanced within the design of a resin system. The market
requirements mean that laminate manufacturers must continue to research
available options that will provide incremental improvements to the resin
system performance.

For example, 15 years ago in 2005, RoHS was implemented. The available high
Tg, Dicy-cured epoxy laminates were not adequate for the higher tempera-
ture, lead-free assembly processes the board would see. The introduction of
new, higher-temperature soldering processes necessitated the need for an
improved FR-4 resin system to address thermal performance deficiencies.
Phenolic-cured epoxies and fillers became commonplace in the new materials.

Resin systems continue to evolve and performance capabilities continue to

improve. Table 1.1 shows a general overview of the types of resin systems
for copper-clad rigid laminates that are currently offered. Rigid laminate
systems are composites, so before we can cover selection, we need to review
the components that make up the composite. We are now seeing that resin

6
systems are commonly blends or plastic alloys that combine resin technology,
filler technology, and bonding technology to assure the components are prop-
erly bonded for thermal and mechanical reliability.

Choosing a resin system for a high-speed digital application is becoming less

difficult from a thermal and mechanical perspective since new materials have
been developed and tested to meet current functional requirements. This
allows the designer to look at the general electrical properties to choose a
class of material that meets the need of the specific design. Not every design
requires the lowest loss resin system and choices with lower cost can be
considered. More information is still needed to make a good decision.

Evolution of Resin Fillers

Fillers have been used for many years with the primary purpose being to take
up space in the resin system. The cost of a high-performance resin system like
PTFE is higher than the cost of the filler, therefore it reduces the processing
cost of the resin system. In recent years, more attention has been paid to the
functional impact of various fillers.

There are numerous options available to use and each option has pluses and
minuses. For example, ceramic fillers will provide excellent thermal perfor-

7
mance improvement, but will introduce drill wear issues. Talc provides excel-
lent thermal performance improvement and is soft for excellent drill wear,
but electrical performance is compromised. The following list is by no means
all inclusive, but it demonstrates the potential options available for laminate
manufacturers to use.
• Silica powder

• Aluminum hydroxide

• Spherical alumina

• Titanium white powder

• Aluminum nitride

• Hexagonal boron nitride (H-BN)

• Silicon carbide

• Glass microspheres

There have also been many recent improvements to the fillers themselves:

• Adhesion coatings for improved bonding to the resin system,

to improve thermal performance

• Improved filler milling processes to improve filler shape for

better dispersion, to reduce agglomerations and improve
homogeneity of the dielectric composite

• Size reduction to improve signal integrity

• Use of non-reacted flame retardants which can enhance mate-

rial performance properties over reacted flame retardants

Laminate manufacturers have learned how these fillers can be used to manip-
ulate material properties and how to balance the resin system to maximize the
benefit. For example, fillers are used to manipulate properties like permittivity,
dissipation factor, heat dissipation, and PCB processing performance. There
are limits to how much filler one can use in a resin system before negative
performance attributes emerge. As a designer you may want a resin system
that has a very low CTE. For the laminator to achieve a low CTE, the resin system
needs a low CTE, ceramic-type filler with loading near the maximum amount
that will allow adequate resin bonding between filler, glass and copper.

8
The problem with maximum filler loading is that a heavily loaded resin system
does not easily fill and flow into copper features and requires high lamination
pressure to mold the material. There are always tradeoffs; too much filler may
result in weak bonding and reduce thermal reliability due to inadequate resin
flow. Just the right amount of filler can reduce loss, cost, the propensity for CAF
formation, and improve thermal reliability.

As a user of the material, it is not likely you will know what the fillers are in
a particular resin system. But you can gain insight by looking at the general
properties of the material. If the Z-Axis CTE is in the low 2% range, it is likely
highly loaded. Does the material have a very low drill hit count? It likely has a
hard ceramic-type filler.

9
10
 Chapter 2

Glass Fabric

Evolution of Glass Fabric

Materials such as cotton, paper and glass mat were used before woven
glass fiber started mass production and became the dominant fabric used
for PCB composites. Early PCBs were low layer count and used a heavy
glass weave, such as 7628 or 7629, as the primary component. Since the
mid ‘70s, glass manufacturers have introduced new and thinner glass
weaves to enable ultra-thin laminate and substrate materials.

Woven glass fabric is impregnated with resin and when fully cured or
dried, provides the mechanical, chemical and electrical properties for rigid
printed circuit applications. The characteristics and properties of glass
fiber and fabrics are defined by IPC-4412 “Specification for Finished Fabric
Woven from E-Glass for Printed Boards.” There are compositions of glass
fibers that will also be discussed including the next generation of lower-Dk
glass fabrics now in development.

Glass is a mix of several inorganic minerals which are melted in a furnace.

Temperatures are maintained above 1000°C so the components can be
melted and homogenized. The molten glass is then drawn from plat-
inum bushings to form fibers which are collected to make a yarn which is
collected onto a bobbin. These bobbins are then processed into an elec-
tronics fabric designed to be used in production of laminate and prepreg.
Figure 2.1 is a review of the whole process from raw material to the fiber
and process to be woven as glass cloth.

11
 Figure 2.1: Glass fiber/glass cloth manufacturing process. (Source: Taiwan Glass)

Various Glass Types and Chemical Components

There are yarn manufacturers and fiberglass weavers and some electronics
glass fabric suppliers that do both. They all produce products that perform
similarly with similar mechanical, electrical and processing capability. These
are the common glass compositions that are used in volume or that are used
in special applications.

E-glass is the standard for high volume PCB designs. The composition of the glass
provides excellent overall mechanical, thermal and electrical performance
across a wide range of applications.

L- and NE-glass use a lower Dk glass fiber for high-speed digital and radio frequency
and microwave PCB designs. Use of this type of glass has increased significantly
in volume in recent years due to the lower Dk and reduced Df, a performance
attribute that is good for high speed and high data rate applications.

L2- and NER-glass provide an even lower Dk. This glass is new to the market and
currently under continued development. The glass composition offers an even
lower Dk than L- or NE-glass, thus enables higher speed and faster data rates.

12
T- and S-glass are high strength glass fibers that have been developed for woven
glass used in IC substrates due to the high dimensional stability and very low
expansion in the X and Y axes. This makes them suitable for thin dielectrics that
closely match components of the IC package.

Each of these glass types has unique properties based on the composition of
the glass. When choosing a laminate system for a specific application, the pros
and cons should be analyzed (Table 2.1).

The raw material costs of these glass types are approximately 1x, 5x, 7x and
10x for E-glass, low Dk glass, L2/NER glass, and S/T glass, respectively. The
volume of L2/NER glass is very small since it is still in development and beta
testing. Low Dk glass and S-glass are much lower volume than E-glass due to
the high melting temperature and quality control requirements during each
process step, which are more difficult than on E-glass. Currently, there are only

13
a few low Dk yarn suppliers and therefore the total capacity of this glass type
is limited due to furnace capacity for making the yarn. However, low Dk glass
demand is increasing rapidly as 5G infrastructure continues to drive demand
and new capacity is coming online to meet the demand. L2/NER glass is facing
a similar limitation and is not yet readily available.

Glass Styles and Weave

Glass fabric used in PCB manufacturing is woven using a plain over-under
weave pattern. There are numerous yarns available to achieve the desired
thickness which can be seen in the warp (grain or machine direction) and fill
(cross-grain or cross-wise direction). These are defined by code in the way
shown in Figure 2.2.

Figure 2.2: Poly-code for glass yarn.

Based on the U.S. yarn designation system the poly-code can be decoded as
follows:

• First letter designates the yarn to be electronics grade

• Second letter indicates the yarn is made up of continuous fila-

ments

• Third letter indicates the diameter of the of the filaments that

make up the yarn

• First number indicates the yarn weight in length/weight

• Second number indicates that there is one yarn and it is not

twisted with another yarn

Yarns are twisted using 200 to 400 filaments. The filament diameters and
counts are shown in Table 2.2.

14
Laminators can combine glass and resin to achieve various thicknesses. As
a rule of thumb for new materials, a minimum of 0.2 mils of “butter coat” on
top and bottom of the laminate is designed in to ensure there is no weave
texture or glass-to-copper contact. If you take a nominal glass thickness and
add 0.4 mils, this would give the minimum possible thickness for a glass style.
However, for HSD designs, there are other considerations such as material
handling during processing, targeting a nominal thickness for ease of creating
stack-ups, adjustment of resin content to control Dk, and other functional
needs that are part of the development of a good construction table.

Table 2.3 shows the most commonly used glass styles for E-glass. Low Dk glass
has a different density and thus slightly different weight.

15
Spread Glass
During the last 10 years, the demand for spread glass fabrics is becoming a
basic requirement for high-speed digital applications. The recent advance-
ments in the spreading process for glass fabric have resulted in the vast
majority of glass now being spread. There are several methods used to expand
the yarn to allow resin to more easily penetrate into the yarn. Figure 2.3 shows
the improvement that has been made by leading glass weavers to improve the
overall wet-out and, ultimately, the CAF performance of the composite, as well
as reducing the fiber weave effect.

16
While the benefits of wet-out and reduction of FWE (Fiber Weave Effect) are
welcome improvements, there is a tradeoff. The tradeoff is that the spread
weave behaves like a strainer and reduces the resin flow from one side of the
glass fabric to the other because the windows between the yarns are much
smaller. This reduced side-to-side flow decreases resin availability for filling
the etched copper features, especially on heavy copper applications. Higher
resin contents and the use of generally more open weaves, such as 1080
compared to 1086, for example, may be a benefit, especially in applications
with copper weights of 2 oz. and greater.

Figure 2.3: Typical 106 E-glass in year 2000 (left) versus 106 spread in 2020 (right).
(Source: Isola Johann Schumacher Laboratories)

Clearly the process changes the structure of the thin glass weaves. The warp
yarn is not easy to expand or spread during processing since the warp yarn is
under tension control in the machine direction, unlike how it is in the fill direc-
tion. Depending on the glass style, the glass may still have some “windows”
between the weave as seen in Figure 2.4. Although the ultra-thin glass like
1035, which is popular for reduced thickness, glass weaves like 1067, 1086
and 1078 would appear to provide a more consistent dielectric base with glass
more completely spread, which reduces micro Dk effects. These images show
that difference and should be considered when choosing the best option for
the design.

Figure 2.4: Glass styles 1035, 1067, 1086 and 1078 showing E-glass “windows.”
(Source: Isola Johann Schumacher Laboratories)

17
What about weaves like 3313 and 2116? They are also spread, but since the
weave is very tight to begin with, the spreading process is more about “fluffing”
the yarn versus spreading the yarn. These two glass styles have very little if
any window and some believe provide the best option for reduction of micro
Dk effects and skew mitigation.

Glass Surface Finishes

Glass is a mix of inorganic components, so it requires a coupling agent or
silane coating to bond organic resin and inorganic glass fabrics. Various types
of silane coatings are used as the coupling agent between the resin and glass
fibers. The choice of silane is critical in maximizing the CAF performance and
thermal reliability of the bond between them. With the new generations of
resin systems, the match for a good bond with different resin formulas must
be carefully chosen.

New Reinforcement Development

Currently, 1035 and 1078 glass weaves are commonly used for ultra-low loss
materials and are 0.029 and 0.043 mm thick, respectively. Glass weaves like
1007, 1017, and 1027 have been developed and are only 0.011, 0.015 and
0.017 mm thick and weigh just 9, 11 and 18 g/m2 respectively. This fabric feels
like silk when held between your fingers. These ultra-thin glass fabrics have
been adopted for the IC substrate market.

Organic fabrics have been available in the market for years. They are usually
chopped into fibers of short length to form non-woven fabrics. However, the
composite modulus will be reduced compared to a woven fabric for this type
of material. One benefit of this type of material is that the dielectric constant
may be lower depending on the type of raw material itself. New developments
with organic fiber-based material may be a replacement for glass-woven
fabrics. These technologies are fast approaching as development continues
on a replacement for glass fabrics that are reaching limits of the performance
of the resin systems they are paired with.

18
19
 Chapter 3

All About Construction Tables

Building a Material Construction Table

We have covered information on resin, fillers, glass and silane which make up
the dielectric composite commonly used for high-speed digital designs. Before
we start discussing material selection, we should cover how these dielectrics
are designed to achieve nominal thickness. Given the resin and glass informa-
tion, the laminate manufacturer can create a construction table with an array
of core thicknesses and prepreg resin contents.

B-stage or prepreg is produced in a treating system with operators using

treated weight of the final product to measure the acceptability of the
product. Once the glass is impregnated with the resin, the thickness is set
using metering rollers to a precise thickness before the A-stage coated glass is
drawn into the treater oven. Once the composite is partially cured, a sample
of the B-stage is taken and the material is weighed to determine if it is within
the production specification using the test method IPC TM-650 2.3.16.2.6 This
method takes into account the basis weight variation within the glass roll. The
treated weight is then converted into a resin content percent using IPC TM-650
2.3.16.1. This is the value that is used in the laminate and prepreg construction
table and is the resin content on the basis of weight.

In designing the B-stage for core or prepreg, one must take into account
the resin and glass density in order to determine the ratio that is needed to
achieve the target thickness. Resin density can vary with the type of resin, the
type of filler, and whether a reacted or solid flame retardant is used. With the
various combinations of options, the range of density can be as low as
~1.2 g/cm3 to about ~2.1 g/cm3. In addition, the density of E-glass and low Dk
glass differs. Those differences can affect the final thickness a few tenths of a
mil per ply of glass.

21
For example, if you have two resin systems, one with a density of 1.4 g/cm3
and one with a density of 1.55 g/cm3, both applied to a 2x1035 E-glass core,
the final thickness at 65.5% resin content (RC) would be 4.15 mils and 3.83
mils, respectively. That is 0.32 mils difference in thickness which is significant
when trying to design a construction set to nominal thickness targets.

To create a core construction table, laminators use these five general design
rules that make using a material easier.

1. Design cores with 0.5 mil increments from 2 mils (0.051 mm) to
5 mils (0.127 mm) to span the needed Dk range of thin designs.

2. Include two-ply options down to ~3.0 mils where possible to

minimize Z-axis issues like CAF.

3. Ensure every core has adequate resin butter coat to ensure sepa-
ration between glass and copper foil, usually a minimum of 0.2
mils per side. Poor butter coat can result in problems resolved
years ago such as weave exposure, weave texture, and dryness
(Figure 3.1).

4. Use the lowest cost glass with spread weave to maximize overall
skew and micro Dk performance.

5. Use B-stage building blocks that allow the maximum flexibility

to fill the construction table while minimizing the number of
B-stage options required to create it.

Figure 3-1: Butter coat thickness example. (Source: Isola Johann Schumacher Laboratories)

22
 This is an example of how a 0.102 mm (4 mil) core is designed using a 3313
glass style. The term “height” is used to identify the thickness of the glass and
resin of a unit volume, in this case cm2.

Hg – Glass height (cm) Wr – Resin weight (g/cm2)

Wg – Glass weight (g/cm2) ρr – Resin density (g/cm3)

ρg – Glass density (g/cm3) Hf – Laminate thickness

Hr – Resin height (cm) RC% – Resin content % by weight

Hg = (Wg/ρg) = (0.0081 cm2/2.54 g/cm3) = 0.0032 cm

Hr = Hf – Hg = 0.0102 cm – 0.0032 = 0.007 cm

Wr = (Hr * ρr) * (mm2/cm2) = (0.007 cm * 1.39 g/cm3)

* 100 mm/cm = 0.097 g/cm2

RC% = (ρr * Hr)/(ρr * Hr + Wg) = (1.39 g/cm3 * 0.007 cm)

/ (1.39 g/cm3 * 0.007 cm + 0.0081 cm2) = 54.6%wt

To achieve the target thickness, the retained resin percent or resin content
percent, the value would need to be 54.6%. In addition to that value, we want
to ensure adequate butter coat. We check the nominal glass height of 3313,
which is 0.080 mm, and find that we have 0.102 mm - 0.08 mm = 0.022 mm
or 0.87 mils. This gives us 0.43 mils per side of butter coat which is adequate.
There is also some resin loss that occurs around the perimeter of the laminate
during lamination. The final RC% would be based on the resin flow of the resin
system and then adjusted and optimized based on thickness testing.

For a prepreg construction table, the laminator needs to consider the widest
range of applications. Typically, one glass style may be used to create two or
more thicknesses using different resin contents. Prepreg plays an important
role in meeting specific dielectric thickness targets and supplying enough resin
to fill in the copper inner layer pattern during lamination. A range of prepreg
options with various glass styles are typically used to give the designer options.

23
Table 3.1 is an example of five different thicknesses for one glass style and the
filling capability of the specific resin content between two inner layers with the
same remaining copper. Not every glass style will need to have five different
resin contents, as long as the designed options provide small enough thick-
ness increments. This allows the designer to select the prepreg that will meet
thickness requirements to ensure the electrical performance is acceptable.

We also need to consider the resin loss for prepreg around the perimeter
of the panel. The final thickness is going to vary based on several factors
including the press heating profile that determines the viscosity of the resin,
the press pressure and application timing, the design of the perimeter flow
control pattern, and the design of the circuitry on the layer. For Table 3.1, the
fill capability is strictly volumetric and does not take into account these vari-
ables. Proper determination of thickness comes with regular process control
monitoring to fully understand the resulting thickness using the fabricator
press process.

Dielectric Properties
The permittivity (Dk) and the loss tangent (Df) are commonly determined by
bare or etched “laminate” test methods, most of which are defined by IPC
TM-650. The methods, such as Bereskin Stripline, Split Cylinder Resonator,
Split Post Resonator, Fabry-Perot Open Resonator and Stripline Resonator,
are all tests that require removal of the copper cladding and thus test only the
dielectric properties.

24
The methods can be sorted into two main groups. One group is having the
electrical fields perpendicular to the material surface. Those are called “out-of-
plane” methods. Bereskin Stripline or Stripline Resonator (IPC-TM650 2.5.5.5)
would fall into that group. The second group has the fields parallel to the
surface and are referred to as “in-plane” methods; SPC, SPDR, FPOR are all
part of that group.

Within the two groups, these methods provide similar values within the range
of each method’s test capability, but are limited to the frequency they can test.
However, based on the anisotropic nature of woven glass-reinforced mate-
rials, there is a difference between the in-plane and out-of-plane results.

Most of the test methods generally require a thickness greater than 20 mils in
order to test the dielectric properties. The dielectric may be stacked to achieve
the final thickness required by the fixture used, which may result in slightly
lower values due to the tiny air gaps between the laminates and the fixture
used. The 2.5.5.5. and Bereskin methods use a copper conductor standard
that also results in a small air gap between the dielectrics.

Another suite of test methods work with copper-cladded laminates. Structures

are created (e.g. transmission lines or line/ring resonators) and measured with
vector network analyzer equipment. From those results, Dk and Df values can
be extracted. The main difficulty is, however, that the separation of copper and
dielectric losses are not easy, so quite often, copper roughness related losses
are lumped into the Df values reported, resulting in higher than expected
dielectric loss numbers.

The dielectric properties are determined by the combination of the resin and
glass properties and can be estimated using the rule of mixtures. The electrical
properties of glass are shown in Table 3.2 and resin electrical properties were
shown in Table 1.1.

25
The resulting composite (resin + glass) Dk and Df is determined by the resin
content percent by volume. To demonstrate this, the charts in Figure 3.2 show
a plot of the Dk and Df of four laminate test samples that were made with
various resin contents and tested using the Bereskin Strip line test method.
These kinds of tests are used to develop a full construction table that uses
various resin content % for each laminate and prepreg. Testing every combi-
nation of constructions would become cost prohibitive and is not necessary
given that the values closely follow a linear function.

This method is used to determine the Dk and Df regardless of glass style and
produces reasonably accurate values that are a starting point for a stack-up.
This particular set of data uses four different RC%vol values to determine the
properties based on the RC%vol. These values are then converted to RC%wt for
the construction tables provided by the laminate supplier.

Figure 3.2: Test values plotted to find the equation for Dk and Df—Node 4 @ 8.9 GHz.
(Source: Isola Johann Schumacher Laboratories)

For the product shown in the charts in Figure 3.2, you could expect a 3313
glass with a volume RC%vol of 70% to have a weight RC%wt of 57%. Using the

26
equations for each property, we can calculate the anticipated Dk and Df:
Dk = -2.29 * 0.70 + 5.94 = ~4.34
Df = 0.0293 * 0.70 - 0.0056 = ~0.015

Therefore, the Df is 0.015 for a 3313 prepreg with 57% RCwt as listed in the
construction table at ~8.9 GHz. This is repeated for each node and the table
can be filled in using the equations. Followup testing over time confirms the
values and adjustments made if needed.

Dkdielectric versus Dkeff

One of the most common misunderstandings is that Dk of the dielectric as
shown in a construction table is going to be the same as the effective Dkeff
as extracted from a PCB. That’s not necessarily the case. Bert Simonovich7
describes the reason for these differences as related to the roughness or
smoothness of the copper foil in the PCB DUT. We should also note that
the losses are also going to be influenced by the difference in roughness or
smoothness of the copper foil. Depending on the extraction method, those
additional losses will be added to the Df, making that number an “effective
Df” as well. In addition, as the frequency increases, all sources of loss become
relevant.

When designing a stack-up, the prepreg Dk found on the data sheet or

construction table is often considered a constant. Nothing could be further from
the truth.

Resin filling of the etched copper features is consistently overlooked in stack

up design. First, the Dk between the transmission line and reference plane
changes across a prepreg dielectric. As the resin is redistributed during
re-lamination of the PCB, the thickness between conductors is reduced from
the starting thickness. Second, the resin required to fill the etched copper
features may be inadequate and glass-to-copper contact may occur in areas
of the board where resin fill volume required is higher than other areas in that
dielectric opening. This can result in small differences in the Dk from one loca-
tion to another.

Resin Filling
Starting thickness of a prepreg dielectric is misleading and some designers
forget to consider the resin fill requirement. Prepreg thickness posted in a

27
construction table is the starting point. This is important to understand. During
lamination, the thickness of the prepreg becomes thinner between conduc-
tors, an all too often forgotten when creating a stackup.

Figure 3.3 shows how the resin is distributed during lamination and how the
prepreg thickness changes between conductors. When the copper foil pattern
is etched on the inner layer, this leaves remaining copper on the surface that
defines the design. The volume of copper that is removed must be replaced
by resin from the prepreg. Using a volumetric calculation, we can predict the
theoretical thickness after lamination.

Figure 3.3: Resin filling reduces prepreg thickness. (Source: Isola R&D)

This calculation uses a common very-low-loss resin system at 76% RC. Using
the remaining copper at 20% to represent a signal layer, we would estimate
the resin volume required as 1.25 * 80% = 1.0 mil of resin thickness per unit
area is required to fill the air gap. After lamination the thickness between the
conductors is reduced from 6.4 mils to 5.4 mils because resin was consumed
to fill the copper features.

28
Because the resin content between the conductors is now reduced, the dielec-
tric constant is also going to change since it is a function of the composite resin
content, specifically above the transmission line. For the 1067 76% RC prepreg,
the starting Dk is ~3.10 while after lamination the theoretical Dk at 72% RC is
~3.2. Given the core is a 2x1067 72% RC and uses the same glass style, the
structure is now a symmetric Stripline with pure resin on the side walls. This
means for the purpose of calculating the impedance we can use a Dk of 3.2.

To demonstrate the difference, we used the EEWeb online impedance calcu-

lator which uses IPC-2141A 2D equations (Figure 3.4). Note that this model
does not take into account the surface roughness of the copper foil and there-
fore will differ from extracted values.

Figure 3.4: Impedance calculation comparison.

(Source: Asymmetric Stripline Impedance - Tool | EEWeb Community)

For this case, the Asymmetric Stripline model was used to estimate the imped-
ance using the initial prepreg thickness and Dk, which yielded 50 ohm imped-
ance with a 5.55 mil trace width and 1.25 mil trace height. Making the correc-
tion to account for resin consumption to fill the inner layer pattern and the
resulting thickness and Dk, the impedance with no change to line width would
be 46.4 ohms or about a –3.6 ohm shift. Correcting the line width to 4.8 mils to
account for the resin fill, results in impedance of 50 ohms using the corrected
prepreg thickness and Dk.

Incorrect impedance problems can be difficult to track down. Selecting the

correct prepreg, glass style and resin content to achieve the desired struc-
ture is important to minimizing stackup related design issues. Accounting for
the change in dielectric thickness is a common error that is easy to correct to
arrive at the desired impedance.

29
 Chapter 4

Copper Foil

Copper foil is the standard conductive layer used for metal-clad laminates,
although other options are available. There are two main types of copper foil
used for PCB boards today: electrodeposited (ED) foil and rolled annealed
(RA) foil. ED copper foil is produced by a continuous process which yields
a well-controlled product in mass volume and low cost as compared to RA
copper foil. ED copper foil has a wide range of thicknesses, from 5 micron to
400 micron, for PCB applications. IC substrate application requires an ultra-
thin foil which is supplied on an 18–72 micron copper carrier and range in
thicknesses from 1.5 micron to 5 micron.

Rolled annealed foil yields a very smooth surface where the process deforms
the copper crystalline structure to achieve thickness. Unfortunately, the foil
is only available in a 25” wide format. This makes use of the foil difficult
in the large batch processes used by laminators to manufacture laminates.
Most processes are designed around a 50 inch wide machine direction of
the glass using large hydraulic presses with platen sizes to accommodate
the 50 inch glass width. Use of the RA foil reduces productivity and results
in higher cost. With the development of newer smooth ED foils that are as
smooth as RA foil, the need for RA foil and the associated cost has been
largely mitigated.

ED copper foil that is commonly used for radio frequency and microwave
and HSD designs—where high frequency boards require very low rough-
ness—is required to reduce the conductor losses. Roughness is one of the
key factors for high frequency applications where conductor loss is the
secondary contributor to overall loss after dielectric losses at frequencies
over about ~10 GHz.

31
Copper Foil Technology Development
With the introduction of lead-free compatible materials in ~2005 with a lower
overall Z-axis CTE, copper bond strength decreased with the addition of
fillers in the materials. Copper suppliers began work on improving the bond
strength of the copper foil. When finer transmission line features became
more common in designs, the industry needed a better foil for etching fine
lines. Reverse treated foil (RTF) is foil that has the laminate side treatment on
the drum side of the foil. RTF foil was seen as the way to mitigate problems
and was the first step toward making smooth copper foils. Typical roughness
was about 4–6 µm.

The current development efforts have been focused on newer foils such
as HVLP3 or HVLP#, where # indicates the generation. While the new treat-
ments resulted in a much smoother, laminate side copper foil surface profile,
bonding resin to ultra-smooth copper foils has proven to be challenge. The
smooth laminate surface left after removal of the copper foil has created an
adhesion challenge that can lead to what is known as a “bond line failure.” This
happens when the copper treatment chemistry remains on the smooth lami-
nate surface and interferes with prepreg and laminate bonding. The failure
modes are delamination or CAF failure at this interface.

The development of high speed, ultra-smooth copper foils required new tech-
niques for achieving a reasonable bond to the new generation of resin systems

32
like PPE/PPO. ED copper foil manufacturers improved their technology to
reduce roughness which in turn improved the SI performance of the foil on
the composite. Table 4.1 shows the commonly used terms to describe general
roughness parameters.

The new foil types were developed for use in the EV battery foil market, but
they have been adapted to the PCB industry for high-speed digital and radio
frequency designs. Battery foil plating technology requires fine grain copper
and very smooth surfaces. To achieve that requirement, the titanium drum
surface is polished to a surface finish of less than 2 µm. The fine copper grain
structure produces a matte side finish of ~1.5 µm. The most recent develop-
ments in foil processing technology have allowed the manufacturers to achieve
a surface roughness of <1 µm, with some manufacturers claiming to be able
to achieve 0.5 µm. Given the ultra-smooth surface that must be bonded to the
resin, a new approach to treatment was required.

DSTF® (drum side treated foils) or RTF (reverse treated foils) have been used
for some time with the benefit being better defined traces after etching. This
foil is treated on the drum side for bonding to the dielectric during lamination
of the copper-clad laminate. This type of foil provides a very smooth surface
against the laminate.

New generations of RTF foil, known as RTF2 or RTF3, are being developed
by many foil suppliers for ultra-high-speed applications. The foil supplier
combines RTF foil with fine grain structure to produce a very smooth foil and
achieve a Rz roughness of about 2.3 µm or less on the laminate side surface.
This surface is then treated with bonding chemistry that will chemically bond
to the laminate. The major difference between an HVLP foil and RTF2 foil is the
resist side roughness. Combining these very smooth foil technologies with a
nonmetal modifying bond treatment on the resist side of the foil by the PCB
fabricator prior to multilayer lamination produces nearly ideal transmission
line surfaces.

Industry Copper Specification, IPC-4562

The IPC-4562 "Metal Foil for Printed Wiring Applications" defines the profiles
of copper foil (IPC-4562 Table 3-1). This specification has not been updated
recently and the roughness classes listed there are not suitable for the current
and future design requirements for high speed digital or RF/MW designs.
Because there is no specification, selecting a copper foil for the laminate mate-

33
rial requires measured data to understand the performance of a given grade.
There is also a need to find a balance between performance and cost.

For HSD designs, copper foil

with Rz (ISO) values of ≤ 2.5
µm are desired to minimize
conductor losses at higher
frequencies. The IPC table
shown in Table 4.2 demon-
strates that the current speci-
fication is lacking any rough-
ness information for VLP
(very low profile) foil below 5.1 µm and therefore the specification of the foil
by the OEM or PCB fabricator must be AABUS (as agreed between user and
supplier).

Defining Copper Foil Roughness

There are several different roughness parameter definitions that can be used
to explain the foil roughness. Rz is the most commonly used definition by the
ED copper foil makers and PCB fabricators. This value is then used by designers
when modeling their designs. Rz (ISO) can be a contact or non-contact method
that uses the average value of the absolute values of the heights of five
highest profile peaks and the depths of five deepest valleys within the evalu-
ation length. Most copper foil suppliers provide an Rz (JIS) value on their data
sheets which is a typically derived from a contact method using a stylus. The
JIS method results in slightly lower values primarily due to the difference in
calculation methods for each specification.

The measurements from these two methods are then used to determine the
resulting value as follows (Figures 4.1 and 4.2).

34
 Figure 4.1: Determination of copper foil surface roughness, Rz.

Ra is another value that is sometimes shown on copper supplier data sheets.

The Ra value is the average roughness of the surface. It is the area between
the roughness profile and its mean line, or the integral of the absolute value of
roughness profile height over the evaluation length.

Figure 4.2: Determination of copper foil surface roughness, Ra.

35
At the time of this writing, the industry has not settled on the equipment and
the method required to measure surface roughness on very smooth copper
foil. Foil suppliers have been using the smallest denominator, which is Rz by
stylus method, which is not suitable for foils smoother than IPC-4562 VLP defi-
nition. This is likely why there are no further classes at this time.

Round Robin testing demonstrated the difficulty in obtaining repeatable

results that correlate from one lab to the next. This makes comparison using
only surface roughness difficult when considering and selecting different
grades of foil. The only way to truly compare one HVLP copper foil to another
HVLP copper foil is to test them side by side in an SI test vehicle. Comparing the
simple roughness value listed on the copper supplier data sheet does not provide
the entire performance picture.

If that is true, what other things does a designer need to consider when devel-
oping a PCB and modeling the structures? There are several different attri-
butes of the roughness that cannot currently be modeled easily. While the
copper foil may appear to be smooth and even shiny, when you take a look
using an SEM under high magnification, you can see that the surface is not as
smooth as one would think.

Copper Foil Surface Roughness Factors

Skin Effect
The "Skin Effect" of a conductor (copper foil) is a result of the current distribu-
tion which is affected by the induced magnetic fields that force the current to
flow toward to the conduc-
tor’s surface as frequency
increases. Skin depth can
be calculated and can be
found at 10 GHz to be
only 0.66 micron as seen
in Table 4.3.

The example in Figure

4.3 demonstrates why
the surface roughness and the skin effect are important at high frequencies.
Higher roughness at the conductor surface results in higher losses as frequency
increases, while lower copper roughness at the surface of the copper results

36
in lower loss. However, there is a tradeoff of lower bonding strength of the foil
when smoother foil is used. The user needs to consider this as well.

Figure 4.3: Example of current flow path moving to the surface.

Modeling the Roughness

The most sophisticated modeling tools employ several methods for modeling
the roughness of the copper foil, called “cannonball” or “snowball” methods.
These methods are used in conjunction with actual measurements and refined
as needed to get accurate representations of real board performance. A closer
look at copper foil morphology suggests there is more work to do to refine
these models, especially as frequencies increase and higher data rates are
needed.

The following information describes why the simple use of an Rz value is

misleading.

Morphology—Shape, Size and Density of the Treatment

Smaller copper treatment particle size increases the contact area resulting in
increased bonding strength, but this also increases loss. Smaller copper treat-
ment particle size may reduce adhesion between copper particle structures.

The shape of the treatment influences consistency of the loss because various
angles of the treatment will reflect more or less energy. Larger, inconsistently
shaped treatment will result in higher loss, while smoother, more consistent

37
 Figure 4.4: High-angle image of treatment side of the copper foil.
(Source: Isola Johann Schumacher Laboratories)

treatment will result in lower loss. Figure 4.4 shows how there are differences
in the way the treatment appears at high magnification using an SEM at a high
angle. The left image shows the treatment appearing as “stalagmite” shape that
is used for anchoring into the laminate surface, while the right image shows an
angular shape of the treatment even though the Rz values were similar. These
differences in treatment result in differences in conductor losses.

With these two examples, it should be clear why there are differences in
performance even when the Rz values are reported as equivalent. The right
image in Figure 4.4 shows inconsistencies in the size and shape of the treat-
ment that results in less than desired performance compared to foil with
similar ~ 2 micron Rz roughness values. Ideally, the designer should use a foil
like the example on the left. The treatment is consistently similar and smaller
in particle size.

Drum Side Titanium Drum Polishing Roughness

Copper foil is plated onto a titanium drum. These drums are polished to a
fine surface finish to achieve the lowest possible profile. This process leaves
a pattern of ridges from the polishing brushes that can be seen in Figure 4.5.
At low frequencies, these ridges are of no consequence. However, as the
frequency increases significantly, the directionality of these ridges do result in
noticeable differences in loss when comparing X and Y directions This effect is
similar to how the glass weave causes micro Dk effects.

38
 Chemical Treatment
Early low profile VLP or more
commonly called HVLP products
employed the use of an additive
process to create nodules for a
mechanical bond to the resin. While
these products were able to achieve
a lower profile and reduce conductor
losses, the nodules could not easily
be further reduced in size to achieve
Figure 4.5: Treatment side of the copper foil. even lower loss without significantly
(Source: Isola Johann Schumacher Labs)
impacting the bond strength. An
even smoother foil surface was needed and the additive treatment process
was replaced with a chemistry that left the surface much smoother.

Copper foil is an inorganic material and the resin is an organic material. This
required a special type of silane coating with two different functional groups
for the coupling agent to bond the resin (organic side) and copper (inorganic
side) for a chemical bond. A well-matched chemical treatment provides good
bond force along the boundary area that holds up to critical processes and
simulation testing.

Testing is Required
The differences described above influence the actual performance of the
laminate material, so the laminator must understand the differences between
multiple foils that claim to be ultra-smooth. Copper foil supplier data sheets
do not tell the whole story about the performance in real PCBs. By testing
the copper foils on a standardized test vehicle, the laminator can sort various
grades of copper.

While chemical bonding treatments hold great promise, there are drawbacks.
The chemical treatments have a shelf life and they must be carefully managed
to ensure the treatment does not age out. There is still a lot to be learned
by the copper suppliers at this time. While glass suppliers have been using
silane coatings for many years, foil suppliers are just now developing expertise
and process capability to get the right amount of the right coating adhered to
the surface to ensure good bonding for the specific resin system. Comparison

39
 Figure 4.6: Comparison of < 1 micron copper foil. (Source: Isola R&D)

testing between multiple copper foil suppliers and grades demonstrates this
point. Electrical performance, CAF performance, thermal reliability perfor-
mance, and processability are critical performance attributes that must be
carefully balanced and not compromised.

In the example in Figure 4.6, the electrical performance of ~1 micron Rz foil

demonstrates that there is a significant difference in conductor loss perfor-
mance between the various 1 µm foils. Make sure your supplier has a solid
knowledge of the performance of the foil they are using and make sure to
know the manufacturer and the grade that goes into your product. Changing
copper alone can make a huge difference in the actual loss performance.

Bonding Treatments of Copper Foil—Prepreg Side

The copper foil laminate side roughness is only half of the story of conductor
loss. The bonding treatment required for good prepreg to copper foil adhe-
sion is just as important. If you invest in the higher performance ultra-smooth
copper and then accept the typical oxide treatment, you have wasted your
money.

Historically, copper foil has been treated with various types of chemistries
to create a fine copper topography that behaves like a tooth to “bite” into
the resin and create a mechanical bond. This mechanical structure gives the
copper excellent bonding strength which gives the composite a high level of

40
thermal reliability and PCB assembly robustness. But just like the laminate
side roughness, the roughness or skin of the transmission line is critical to
reducing the conductor losses.

Figure 4.7 shows the roughness of the copper foil and how that the bond
was achieved historically. This “tooth” profile was used to create the mechan-
ical bond. The resist side was then roughened in the oxide coating process
to achieve adequate bond strength to the prepreg during the relamination
process.

Figure 4.7: Half-ounce HTE, RTF and HVLP copper foil. Arrows indicate top surfaces.

41
 Chapter 5

Control of Electrical
Performance
With many things influencing electrical performance, like resin system, glass
weave, copper treatment roughness and impact of alternative oxide, what
options are available for the user to make sure that the PCB works as intended?

Electromagnetic field simulations have improved significantly in recent years,

but they all depend on defining the structures correctly. Geometries can be
found quite easily by cross-sectioning. For Dk/Df values, it’s important to
understand the methods that have been used at the CCL supplier to deter-
mine them. There really is no magic Dk number to plug into a simulation tool
to get everything right. Even so-called ‘design-Dk’ values are just measurement
by a different test method that may or may not reflect field orientation in a
given design.

As covered above, we know that the issue of copper roughness is making

things very complicated. The roughness created by the alternative oxide will
be different from PCB supplier to PCB supplier, so there are no good rules of
thumb that one can apply in a model with 100% confidence.

The only way to be sure is to measure characteristics on the final PCB. Two
major tests are employed here:

Impedance Testing by TDR

A standard in the PCB industry for many years now, this tool is especially
powerful for monitoring consistency in volume production. It will ensure that
dielectric thicknesses, line widths and Dk values do not deviate too much from
expectation.

43
Insertion Loss Testing
Quite a few methods have been proposed and found their way into IPC-TM650,
like EBW (effective band width), RIE (root impulse energy), SET2DIL (single
ended TDR to differential insertion loss) and SPP (short pulse propagation)
[all described in IPC-TM650 2.5.5.12]. But in the more recent past, the ‘Delta-L’
method gained a lot of acceptance and is more or less the standard method
now. Testing insertion losses that way will include all base material and PCB
processing impact, so the results are a good predictor of the actual product
performance.

44
45
 Chapter 6

Automotive Electrification

Electrification in the automotive sector is strongly driven by environmental

concerns and especially the reduction of carbon-dioxide emissions. This has a
major impact on our mobility choices and leads to significant changes within
the car itself. The combustion engine is replaced by an electric drive (or drives)
and a battery package. This has an effect on the whole powertrain, power
distribution systems, and controls—including AI and communications for
autonomous driving.

Historically, the voltage levels in combustion engine vehicles have been 12 or

24 VDC. That level was raised to 48 VDC to enable the operation of all the ever-
increasing electrical consumption requirements. But with the electrification
of the powertrain, the voltage range requirements are now 400, 800, or in the
future, even 1000 VDC and higher are reached.8 Different components and
devices of the drive train and the rest of the car operate at different voltage
levels. Thus, in addition to battery monitoring and managing electronics,
inverters and converters are needed within the powertrain, which can step
voltages to different levels or invert AC to DC and vice versa.

Depending on the technology, the electronics used within the power train must
withstand the higher voltage levels. In addition to isolation on the surface and
within the boards, which is usually a matter of spacing, sufficient CAF resis-
tance of the base material must be ensured.

HSD and Automotive CAF Testing

Typical CAF test conditions for the computing, communication and automo-
tive industries are 15 VDC to 100 V (DC) and 500- or 1000-hour test duration.
Due to the high voltage levels within the electrical power train, the 100 V CAF
test is no longer sufficient to model the long-term reliability. CAF testing at
much higher voltages is required to ensure that PCBs are suitable for high

47
power applications. So, the chosen base material must show a CAF resistance
performance at voltages of 1000 V or beyond. A material may be sufficient for
high- speed digital application that operates at lower voltages, but as voltage
levels increase for power distribution a higher voltage level will be needed for
them as well.

We have learned that the step from 100 V to 1000 V test voltage has led to the
formation of a failure mode that is not new but very rarely seen when using
the 100 V CAF test. Copper migration through the resin has been observed
when dielectric thickness is insufficient. This mode has not been sufficiently
investigated within the industry and requires more study.

The root causes, factors affecting copper growth, as well as accelerating factors
and the failure mechanism itself, are currently under extensive investigation.
Furthermore, the conditions of an adequate accelerated life test for different
high voltage devices are not yet determined. Test voltage levels range between
250 V up to 3000 V which is the current lab capability that is available. Also, the
common 1000 hours of test duration are extended to 2000 or 3000 hours. Reli-
ability over an extended life cycle of an electric vehicle is the primary concern.

For a combustion engine, car operation time was driving time. However, an
electric vehicle is not only powered during a drive, but the system is also oper-
ating during the charging process. The operating time of the high voltage
systems is increased and thus the 1000-hour ALT, which corresponds to 10,000
hours of operating time under accelerated conditions, must be extended for
a longer period.

As already mentioned for the 100 VDC CAF test conditions like voltage, the
duration, feature spacing, and the construction of the TV are not standardized
and differ depending on the OEM-specific requirements. Overall, there is still
uncertainty about which test conditions and acceleration factors reflect real
applications. For the base material supplier, it is problematic and indeed risky
for the supplier to make a general statement about high voltage CAF resis-
tance without appropriate testing of the material using a standardized test
vehicle and test conditions.

Current Carrying Capacity

With the increase in voltage levels, higher current carrying capacities are
needed to power electronic devices. Heavy copper is the common technology

48
used to enable this with copper weights of 3 oz. up to 12 oz., which can make
power electronic PCBs very heavy. Copper has excellent thermal conductivity
which helps to dissipate the high amount of heat induced by power losses.
Heavier copper has challenges in processing beginning with etching of inner
layer structures. The process can be slow and side wall features require a well-
controlled etching process to ensure reliability.

Furthermore, these structures must be filled properly during multilayer

production, therefore a prepreg with high resin content and suitable flow
behavior is required. Refer to Figure 3.3. Dynamic and static thermal loads
during testing or operation of these devices can cause cracks at the heavy
copper flanks and corners within the
resin. Resin systems which show a
higher resistance against cracking Today’s commonly
and crack propagation have an used semiconductors
advantage when used within heavy
copper boards. are silicon based.
This semiconductor
Heat Generation
With high current, heat is generated material is approach-
on the boards and results in power ing its performance
loss while devices are working. Minia-
turization, where densification of
and efficiency limits.
components are installed in close
proximity, can save space, but results in intensifying this problem. Tempera-
ture may also be further increased by the introduction of a new power semi-
conductor technology.

Today’s commonly used semiconductors are silicon based. This semicon-

ductor material is approaching its performance and efficiency limits. The
upcoming new power semiconductor generation for the electrical powertrain
will be based on silicon carbide (SiC), which is part of the wide band gap semi-
conductors family. Energy loss is reduced using SiC chips in comparison to
silicon-based semiconductors which makes the electronic devices work more
efficiently.

More energy is available and thus the driving range is increased. Higher
switching frequencies and e.g. faster charging of batteries is possible. These

49
are some of the advantages of SiC chips.9,10 Due to the lower heat losses, SiC
chips can operate at higher junction temperatures (Tj) up to 175°C or even
beyond11. The overall increase in temperatures of the electronic devices the
designer must deal with, will lead to the use of different active or passive
cooling technologies. Thermal management and heat spreading become
necessary.

Common FR-4 type base materials that are usually used in PCB production
temperatures around 150°C are already challenging. The new FR15.1/0 mate-
rial category defined by UL should help to identify materials with increased
thermal stability and offer a choice of materials for these thermally demanding
applications.

Temperatures levels up to 175°C make it necessary to develop a new base mate-

rial solution so that cost of intensive cooling or thermal management systems
for the components can be reduced. Benzoxacine is an example for an innova-
tive resin system that was developed to withstand operating temperatures up
to 175°C. This resin system shows an increased thermal stability compared to
the common epoxy resins, but at the same time has the advantage of a FR-4
similar behavior during PCB production. Standard manufacturing processes
can be used and the resin system enables higher operating temperatures up
to 175°C while still having the advantage of FR-4 similar processing.

Automotive electrification is pushing the boundaries of the base material.

Increased voltages make high voltage CAF resistance of base material neces-
sary. Increased current flows and the resulting use of heavy copper requires
a base material with appropriate resin filling behavior. The material offering
must include very high resin content prepreg to ensure proper filling of the
heavy copper structures. And finally, the base material must withstand the
increased thermal load. Standard FR-4 materials are reaching their limit
when it comes to high voltage applications and new base materials should be
selected for these applications.

50
51
 Conclusion

This book did not cover thermal reliability requirements in any great detail.
Lead-free capable materials have been well established since the initial imple-
mentation of RoHS in 2005. They should be able to handle standard data sheet
tests per IPC specifications. While OEMs and PCB fabricators have extended
these test requirements—for example, 6x260°C to 10x260°C reflow simula-
tion—given good PCB fabrication practices, lead-free compatible materials
should easily pass these tests.

Where we see the challenges is when new tests and new conditions are
applied to qualification testing protocols as we read in the automotive CAF
testing arena. There are ever-increasing requirements for thermal cycling for
high-speed digital applications that employ HDI technologies such as stacked
microvias and stacked microvias on buried vias. These high-density structures
are becoming more common on large format PCBs and applying standard IPC
testing as seen on a data sheet simply does not provide adequate information
for design purposes.

Hopefully, with the information provided in this book, you will have enough
new information to understand how the material is made and how the mate-
rial will perform. The combination of options is based on raw materials and
those options can be seen in the laminate supplier’s offering. Each mate-
rial offering has been developed to address new requirements at the time
of development. These materials have gone through a significant amount of
internal testing and external qualification testing to ensure they will perform
as needed.

So how do you know which laminate system you should pick? The easiest way
is to contact your laminate supplier directly and ask a lot of questions about
the performance attributes. Those of us who have been around a while have
seen a lot and can give you a good start on which material to use. We may
end up recommending our standard FR-4 system, but we may have something
new that offers a significant advantage over previous legacy laminate systems.

52
So, what if you want to use material that you have used many times before?
There is nothing wrong with using a proven product unless the design sees
new operating conditions or design features that you have not used before.
A quick call to check with your supplier is an effective way to make it easier to
sleep at night.

The next best thing is to test the potential material candidates. It will be less
expensive to do the testing up front than to re-spin the design. An experi-
enced laminate technician with a wide range of career experiences from mate-
rial development, PCB processing and OEM qualifications for designs across
a wide range of applica-
tions makes your supplier
an integral member of
your team to find solu-
tions that will move your
design to market faster
with fewer headaches. You
may even find they have
developed the data you
need to justify your mate-
rials design choice. A call
to ask is a low-cost way to
get your project moving.

As you can surmise, selecting the proper base material can be challenging,
especially with so many options in the market today. We hope this book
has provided you with a fundamental understanding of the building blocks
required to produce laminate and prepreg materials and the wide range of
performance characteristics they exhibit. With this information now in hand,
the reader should be better equipped to make an informed decision when
making future material selections.

53
 References
1. Grace Jeffers, “Learn About Laminate: How Laminate Was Invented
and How It Is Made;” Retro Renovation, June 2013.
2. PCBWay
3. Encyclopedia.com
4. PCBWay
5. PCBWay
6. IPC TM-650 Test Methods Manual, industry guide for test methods.
7. Bert Simonovich, “A Practical Method to Model Effective Permittivity
and Phase Delay Due to Conductor Surface Roughness,” DesignCon
2017.
8. ZVEI—German Electrical and Electronic Manufacturers’ Association,
Voltage Classes for Electric Mobility, December 2013.
9. MTI Instruments Inc., “Silicon Carbide Versus Silicon in EV Power
Electronics;” AZoM, April 19, 2021.
10. Murray Slovick; “Making the Jump to Wide Bandgap Power;” Elec-
tronic Design, December 2017.
11. B. Wrzecionko, J. Biela, J. W. Kolar; “SiC Power Semiconductors in
HEVs: Influence of Junction Temperature on Power Density, Chip
Utilization and Efficiency;” IEEE, 2009.

Acknowledgments
I would like to thank the following colleagues for their significant contributions
to the collection of knowledge presented in this e-book. My Isola colleagues
are a handful of the best and brightest technologists in our industry. Without
their contributions, corrections and revisions, this work would not be a valu-
able resource for the reader.

• Alexander Ippich, Technical Director, Signal Integrity &

Advanced Technology Product Manager RF/Microwave OEM
Marketing Europe

• Dr. Fandy Wei 魏馥君, Senior Director, Asia OEM Marketing

• Steven Sekanina, Director, High Speed Digital Products

• Dr. Anna Graf, Head of Application Engineering Europe, OEM

Marketing Automotive

• Cory Zahringer, Marketing & Communications Manager

54
 Glossary of Acronyms
AABUS – As Agreed Between User and Supplier
CAF – Conductive Anodic Filament
CCL- Copper Clad Laminate
CTE – Coefficient of Thermal Expansion
DSTF® - Drum Side Treated Foil
DUT – Device Under Test
EBW – Effective Band Width
ED – Electrodeposited
FPOR – Fabry-Perot Open Resonator
FWE – Fiber Weave Effect
HDI – High Density Interconnect
HVLP – “Hyper” Very Low Profile
IC – Integrated Circuit
PCB – Printed Circuit Board
PPE - Polyphenol Ether
PPO – Polyphenylene Oxide
PTFE – Polytetrafluoroethylene
RA – Rolled Annealed
RC% – Resin Content Percent
REACH - Registration, Evaluation, Authorization and Restriction
of Chemicals
RF/MW – Radio Frequency/Microwave
RoHS – Restriction of Hazardous Substances
RTF – Reverse Treated Foil
SEM – Scanning Electron Microscope
SET2DIL – Single-Ended TDR to Differential Insertion Loss
SPC – Split Post Cavity
SPDR – Split Post Dielectric Resonator
SPP – Short Pulse Propagation
TDR – Time Domain Reflectometer

55
 About Isola
Isola is a global leader in material sciences that began production of insulation
materials in 1912 as Continentale Isola Werke AG in Düren, Germany. In 1956,
Isola began production of copper-clad phenolic-paper laminates. Since then,
the company has acquired or merged with numerous laminate and prepreg
manufacturers such as Allied Signal, Norplex, Westinghouse, and Polyclad to
become one of the most recognized global brands in the industry.

Today, Isola designs, develops, manufactures and distributes copper-clad

laminates and dielectric prepregs used to fabricate multilayer printed circuit
boards. These materials span a range of applications from low-cost, high-
performance FR-4 epoxy systems to ultra-low loss dielectric materials.

Isola has seven manufacturing facilities, three R&D facilities, three state of the
art analytical services laboratories, and numerous technical support and sales
teams across Asia, Europe, and North America. Our global presence enables
Isola to service customers around the world.

For more information, visit Isola's website.

57