74F382 4-Bit Arithmetic Logic Unit

May 1988
Revised January 2004

74F382
4-Bit Arithmetic Logic Unit
General Description Features
The 74F382 performs three arithmetic and three logic oper- ■ Performs six arithmetic and logic functions
ations on two 4-bit words, A and B. Two additional Select ■ Selectable LOW (clear) and HIGH (preset) functions
input codes force the Function outputs LOW or HIGH. An
■ LOW input loading minimizes drive requirements
Overflow output is provided for convenience in twos com-
plement arithmetic. A Carry output is provided for ripple ■ Carry output for ripple expansion
expansion. For high-speed expansion using a Carry ■ Overflow output for twos complement arithmetic
Lookahead Generator, refer to the 74F381 data sheet.

Ordering Code:
Order Number Package Number Package Description
74F382SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74F382SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F382PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Logic Symbols Connection Diagram

IEEE/IEC

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74F382

Unit Loading/Fan Out

U.L. Input IIH/IIL
Pin Names Description
HIGH/LOW Output IOH/IOL
A0–A3 A Operand Inputs 1.0/4.0 20 µA/−2.4 mA
B0–B3 B Operand Inputs 1.0/4.0 20 µA/−2.4 mA
S0–S2 Function Select Inputs 1.0/1.0 20 µA/−0.6 mA
Cn Carry Input 1.0/5.0 20 µA/−3.0 mA
Cn + 4 Carry Output 50/33.3 −1 mA/20 mA
OVR Overflow Output 50/33.3 −1 mA/20 mA
F0–F3 Function Outputs 50/33.3 −1 mA/20 mA

Functional Description Function Select Table

Signals applied to the Select inputs S0–S2 determine the
Select
mode of operation, as indicated in the Function Select Operation
Table. An extensive listing of input and output levels is S0 S1 S2
shown in the Truth Table. The circuit performs the arith- L L L Clear
metic functions for either active HIGH or active LOW oper- H L L B Minus A
ands, with output levels in the same convention. In the
Subtract operating modes, it is necessary to force a carry L H L A Minus B
(HIGH for active HIGH operands, LOW for active LOW H H L A Plus B
operands) into the Cn input of the least significant package. L L H A⊕B
Ripple expansion is illustrated in Figure 2. The overflow H L H A+B
output OVR is the Exclusive-OR of Cn + 3 and Cn + 4; a
L H H AB
HIGH signal on OVR indicates overflow in twos comple-
ment operation. Typical delays for Figure 2 are given in H H H Preset
Figure 1. H = HIGH Voltage Level
L = LOW Voltage Level

Toward Output
Path Segment
F Cn + 4, OVR
A1 or B1 to Cn + 4 6.5 ns 6.5 ns
Cn to Cn + 4 6.3 ns 6.3 ns
Cn to Cn + 4 6.3 ns 6.3 ns
Cn to F 8.1 ns —
Cn to Cn + 4, OVR — 8.0 ns
Total Delay 27.2 ns 27.1 ns
FIGURE 1. 16-Bit Delay Tabulation

FIGURE 2. 16-Bit Ripply Carry ALU Expansion

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 74F382
Truth Table
Inputs Outputs
Function S0 S1 S2 Cn An Bn F0 F1 F2 F3 OVR Cn + 4
CLEAR L L L L X X L L L L H H
H X X L L L L H H
B MINUS A H L L L L L H H H H L L
L L H L H H H L H
L H L L L L L L L
L H H H H H H L L
H L L L L L L L H
H L H H H H H L H
H H L H L L L L L
H H H L L L L L H
A MINUS B L H L L L L H H H H L L
L L H L L L L L L
L H L L H H H L H
L H H H H H H L L
H L L L L L L L H
H L H H L L L L L
H H L H H H H L H
H H H L L L L L H
A PLUS B H H L L L L L L L L L L
L L H H H H H L L
L H L H H H H L L
L H H L H H H L H
H L L H L L L L L
H L H L L L L L H
H H L L L L L L H
H H H H H H H L H
A⊕B L L H X L L L L L L L L
X L H H H H H L L
L H L H H H H L L
X H H L L L L H H
H H L H H H H H H
A+B H L H X L L L L L L L L
X L H H H H H L L
X H L H H H H L L
L H H H H H H L L
H H H H H H H H H
AB L H H X L L L L L L H H
X L H L L L L L L
X H L L L L L H H
L H H H H H H L L
H H H H H H H H H
PRESET H H H X L L H H H H L L
X L H H H H H L L
X H L H H H H L L
L H H H H H H L L
H H H H H H H H H
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial

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74F382
Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

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 74F382
Absolute Maximum Ratings(Note 1) Recommended Operating
Storage Temperature −65°C to +150°C Conditions
Ambient Temperature under Bias −55°C to +125°C Free Air Ambient Temperature 0°C to +70°C
Junction Temperature under Bias −55°C to +150°C Supply Voltage +4.5V to +5.5V
VCC Pin Potential to Ground Pin −0.5V to +7.0V
Input Voltage (Note 2) −0.5V to +7.0V
Input Current (Note 2) −30 mA to +5.0 mA
Voltage Applied to Output
in HIGH State (with VCC = 0V) Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
Standard Output −0.5V to VCC under these conditions is not implied.
3-STATE Output −0.5V to +5.5V Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Current Applied to Output
in LOW State (Max) twice the rated IOL (mA)

DC Electrical Characteristics over Operating Temperature Range unless otherwise specified

Symbol Parameter Min Typ Max Units VCC Conditions
VIH Input HIGH Voltage 2.0 V Recognized as a HIGH Signal
VIL Input LOW Voltage 0.8 V Recognized as a LOW Signal
VCD Input Clamp Diode Voltage −1.2 V Min IIN = −18 mA
VOH Output HIGH 10% VCC 2.5 IOH = −1 mA
V Min
Voltage 5% VCC 2.7 IOH = −1 mA
VOL Output LOW
10% VCC 0.5 V Min IOL = 20 mA
Voltage
IIH Input HIGH
5.0 µA Max VIN = 2.7V
Current
IBVI Input HIGH Current
7.0 µA Max VIN = 7.0V
Breakdown Test
ICEX Output HIGH
50 µA Max VOUT = VCC
Leakage Current
VID Input Leakage IID = 1.9 µA
4.75 V 0.0
Test All Other Pins Grounded
IOD Output Leakage VIOD = 150 mV
3.75 µA 0.0
Circuit Current All Other Pins Grounded
IIL Input LOW Current −0.6 VIN = 0.5V (S0 – S2)
−2.4 mA Max VIN = 0.5V (A0 – A3, B0 – B 3)
−3.0 VIN = 0.5V (Cn)
IOS Output Short-Circuit Current −60 −150 mA Max VOUT = 0V
ICC Power Supply Current 54 81 mA Max

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74F382
AC Electrical Characteristics
TA = +25°C TA = 0°C to +70°C
VCC = +5.0V VCC = +5.0V
Symbol Parameter Units
CL = 50 pF CL = 50 pF
Min Typ Max Min Max
tPLH Propagation Delay 3.0 8.1 12.0 3.0 13.0
ns
tPHL Cn to Fi 2.5 5.7 8.0 2.5 9.0
tPLH Propagation Delay 4.0 10.4 15.0 3.5 17.0
ns
tPHL Any A or B to Any F 3.0 8.2 11.0 2.5 12.0
tPLH Propagation Delay 6.5 11.0 20.5 5.5 21.5
ns
tPHL Si to Fi 4.0 8.2 15.0 4.0 17.5
tPLH Propagation Delay 3.5 6.0 8.5 3.5 11.0
ns
tPHL Ai or Bi to Cn + 4 3.5 6.5 9.0 3.5 10.5
tPLH Propagation Delay 7.0 12.5 16.5 7.0 17.5
ns
tPHL Si to OVR or Cn + 4 5.0 9.0 12.0 5.0 14.5
tPLH Propagation Delay 2.5 5.6 8.0 2.0 9.0
ns
tPHL Cn to Cn + 4 3.5 6.3 9.0 2.0 10.0
tPLH Propagation Delay 3.5 8.0 11.0 3.5 13.0
ns
tPHL Cn to OVR 2.5 7.1 10.0 2.5 11.0
tPLH Propagation Delay 7.0 11.5 15.5 7.0 16.5
ns
tPHL Ai or Bi to OVR 3.0 8.0 10.5 3.0 11.5

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 74F382
Physical Dimensions inches (millimeters) unless otherwise noted

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M20B

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74F382
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D

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 74F382 4-Bit Arithmetic Logic Unit
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Package Number N20A

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Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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