INTRODUCTION TO 8085 PROGRAMMING MODEL

1. THE 8085 PROGRAMMING MODEL

The 8085 programming model includes six registers, one accumulator, and one flag register,
Figure. In addition, it has two 16-bit registers: the stack pointer and the program counter. They are
described briefly as follows

ACCUMULATOR (8) FLAG (8)

B (8) C (8)

D (8) E (8)

H (8) L (8)

Stack Pointer (16)

Program Counter (16)

8-lines bidirectional data bus 16-bit unidirectional address bus

Figure 2.1: 8085 Programming Model

Registers

The 8085 has six general-purpose registers to store 8-bit data; these are identified as
B,C,D,E,H, and L as shown in the figure. They can be combined as register pairs - BC, DE, and
HL - to perform some 16-bit operations. The programmer can use these registers to store or copy
data into the registers by using data copy instructions.

Accumulator

The accumulator is an 8-bit register that is a part of arithmetic/logic unit (ALU). This register
is used to store 8-bit data and to perform arithmetic and logical operations. The result of an
operation is stored in the accumulator. The accumulator is also identified as register A.
Flags

The ALU includes five flip-flops, which are set or reset after an operation according to data
conditions of the result in the accumulator and other registers. They are called Zero (Z), Carry
(CY), Sign (S), Parity (P), and Auxiliary Carry (AC) flags; their bit positions in the flag register
are shown in the Figure below. The most commonly used flags are Zero, Carry, and Sign. The
microprocessor uses these flags to test data conditions.

B7 B6 B5 B4 B3 B2 B1 B0
S Z AC P CY

Figure 2.1: 8085 Flag Register

For example, after an addition of two numbers, if the sum in the accumulator id larger than eight
bits, the flip-flop uses to indicate a carry − called the Carry flag (CY) − is set to one. When an
arithmetic operation results in zero, the flip-flop called the Zero (Z) flag is set to one. The first
Figure shows an 8-bit register, called the flag register, adjacent to the accumulator. However, it is
not used as a register; five bit positions out of eight are used to store the outputs of the five flip-
flops. The flags are stored in the 8-bit register so that the programmer can examine these flags
(data conditions) by accessing the register through an instruction.

These flags have critical importance in the decision-making process of the microprocessor. The
conditions (set or reset) of the flags are tested through the software instructions. For example, the
instruction JC (Jump on Carry) is implemented to change the sequence of a program when CY
flag is set. The thorough understanding of flag is essential in writing assembly language
programs.

Sign Flag (S) – After any operation if the MSB (B(7)) of the result is 1, it in indicates the number
is negative and the sign flag becomes set, i.e. 1. If the MSB is 0, it indicates the number is positive
and the sign flag becomes reset i.e. 0.

from 00H to 7F, sign flag is 0

from 80H to FF, sign flag is 1

1- MSB is 1 (negative)
0- MSB is 0 (positive)

Example:

MVI A 30 (load 30H in register A)

MVI B 40 (load 40H in register B)
SUB B (A = A – B)

These set of instructions will set the sign flag to 1 as 30 – 40 is a negative number.
1. MVI A 40 (load 40H in register A)
MVI B 30 (load 30H in register B)
SUB B (A = A – B)

These set of instructions will reset the sign flag to 0 as 40 – 30 is a negative number.

2. Zero Flag (Z) – After any arithmetical or logical operation if the result is 0 (00)H, the
zero flag becomes set i.e. 1, otherwise it becomes reset i.e. 0.

00H zero flag is 1.

from 01H to FFH zero flag is 0

1- zero result
0- non-zero result

Example:

MVI A 10 (load 10H in register A)

SUB A (A = A – A)

These set of instructions will set the zero flag to 1 as 10H – 10H is 00H

3. Auxiliary Cary Flag (AC) – This flag is used in BCD number system (0-9). If after any
arithmetic or logical operation D(3) generates any carry and passes on to B(4) this flag
becomes set i.e. 1, otherwise it becomes reset i.e. 0. This is the only flag register which is not
accessible by the programmer

1-carry out from bit 3 on addition or borrow into bit 3 on subtraction

0-otherwise

Example:

MOV A 2B (load 2BH in register A)

MOV B 39 (load 39H in register B)
ADD B (A = A + B)

These set of instructions will set the auxiliary carry flag to 1, as on adding 2B and 39,
addition of lower order nibbles B and 9 will generate a carry.

4. Parity Flag (P) – If after any arithmetic or logical operation the result has even parity, an
even number of 1 bits, the parity register becomes set i.e. 1, otherwise it becomes reset i.e. 0.

1-accumulator has even number of 1 bits

0-accumulator has odd parity
 Example:

MVI A 05 (load 05H in register A)

This instruction will set the parity flag to 1 as the BCD code of 05H is 00000101, which
contains even number of ones i.e. 2.

5. Carry Flag (CY) – Carry is generated when performing n bit operations and the result is
more than n bits, then this flag becomes set i.e. 1, otherwise it becomes reset i.e. 0.
During subtraction (A-B), if A>B it becomes reset and if (A<B) it becomes set.
Carry flag is also called borrow flag.

1-carry out from MSB bit on addition or borrow into MSB bit on subtraction
0-no carry out or borrow into MSB bit

Example:

MVI A 30 (load 30H in register A)

MVI B 40 (load 40H in register B)
SUB B (A = A – B)

These set of instructions will set the carry flag to 1 as 30 – 40 generates a carry/borrow.

MVI A 40 (load 40H in register A)

MVI B 30 (load 30H in register B)
SUB B (A = A – B)

These set of instructions will reset the sign flag to 0 as 40 – 30 does not generate any
carry/borrow.

Program Counter (PC)

This 16-bit register deals with sequencing the execution of instructions. This register is a memory
pointer. Memory locations have 16-bit addresses, and that is why this is a 16-bit register.
The microprocessor uses this register to sequence the execution of the instructions. The function
of the program counter is to point to the memory address from which the next byte is to be
fetched. When a byte (machine code) is being fetched, the program counter is incremented by one
to point to the next memory location.

Stack Pointer (SP)

The stack pointer is also a 16-bit register used as a memory pointer. It points to a memory location
in R/W memory, called the stack. The beginning of the stack is defined by loading 16-bit address
in the stack pointer.

This programming model will be used in subsequent tutorials to examine how these registers are
affected after the execution of an instruction.
ADDRESSING MODES IN 8085

2. ADDRESSING MODES IN 8085

These are the instructions used to transfer the data from one register to another register, from
the memory to the register, and from the register to the memory without any alteration in the
content. Addressing modes in 8085 is classified into 5 groups −

Immediate addressing mode

In this mode, the 8/16-bit data is specified in the instruction itself as one of its operand.
For example: MVI C, 20F: means 20F is copied into register C.

Register addressing mode

In this mode, the data is copied from one register to another.

For example: MOV D, B: means data in register B is copied to register D.

Direct addressing mode

In this mode, the data is directly copied from the given address to the register.
For example: LDA 5000: means the data at address 5000 is copied to register A.

Indirect addressing mode

In this mode, the data is transferred from one register to another by using the address pointed by
the register.
For example: LDAX B: means data is transferred from the memory address pointed by the
register pair BC to the register A.

Implied addressing mode

This mode doesn’t require any operand; the data is specified by the opcode itself.
For example: CMA.
INSTRUCTION SET (DATA TRANSFER INSTRUCTION)

3. THE 8085 INSTRUCTIONS:

The 8085 instructions can be classified into the following five functional categories: data transfer
(copy) operations, arithmetic operations, logical operations, branching operations and machine-
control operations.

3.1. DATA TRANSFER (COPY) INSTRUCTION

This group of instructions copies data for a location (register or I/O or memory) called the source,
to another location (register or I/O or memory) called the destination. The contents of the source
are not changed. In the8085 processor, data transfer instructions do not affect the flags.
The instructions used to copy are:

1. MOV
2. MVI
3. LXI
4. LDA
5. STA
6. LDAX
7. STAX
8. LHLD
9. SHLD
10. XCHG
11. IN
12. OUT

1. MOV: Move - Copy from Source to Destination

Opcode Operand Bytes Register Transfer Logic

MOV Rd, Rs 1 (Rd) ← (Rs)
MOV M, Rs 1 ((H)(L)) ← (Rs)
MOV Rd, M 1 (Rd) ← ((H)(L))

Description: This instruction copies the contents of the source register into the destination
register, the content of the source register are not altered. If one of the operands is a memory
location, it is specified by the contents of HL registers.
Flags: No flags are affected
Example 1:

Let us assume register B contains 72H and register C contains 9F. We move the contents of
register C to register B.

Instruction: MOV B, C

It can be noted that the first operand B specifies the destination and the second operand C
specifies the source.

Register contents before instruction

B 72 9F C

Register contents before instruction

B 9F 9F C

Example 2:

Let us assume register B contains 72H and registers H and L are 90 and 50, respectively. Memory
location 9050 contains 9F. We transfer the content of the memory location 9050 to register B.

Instruction: MOV B, M

Contents before instruction

B C
72 XX
D E
H L

9050 9F

Contents after instruction

B C
9F XX
D E
H L

9050 9F
 2. MVI: Move Immediate 8-bit

Opcode Operand Bytes Register Transfer Logic

MVI Rd, <data> 2 (Rd) ← <data>
MVI M, <data> 2 ((H)(L)) ← <data>

Description: The 8-bit data are stored in the destination register or memory. If the operand is a
memory location, it is specified by the contents of HL registers.

Flags: No flags are affected

Example 1:

Let us load 92 in register B

Instruction: MVI B, 92

This instruction loads 92 in register B.

Example 2:

Let us assume that registers H and L contain 90 and 50, respectively. We want to load 3A in
memory location 9050.

Instruction: MVI M, 3A

Contents before instruction

H 90 50 L

9050 XX

Contents after instruction

H 90 50 L

9050 3A
 3. LXI: Load Register pair Immediate

Opcode Operand Bytes Register Transfer Logic

LXI Reg. Pair, <16-bit data> 3 (Rl) ← Bytel
(Rh) ← Byteh

Description: The instruction loads 16-bit data in the register pair designated in the operand. This
is a 3-byte instruction; the second byte specifies the low-order byte and the third byte specifies the
high-order byte.

Flags: No flags are affected

Example:

We want to load the 16-bit data 9050 in register pair BC.

Instruction: LXI B, 9050

This instruction loads 50 in register C and 90 in register B.

[Comments: We can note the reverse order in entering the code of 16-bit data. This is the only
instruction that can directly load a 16-bit address in the stack pointer register.]
 4. LDA: Load Accumulator Direct

Opcode Operand Bytes Register Transfer Logic

LDA <16-bit address> 3 (A) ← (<16-bit address>)

Description: The contents of a memory location, specified by a 16-bit address in the operand, are
copied to the accumulator. The contents of the source are not altered. This is a 3-byte instruction;
the second byte specifies the low-order address and the third byte specifies the high-order address.

Flags: No flags are affected

Example:

Let us assume memory location 9050 contains byte 25. We want to load the accumulator with the
contents of location 9050.

Instruction: LDA 9050

Contents before instruction

A XX XX F

9050 25

Contents after instruction

A 25 XX F

9050 25
 5. STA: Store Accumulator Direct

Opcode Operand Bytes Register Transfer Logic

STA <16-bit address> 3 < (16-bit address) > ← (A)

Description: The contents of the accumulator are copied to a memory location specified the
operand, are copied to a memory location specified by the operand. This is a 3-byte instruction;
the second byte specifies the low-order address and the third byte specifies the high-order address.

Flags: No flags are affected

Example:

Let the accumulator contains byte 9F. We want to store the accumulator content into memory
location 9050.

Instruction: STA 9050

Contents before instruction

A 9F XX F

9050 XX

Contents after instruction

A 9F XX F

9050 9F
 6. LDAX: Load Accumulator Indirect

Opcode Operand Bytes Register Transfer Logic

LDAX B/D Reg. pair 1 (A) ← ((Rh)(Rl))

Description: The contents of the designated register pair point to a memory location. This
instruction copies the content of that memory location into the accumulator. The contents of either
the register pair or the memory location are not altered.

Flags: No flags are affected

Example :

Let us assume the contents of register B = 90, C = 50, and memory location 9050 = 9F. We want
to transfer the contents of the memory location 9050 to the accumulator.

Instruction: LDAX B

Contents before instruction

A XX XX F

B 90 50 C
V

9050 9F

Contents after instruction

A 9F XX F

B 90 50 C
V

9050 9F
 7. STAX: Store Accumulator Indirect

Opcode Operand Bytes Register Transfer Logic

STAX B/D Reg. pair 1 ((Rh)(Rl)) ← (A)

Description: The contents of the accumulator are copied into the memory location specified by the
contents of the operand (register pair). The contents of the accumulator are not altered.

Flags: No flags are affected

Example:

Let us assume the contents of accumulator are F9 and the contents of B and C are 90 and 50
respectively. We want to store the accumulator contents in memory location 9050

Instruction: STAX B

Contents before instruction

A F9 XX F

B 90 50 C
V

9050 XX

Contents after instruction

A F9 XX F

B 90 50 C
V

9050 F9

[Comments: This instruction performs the same function as MOV M, A except this instruction
uses the contents of BC or DE as memory pointers.]
 8. LHLD: Load H and L Registers Direct

Opcode Operand Bytes Register Transfer Logic

LHLD 16-bit address 3 (L) ← (<address>)
(H) ← (<address>+1)

Description: The instruction copies the contents of the memory location pointed out by the 16-bit
address in register L and copies the contents of the next memory location.

Flags: No flags are affected

Example :

Let us assume memory location 9050 contains 85 and 9051 contains 01. Transfer of memory
contents to register HL is to be performed.

Instruction: LHLD 9050

Contents before instruction

H XX XX L

9050 85

9051 01

Contents after instruction

H 01 85 L

9050 85

9051 01
 9. SHLD: Store H and L Registers Direct

Opcode Operand Bytes Register Transfer Logic

SHLD 16-bit address 3 (<address>) ← (L)
(<address>+1) ← (H)

Description: The contents of register L are stored in the memory location specified by the 16-bit
address in the operand, and the contents of register H are stored in the next memory location by
incrementing the operand. The contents of register HL are not altered. This is a 3-byte
instruction; the second byte specifies the low-order address and the third byte specifies the high-
order address.

Flags: No flags are affected

Example :

Let us assume that the H and L registers contain 01 and FF respectively. We want to store the
contents at memory locations 9050 and 9051.

Instruction: SHLD 9050

Contents before instruction

H 01 FF L

9050 XX

9051 XX

Contents after instruction

H 01 FF L

9050 FF

9051 01
 10. XCHG: Exchange H and L with D and E

Opcode Operand Bytes Register Transfer Logic

XCHG - 1 (H) ↔ (D)
(L) ↔ (E)

Description: The contents of register H are exchanged with the contents of register D, and the
contents of register L are exchanged with the contents of register E.

Flags: No flags are affected

Example:

Let us assume that registers H and L contains the data bytes 98 and A4, respectively. Again, let us
assume that registers D and E contains the data bytes C7 and 05, respectively.

Instruction: XCHG

Contents before instruction

H 98 A4 L

D C7 05 E

Contents after instruction

H C7 05 L

D 98 A4 E
 11. IN: Input Data to Accumulator from a Port with 8-bit Address

Opcode Operand Bytes Register Transfer Logic

IN <8-bit port address> 2 (A) ← (<port address>)

Description: The contents of the input port designated in the operand are read and loaded into the
accumulator.

Flags: No flags are affected

[Comments: The operand is an 8-bit address; therefore, port addresses can range from 00 to FF.
While executing the instruction, a port address is duplicated on low-order (A7-A0) and high-order
(A15-A8) address buses. Any one of the sets of address lines can be decoded to enable the input
port.]

12. OUT: Output Data from Accumulator to a Port with 8-bit Address

Opcode Operand Bytes Register Transfer Logic

OUT <8-bit port address> 2 (<port address>) ← (A)

Description: The contents of the accumulator are copied into the output port specified by the
operand.

Flags: No flags are affected

[Comments: The operand is an 8-bit address; therefore, port addresses can range from 00 to FF.
While executing the instruction, a port address is duplicated on low-order (A7-A0) and high-order
(A15-A8) address buses. Any one of the sets of address lines can be decoded to enable the output
port.]
INSTRUCTION SET (ARITHMETIC INSTRUCTION)

1.2. ARITHMETIC INSTRUCTION:

The 8085 performs various arithmetic operations, such as addition, subtraction,

increment and decrement. Arithmetic instructions perform these operations.
The instructions used to perform arithmetic operations are
1. ADD
2. ADI
3. ACI
4. ADC
5. SUB
6. SUI
7. SBB
8. SBI
9. INR
10. DCR
11. INX
12. DCX
13. DAD
14. DAA

1. ADD: Add Register to Accumulator

Opcode Operand Bytes Register Transfer Logic

ADD R 1 (A) ← (A) + (R)
ADD M 1 (A) ← (A) + ((H)(L))

Description: The contents of the operand (register or memory) are added to the contents of the
accumulator and the result is stored in the accumulator. If the operand is a memory location, that
is indicated by the 16-bit address in the HL register

Flags: All flags are modified to reflect the result of the addition.

2. ADI: Add Immediate to Accumulator

Opcode Operand Bytes Register Transfer Logic

ADI 8-bit data 2 (A) ← (A) + <data>

Description: The 8-bit data are added to the contents of the accumulator and the result is stored in
the accumulator.

Flags: All flags are modified to reflect the result of the addition.
 3. ACI: Add Immediate to Accumulator with carry

Opcode Operand Bytes Register Transfer Logic

ACI 8-bit data 2 (A) ← (A) + CY + <data>

Description: The 8-bit data (operand) and the carry flag are added to the contents of the
accumulator, and the result is stored in the accumulator.

Flags: All flags are modified to reflect the result of the addition.

[Comments: This instruction is commonly used in 16-bit addition]

4. ADC: Add Register to Accumulator with carry

Opcode Operand Bytes Register Transfer Logic

ADC R 1 (A) ← (A) + (R) + CY
ADC M 1 (A) ← (A) + ((H)(L) + CY

Description: The contents of the operand (register or memory) and the carry flag are added to the
contents of the accumulator and the result is placed in the accumulator. The contents of the
operand are not altered, however, the previous carry flag is reset.

Flags: All flags are modified to reflect the result of the addition.

Example :

Let us assume that register pair BC contains 2498 and register pair de contains 54A1. We add
these 16-bit numbers and save the result in BC registers.

The steps in adding 16-bit numbers are as follows:

1. We add the contents of registers C and E by placing the contents of one register in
the accumulator. This addition generates a carry. We use instruction ADD and save the
low-order 8-bits in register C.

98 = 10011000
A1 = 10100001

1 39 = 1 00111001
 2. We add the contents of registers B and D by placing the contents of one register in
the accumulator. We use instruction ADC.

The result will be as follows:

24 = 00100100
54 = 01010100
1 1 (Carry from previous addition)

79 = 01111001 (We store in register B)

[Comments: This instruction is commonly used in 16-bit addition]

5. SUB: Subtract Register or Memory from Accumulator

Opcode Operand Bytes Register Transfer Logic

SUB R 1 (A) ← (A) − (R)
SUB M 1 (A) ← (A) − ((H)(L))

Description: The contents of the register or the memory location specified by the operand are
subtracted from the contents of the accumulator and the results are placed in the accumulator. The
contents of the source are not altered.

Flags: All flags are modified to reflect the result of the subtraction.

Example 1:

Let us assume that the contents of the accumulator are 37 and the contents of the
register C are 40. We subtract the contents of register C from the accumulator.

Instruction: SUB C

(C) : 40 = 01000000
2’s complement of (C) = 11000000

(A) : 37 = 00110111

0/11110111 = F7

Complement carry: 1/11110111

Flags: S=1, Z=0, AC=0, P=0, CY=1

The result, as a negative number, will be in 2’s complement and thus the Carry (Borrow) flag
is set.
Example 2:

Let us assume that the contents of the accumulator are 40 and the contents of the
register C are 37. We subtract the contents of register C from the accumulator.

Instruction: SUB C

(C) : 37 = 00110111
2’s complement of (C) = 11001001

(A): 40 = 01000000

0/00001001

Complement carry: 0/00001001 = 09

Flags: S=0, Z=0, AC=0, P=1, CY=0

6. SUI: Subtract Immediate from Accumulator

Opcode Operand Bytes Register Transfer Logic

SUI <8-bit data> 2 (A) ← (A) − <data>

Description: The 8-bit data are subtracted from the contents of the accumulator and the results are
placed in the accumulator.

Flags: All flags are modified to reflect the result of the subtraction.

7. SBB: Subtract Source and Borrow from Accumulator

Opcode Operand Bytes Register Transfer Logic

SBB R 1 (A) ← (A) − (R) − B
SBB M 1 (A) ← (A) − ((H)(L)) − B

Description: The contents of the operand (register or memory) and the Borrow flag are subtracted
from the contents of the accumulator and the results are placed in the accumulator.

Flags: All flags are modified to reflect the result of the subtraction.
 8. SBI: Subtract Immediate with Borrow

Opcode Operand Bytes Register Transfer Logic

SBI <>8-bit data 2 (A) ← (A) − <data> − B

Description: The 8-bit data (operand) and the borrow are subtracted from the contents of the
accumulator, and the results are placed in the accumulator.

Flags: All flags are modified to reflect the result of the operation.

9. INR: Increment Contents of Register/Memory by 1

Opcode Operand Bytes Register Transfer Logic

INR R 1 (R) ← (R) + 1
INR M 1 ((H)(L)) ← ((H)(L)) + 1

Description: The contents of the designated register / memory are incremented by 1 and the
results are stored in the same place. If the operand is a memory location, it is specified by the
contents of HL register pair.

Flags: All flags except CY are modified to reflect the result of the operation.

Example 1:

Register D contains FF. we shall specify the contents of the register after the
increment.

Instruction: INR D

(D) : FF = 11111111
+1 = 00000001

0/00000000 = 00

After the execution of the INR instruction, register D will contain 00; however, carry flag is not
modified.
Example 2:

We assume that the HL register contains 9075. We shall increment the contenmts
of memory location 9075, which presently holds 7F.

Instruction: INR M

Contents before instruction

H 90 75 L 9075 7F

Contents after instruction

H 90 75 L 9075 80

10. DCR: Decrement Contents of Register/Memory by 1

Opcode Operand Bytes Register Transfer Logic

DCR R 1 (R) ← (R) − 1
DCR M 1 ((H)(L)) ← ((H)(L)) − 1

Description: The contents of the designated register / memory are decremented by 1 and the
results are stored in the same place. If the operand is a memory location, it is specified by the
contents of HL register pair.

Flags: All flags except CY are modified to reflect the result of the operation.

Example :

Register B contains 00. we shall specify the contents of the register after the
decrement.

Instruction: DCR B

+1 = 00000001
2’s complement of 1’s = 11111111

(B) : 00 = 00000000

11111111 = FF

After the execution of the DCR instruction, register B will contain FF; however, carry flag is not
modified.
 11. INX: Increment Register Pair by 1

Opcode Operand Bytes Register Transfer Logic

INX Reg. pair 1 (Reg. pair) ← (Reg. pair) + 1

Description: The contents of the designated register pair are incremented by 1. The instruction
views the contents of the two registers as a 16-bit number.

Flags: No flags are affected.

Example :

Register pair HL contains 9FFF. We shall specify the contents of the entire
register if it is incremented by 1.

Instruction: INX H

After adding 1 to the contents of the HL pair the answer is (H) = A0 , (L) = 00

Contents before instruction

H 9F FF L

Contents after instruction

H A0 00 L
 12. DCX: Decrement Register Pair by 1

Opcode Operand Bytes Register Transfer Logic

DCX Reg. pair 1 (Reg. pair) (Reg. pair) −1

Description: The contents of the designated register pair are decremented by 1. The instruction
views the contents of the two registers as a 16-bit number.

Flags: No flags are affected.

Example :

Register pair DE contains 2000. We shall specify the contents of the entire register
if it is decremented by 1.

Instruction: DCX D

After adding 1 to the contents of the HL pair the answer is (D) = 1F , (E) = FF

Contents before instruction

D 20 00 E

Contents after instruction

D 1F FF E

13. DAD: Add Register Pair to H and l register pair

Opcode Operand Bytes Register Transfer Logic

DAD Reg. pair 1 (HL) ← (Reg. pair) + (HL)

Description: The 16-bit contents of the designated register pair are added to the contents of the
HL register and the sum is saved in the HL register. The contents of the source register pair are
not altered.

Flags: If the result is larger than 16 bits the CY flag is set. No other flags are affected
Example 1:

We assume that the register pair HL contains 0242. We want to multiply the
contents by 2

Instruction: DAD H

Contents before instruction

H 02 42 L

DAD operation

0242
+ 0242
0484

Contents after instruction

H 04 84 L

Example 2:

We assume that the register pair HL is cleared. We want to transfer the content of
Stack Pointer (SP) register that points to memory location FFFE to the HL register pair

Instruction: DAD SP

Contents before instruction

H 00 00 L SP FFFE
`

DAD operation

0000
+ FFFE
FFFE

Contents after instruction

H FF FE L SP FFFE
 14. DAA: Decimal-Adjust Accumulator

Opcode Operand Bytes Register Transfer Logic

DAA - 1

Description: The contents of the Accumulator are changed from a binary value to two binary-
coded decimal (BCD) digits. This is the only instruction that uses the auxiliary flag (internally) to
perform the binary-to-BCD conversion.

Flags: All flags are modified to reflect the result of the operation.
INSTRUCTION SET (LOGICAL INSTRUCTION)
1.3. LOGICAL INSTRUCTION:

Logical Instructions:

These instructions perform various logical operations with the contents of the
accumulator.
These instructions include:

1. ANA
2. ANI
3. ORA
4. ORI
5. XRA
6. XRI
7. CMA
8. CMP
9. CPI
10. RLC
11. RAL
12. RRC
13. RAR
14. STC
15. CMC

1. ANA: Logical AND with Accumulator

Opcode Operand Bytes Register Transfer Logic

ANA R 1 (A) ← (A) AND (R)
ANA M 1 (A) ← (A) AND ((H)(L))

Description: The contents of the Accumulator are logically ANDed with the contents of the
operand (register or memory), and the result is placed in the accumulator. If the operand is a
memory location, its address is specified by the contents of HL registers.

Flags: S, Z, P are modified to reflect the result of the operation. CY is reset. AC is set.

2. ANI: AND Immediate with Accumulator

Opcode Operand Bytes Register Transfer Logic

ANI <8-bit data> 2 (A) ← (A) AND <data>

Description: The contents of the Accumulator are logically ANDed with the 8-bit data (operand)
and the result is placed in the accumulator.

Flags: S, Z, P are modified to reflect the result of the operation. CY is reset. AC is set.
 3. ORA: Logical OR with Accumulator

Opcode Operand Bytes Register Transfer Logic

ORA R 1 (A) ← (A) OR (R)
ORA M 1 (A) ← (A) OR ((H)(L))

Description: The contents of the Accumulator are logically ORed with the contents of the operand
(register or memory), and the result is placed in the accumulator. If the operand is a memory
location, its address is specified by the contents of HL registers.

Flags: S, Z, P are modified to reflect the result of the operation. CY and AC are reset.

4. ORI: OR Immediate with Accumulator

Opcode Operand Bytes Register Transfer Logic

ANI <8-bit data> 2 (A) ← (A) OR <data>

Description: The contents of the Accumulator are logically ORed with the 8-bit data (operand)
and the result is placed in the accumulator.

Flags: S, Z, P are modified to reflect the result of the operation. CY and AC are reset.

5. XRA: Logical XOR with Accumulator

Opcode Operand Bytes Register Transfer Logic

XRA R 1 (A) ← (A) XOR (R)
XRA M 1 (A) ← (A) XOR ((H)(L))

Description: The contents of the Accumulator are logically XORed with the contents of the
operand (register or memory), and the result is placed in the accumulator. If the operand is a
memory location, its address is specified by the contents of HL registers.

Flags: S, Z, P are modified to reflect the result of the operation. CY and AC are reset.

6. XRI: XOR Immediate with Accumulator

Opcode Operand Bytes Register Transfer Logic

ANI <8-bit data> 2 (A) ← (A) XOR <data>

Description: The contents of the Accumulator are logically XORed with the 8-bit data (operand)
and the result is placed in the accumulator.

Flags: S, Z, P are modified to reflect the result of the operation. CY and AC are reset.
 7. CMA: Complement Accumulator

Opcode Operand Bytes Register Transfer Logic

CMA - 1 (A) ← (A) ′

Description: The content of the Accumulator is complemented.

Flags: No flags are affected.

8. CMP: Compare with Accumulator

Opcode Operand Bytes

CMP R 1
CMP M 1

Description: The contents of the operand (register or memory) are compared with the contents of
the accumulator. Both contents are preserved and the comparison is shown by setting the flags as
follows:
If (A) < (R) / (M) Then CY = 1, Z = 0
If (A) = (R) / (M) Then CY = 0, Z = 1
If (A) > (R) / (M) Then CY = 0, Z = 0

The comparison of two bytes is performed by subtracting the contents of the operand from the
contents of the accumulator; however, neither contents are modified.

Flags: S, P, AC are also modified in addition to Z and CY to reflect the results of the operation.
(here, S, P, AC are also modified according to the results of the subtraction).

9. CPI: Compare Immediate with Accumulator

Opcode Operand Bytes

CPI <8-bit data> 2

Description: The data is compared with the contents of the accumulator. The values being
compared remain unchanged and the results of the comparison are indicated by setting the flags as
follows:
If (A) < data Then CY = 1, Z = 0
If (A) = data Then CY = 0, Z = 1
If (A) > data Then CY = 0, Z = 0

The comparison of two bytes is performed by subtracting the data byte from the contents of the
accumulator; however, neither are modified.

Flags: S, P, AC are also modified in addition to Z and CY to reflect the results of the operation.
(here, S, P, AC are also modified according to the results of the subtraction).
 10. RLC: Rotate Accumulator Left Without Carry

Opcode Operand Bytes

RLC - 1

Description: Each binary bit of the accumulator is rotated left by one position. Bit B 7 is placed in
the position of B0 as well as in the CY flag.

Before RLC Instruction:

CY B7 B6 B5 B4 B3 B2 B1 B0

Accumulator

After RLC Instruction:

B7 B6 B5 B4 B3 B2 B1 B0 B7

Accumulator

Flags: CY is modified in according to bit B7. S, Z, P, AC are not affected.

11. RAL: Rotate Accumulator Left with Carry

Opcode Operand Bytes

RAL - 1

Description: Each binary bit of the accumulator is rotated left by one position through the carry
flag. Bit B7 is placed in the CY flag and the CY flag is placed in the least significant position of
Accumulator.

Before RAL Instruction:

CY B7 B6 B5 B4 B3 B2 B1 B0

Accumulator

After RAL Instruction:

B7 B6 B5 B4 B3 B2 B1 B0 CY

Accumulator

Flags: CY is modified in according to bit B7. S, Z, P, AC are not affected.

 12. RRC: Rotate Accumulator Right Without Carry

Opcode Operand Bytes

RRC - 1

Description: Each binary bit of the accumulator is rotated right by one position. Bit B 0 is placed in
the position of B7 as well as in the CY flag.

Before RRC Instruction:

B7 B6 B5 B4 B3 B2 B1 B0 CY

Accumulator

After RRC Instruction:

B0 B7 B6 B5 B4 B3 B2 B1 B0

Accumulator

Flags: CY is modified in according to bit B0. S, Z, P, AC are not affected.

13. RAR: Rotate Accumulator Right with Carry

Opcode Operand Bytes

RAR - 1

Description: Each binary bit of the accumulator is rotated right by one position through the carry
flag. Bit B0 is placed in the CY flag and the bit in the CY flag is placed in the most significant
position of Accumulator.

Before RAR Instruction:

B7 B6 B5 B4 B3 B2 B1 B0 CY

Accumulator

After RAR Instruction:

CY B7 B6 B5 B4 B3 B2 B1 B0

Accumulator

Flags: CY is modified in according to bit B0. S, Z, P, AC are not affected.

 14. STC: Set Carry

Opcode Operand Bytes Register Transfer Logic

STC - 1 CY ← 1

Description: The carry flag is set to 1.

Flags: CY is set to 1. S, Z, P, AC are not affected.

15. CMC: Complement Carry

Opcode Operand Bytes Register Transfer Logic

STC - 1 CY ← CY′

Description: The carry flag is complemented.

Flags: CY is modified. S, Z, P, AC are not affected.

INSTRUCTION SET (BRANCH INSTRUCTION)

1.4. BRANCH INSTRUCTION:

BRANCH INSTRUCTIONS:

This group of instructions alters the sequence of program execution either conditionally or
unconditionally.
The branch instructions are classified in three categories:
A. Jump instructions
B. Call and Return instructions
C. Restart instructions

A. Jump instructions: The jump instructions specify the memory location explicitly. They are
3-byte instructions: one byte for the operation code, followed by a 16-bit memory address.
Jump instructions are classified into two categories: Unconditional Jump and Conditional
Jump.

A.1. Unconditional Jump: The 8085 instruction set includes one unconditional Jump
instruction. It is

1. JMP:

1. JMP: Jump Unconditionally

Opcode Operand Bytes Register Transfer Logic

JMP <16-bit address> 3 (PC) address

Description: The program sequence is transferred to the memory location specified by the 16-bit
address. This is a 3-byte instruction; the second byte specifies the low-order byte and the third
byte specifies the high-order byte.

Flags: No flags are affected.

Example: We write the instruction at location 9000 to transfer the program sequence to memory
location 9050.

Instruction:

JMP 9050

Memory Address Hex Code Instruction

9000 C3 JMP 9050

9001 50
9002 90

[Comments: The 16-bit address of the operand is entered in memory in reverse order, the low-
order byte first, followed by the high-order byte.]

A.2. Conditional Jump: Conditional Jump instructions allow the microprocessor to make
decisions based on certain conditions indicated by the flags. The conditional Jump instructions
check the flag conditions and make decisions to change or not to change the sequence of a
program. All conditional Jump instructions in the 8085 are 3-byte instructions; the second-byte
specifies the low-order memory address, and the third byte specifies the high-order memory
address. The following instructions transfer the program sequence to the memory location
specified under the given conditions:

1. JC
2. JNC
3. JZ
4. JNZ
5. JP
6. JM
7. JPE
8. JPO

Opcode Operand Bytes Description

JC <16-bit address> 3 Jump if Carry
JNC <16-bit address> 3 Jump if Not Carry
JZ <16-bit address> 3 Jump if Zero
JNZ <16-bit address> 3 Jump if Not Zero
JP <16-bit address> 3 Jump if Plus / Positive
JM <16-bit address> 3 Jump if Minus
JPE <16-bit address> 3 Jump if Parity Even
JPO <16-bit address> 3 Jump if Parity Odd

Table 2.1: Conditional Jump Instructions

Flags: No flags are affected.

 B. Call and Return instructions:

B.a. Call Instructions:

The Call instructions specify the memory location explicitly. They are 3-byte instructions: one
byte for the operation code, followed by a 16-bit memory address. Call instructions are classified
into two categories: Unconditional Call and Conditional Call.

B.a.1. Unconditional Call: The 8085 instruction set includes one unconditional Call
instruction. It is

1. CALL:

1. CALL: Call Unconditionally

Opcode Operand Bytes Register Transfer Logic

CALL <16-bit address> 3 SP ← SP − 1
M(SP) ← (PC)h
SP ← SP − 1
M(SP) ← (PC)l
(PC)l ← byte 2
(PC)h ← byte 3

Description: The program sequence is transferred to the memory location specified by the 16-bit
address. Before the transfer, the address of the next instruction to CALL (the contents of the
program counter) is pushed on the stack.

Flags: No flags are affected.

Example: We write CALL instruction at location 9010 to call a subroutine at 9150.

Instruction:

CALL 9150

Memory Address Hex Code Instruction

9010 CD CALL 9150

9011 50
9012 91
Execution of CALL:

The address of the program counter (9013) is placed on the stack

FFFD 13
FFFE 90
SP → FFFF

Call address (9150) is stored in the PC.

PC → 9150

[Comments: The CALL instruction should be accompanied by one of the return (RET or
conditional return) instructions in the subroutine]

B.a.2. Conditional Call: The Conditional Call instructions are based on four data conditions
(flags): CY, Z, S and P. The conditions are tested by checking the respective flags. In case of a
conditional Call instruction, the program is transferred to the subroutine if the condition is met;
otherwise, the main program is continued. The conditional Call instructions are listed below:
1. CC
2. CNC
3. CZ
4. CNZ
5. CP
6. CM
7. CPE
8. CPO

Opcode Operand Bytes Description

CC <16-bit address> 3 Call if Carry
CNC <16-bit address> 3 Call if Not Carry
CZ <16-bit address> 3 Call if Zero
CNZ <16-bit address> 3 Call if Not Zero
CP <16-bit address> 3 Call if Plus / Positive
CM <16-bit address> 3 Call if Minus
CPE <16-bit address> 3 Call if Parity Even
CPO <16-bit address> 3 Call if Parity Odd

Table 2.2: Conditional Call Instructions

Flags: No flags are affected.

 B.b. Return Instructions:

The Return instructions are used at the end of the subroutine to return to the calling program.
Return instructions can be classified into two categories: Unconditional return and Conditional
return

B.b.1. Unconditional Return: The 8085 instruction set includes one unconditional Return
instruction. It is

1. RET:

1. RET: Return Unconditionally

Opcode Operand Bytes Register Transfer Logic

RET − 1 (PC)l ← M(SP)
SP ← SP + 1
(PC)h ← M(SP)
SP ← SP + 1

Description: The program sequence is transferred from the subroutine to the calling program. The
two bytes from the top of the stack are copied into the program counter and the program execution
begins at the new address.

Flags: No flags are affected.

Example: Let us assume that the stack pointer is pointing to location FFFD. If we write the RET
instruction, then after execution, the effect will be as follows:

Instruction:

RET

Memory Address Hex Code Instruction

9010 CD CALL 9150

9011 50
9012 91
Execution of RET:

The address of the program counter (9013) is placed on the stack

FFFD 13
FFFE 90
SP → FFFF

Call address (9150) is stored in the PC.

PC → 90 13

[Comments: This instruction is used in conjunction with CALL or conditional call instructions.]

B.b.2. Conditional Return: The Conditional Return instructions are based on four data conditions
(flags): CY, Z, S and P. The conditions are tested by checking the respective flags. In case of a
conditional Return instruction, the program sequence returns to the calling program if the
condition is met; otherwise, the sequence in the subroutine is continued.. The conditional Call
instructions are listed below:

1. RC
2. RNC
3. RZ
4. RNZ
5. RP
6. RM
7. RPE
8. RPO

Opcode Operand Bytes Description

RC - 1 Return if Carry
RNC - 1 Return if Not Carry
RZ - 1 Return if Zero
RNZ - 1 Return if Not Zero
RP - 1 Return if Plus / Positive
RM - 1 Return if Minus
RPE - 1 Return if Parity Even
RPO - 1 Return if Parity Odd

Table 2.3: Conditional Return Instructions

Flags: No flags are affected.

 3. Restart (RST) instructions:

RST instructions are 1-byte call instructions that transfer the program execution to a specific
location on page 00. They are executed the same way as Call instructions. When an RST
instruction is executed, the 8085 stores the contents of the program counter (the address of the
next instruction) on the top of the stack and transfer the program to the Restart location.

There are 8 RST instructions as follows:

1. RST 0
2. RST 1
3. RST 2
4. RST 3
5. RST 4
6. RST 5
7. RST 6
8. RST 7

Opcode Operand Bytes Restart Address (in Hex)

RST0 - 1 0000
RST1 - 1 0008
RST2 - 1 0010
RST3 - 1 0018
RST4 - 1 0020
RST5 - 1 0028
RST6 - 1 0030
RST7 - 1 0038

Table 2.4: Restart Instructions

Flags: No flags are affected.

There is an additional branch instruction namely

PCHL

Opcode Operand Bytes Register Transfer Logic

PCHL - 1 (PC)h ← (H)
(PC)l ← (L)

Description: The contents of registers H and L are copied into the program counter. The contents
of H are placed as a high-order byte and of L as low-order byte.

Flags: No flags are affected.

INSTRUCTION SET (MACHINE CONTROL INSTRUCTION)

1.5. MACHINE CONTROL INSTRUCTIONS:

These instructions control machine functions such as Stack, Interrupt, Halt or do nothing.
These instructions include:

1. PUSH
2. POP
3. XTHL
4. SPHL

5. NOP
6. HLT

7. DI
8. EI
9. RIM
10. SIM
 1. PUSH: Push Register Pair Onto Stack

Opcode Operand Bytes Register Transfer Logic

PUSH Reg. Pair 1 SP ← SP − 1
M(SP) ← (R)h
SP ← SP − 1
M(SP) ← (R)l
PUSH PSW 1 SP ← SP − 1
M(SP) ← (A)
SP ← SP − 1
M(SP) ← (F)

Description: The contents of the register pair designated in the operand are copied into the
stack in the following sequence. The stack pointer register (SP register) is decremented and the
contents of high-order register are copied into the location. The SP register is decremented again
and the contents of the low-order register are copied to that location.

Example:

We assume that the SP registers points to location FFFF. Let register B contains 32 and
register C contains 57. We want to save the contents of the BC register pair on the stack.

Instruction:

PUSH B

Contents before instruction

32 57 FFFD XX
B C
FFFE XX

SP → FFFF

Contents after instruction

FFFD 57
B 32 57 C
FFFE 32

SP → FFFF

[Comments: Operand PSW (Program Status Word) represents the contents of the accumulator
and the flag register; the accumulator is the high-order register and the flags are the low-order
register].
 2. POP: Pop off Stack to Register Pair

Opcode Operand Bytes Register Transfer Logic

POP Reg. Pair 1 (R)l ← M(SP)
SP ← SP + 1
(R)h ← M(SP)
SP ← SP + 1
POP PSW 1 (A) ← M(SP)
SP ← SP + 1
(F) ← M(SP)
SP ← SP + 1

Description: The contents of the memory location pointed out by the stack pointer register
are copied to the low-order register of the operand. The stack pointer is incremented by 1 and
contents of that memory location are copied to the high-order register of the operand. The stack
pointer register is incremented by 1.

Example:
We assume that the SP registers points to location FFFD. Let FFFD contains 23 and
FFFE contains 5A. We want to save the contents of FFFD and FFFE to BC register pair.

Instruction:

POP B

Contents before instruction

XX XX FFFD 23
B C
FFFE 5A

SP → FFFF

Contents after instruction

5A 23 FFFD 23
B C
FFFE 5A

SP → FFFF

[Comments: Operand PSW (Program Status Word) represents the contents of the accumulator
and the flag register; the accumulator is the high-order register and the flags are the low-order
register].
 3. XTHL: Exchange contents of Top of Stack with H and L

Opcode Operand Bytes Register Transfer Logic

XTHL - 1 M(SP) ↔ (L)
M(SP+1) ↔ (H)

Description: This instruction exchanges the contents of the top two locations of the stack with
the contents of register pair HL.

4. SPHL: Copy H and L Registers to the Stack Pointer

Opcode Operand Bytes Register Transfer Logic

SPHL - 1 (SPh) ↔ (H)
(SPl) ↔ (L)

Description: The instruction loads the contents of H and L registers into the stack pointer
register: the contents of the H register provide the high-order address, and the contents of the L
register provide the low-order address. The contents of H and L register are not altered.

5. NOP: No Operation

Opcode Operand Bytes

NOP - 1

Description: No operation is performed. The instruction is fetched and decoded; however, no

operation is executed.

No flags are affected.

[Comments: The instruction is used to fill in time delays (1 M-cycle consisting of 4 T-states) or to
delete and insert instructions while troubleshooting]

6. HLT: Halt

Opcode Operand Bytes

HLT - 1

Description: The MPU finishes executing the current instruction and halts any further
execution. The MPU enters the Halt Acknowledge machine cycle and Wait states are inserted in
every clock period. (The MPU goes through 2 or more M-cycles i.e. 5 or more T-states). The
address and the data bus are placed in the high impedance state. The contents of the registers are
unaffected during the HLT state. An interrupt or reset is necessary to exit from the Halt state.