ARCHITECTURE OF 8085 MICROPROCESSOR (PIN DESCRIPTION)

1. ARCHITECTURE AND PIN DESCRIPTION OF 8085 MICROPROCESSOR

The 8085 is an 8-bit general purpose microprocessor capable of addressing 64K of memory. The
device has forty pins, requires a +5V single power supply, and can operate with a 3MHz single
phase clock.

Following Figure (Figure 1.1) shows the pin diagram of 8085 Microprocessor.

Figure 1.1

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 All the signals can be classified into six groups.

1. Address bus
2. Data bus
3. Control and status signals
4. Power supply and frequency signals
5. Externally initiated signals
6. Serial I/O ports.

Here details of individual pins are described.

Pin number:

1. X1 (Input)
2. X2 (Input)

An LC tuned circuit or an RC network or a crystal (X-tal) can generate clock pulses. In

8085 MPU, an X-tal is connected at these two pins (pin number 1 and 2). The clock generation
circuitry is built inside the unit. The frequency generated by X-tal in 8085 is 6 MHz. The output
pulse train got from crystal is not exact square pulse. So certain amount of wave-shaping is
required. The wave-shaping circuit may be Smitt-trigger circuit using OP_AMP. Smitt-trigger
circuit behaves like a flip-flop (divide by 2) circuit. Thus the frequency at which microprocessor
operates is half of the crystal frequency. Hence we can say 8085 operates with 3 MHz clock
frequency.

3. RESET OUT (Output)

The “Reset Out” pin gives a signal that indicates that the MPU is being reset. The same
signal can be used to reset (or acknowledge) the various other peripheral devices.

4. SOD (Output)
5. SID (Input)

The 8085 has two signals to implement the serial transmission: SOD (Serial Output Data)
and SID (Serial Input Data). In serial transmission, data bits are sent over a single line, one bit at
a time, such as transmission over telephone lines. The data on SID pin is loaded into
Accumulator bit B7 whenever a RIM instruction is executed. The output SOD is set or reset as
specified by the SIM instruction.

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 6. TRAP (Input)
7. RST7.5 (Input)
8. RST6.5 (Input)
9. RST5.5 (Input)
10. INTR (Input)
11. INTA′ (Output)

TRAP, RST7.5, RST6.5, RST5.5 and INTR are interrupt signals and INTA′ is active low
interrupt acknowledge signal.

We shall present a discussion about “Interrupt” later.

12. AD0 (Input / Output)

13. AD1 (Input / Output)
14. AD2 (Input / Output)
15. AD3 (Input / Output)
16. AD4 (Input / Output)
17. AD5 (Input / Output)
18. AD6 (Input / Output)
19. AD7 (Input / Output)

The signal lines AD7 - AD0 are bidirectional: they serve a dual purpose. They are used
as the low-order address bus as well as the data bus. In executing an instruction, during the
earlier part of the cycle, these lines are used as the low-order address bus. During the later part of
the cycle, these lines are used as the data bus. (This is also known as multiplexing the bus.)
Low-order address bus and data bus are mutually exclusive, i.e., these are not needed
simultaneously.

Pin Number:

20. GND

Pin number 20 is connected with Ground.

Pin Number:

21. A8 (Output)
22. A9 (Output)
23. A10 (Output)
24. A11 (Output)
25. A12 (Output)
26. A13 (Output)
27. A14 (Output)
28. A15 (Output)

The 8085 has these eight signal lines, A15 - A8, which are unidirectional and used as the high-
order address bus (the most significant 8 bits of the address bus).

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Pin Number:

29. S0 (Output)

S0 is status signal used to identify the nature of the operation.

Pin Number:

30. ALE (Output)

The ALE (Address Latch Enable) signal is used to demultiplex the low-order bus (the least
significant 8 bits of the address bus). Logic 1 on this pin indicates that the bits on AD7 - AD0 are
address bits. Logic 0 on this pin indicates that AD7-AD0 contain data.

Pin Number:

31. WR′ (Output)

32. RD′ (Output)

WR′ is a Write control signal (active low). This signal indicates the data on the data bus are
to be written into a selected memory or I/O location.

RD′ is a Read control signal (active low). This signal indicates that the selected I/O or
memory device is to be read and data are available on the data bus.

RD′ and WR′ are mutually exclusive signals. Both of them can be inactive at the same time
but both of them cannot be active at the same time.

Pin Number:

33. S1 (Output)

S1 is status signal used to identify the nature of the operation.

Pin Number:

34. IO / M′ (Output)

This is a status signal used to differentiate between I / O and memory operations. When it is
HIGH, it indicates an I/O operation; when it is LOW, it indicates a memory operation.

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Pin Number:

35. READY (Input)

The MPU checks the status of this pin after every machine cycle within a particular
instruction. If READY pin is found HIGH, then the MPU proceeds to the next instruction;
otherwise, it waits over there and starts checking the status of this READY pin after every clock
cycle till found HIGH.

The functions of READY pin are:

i. We can introduce some sort of wait cycles within instruction.
ii. The READY pin is used for matching and speed synchronization between MPU and
peripheral device(s). For example, we can synchronize a slower printer with a MPU.
Here, READY signal is used to delay the microprocessor read or write cycles until
the printer (a slow-responding peripheral) is ready to send or accept data.

Pin Number:

36. RESET IN′ (Input)

When the signal on pin 36 goes low then

i. The PC is set to zero

ii. The buses are tri-stated
iii. Flip-flops are cleared
iv. Registers are cleared
v. The MPU is reset

Pin Number:

37. CLK (Output)

The Clock Output signal is supplied to all peripheral devices. This will be 3 MHz for
8085.

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Pin Number:

38. HLDA (Output)

39. HLD (Input)

When HLD (Hold) signal is HIGH, MPU is reset and buses are not tri-stated. This signal
indicates that a peripheral such as a DMA controller is requesting the use of the address and data
buses, i.e. DMA transfer can be done when HLD is HIGH.
An acknowledge signal (HLDA) is needed to synchronize the MPU with DMA
controller. HLDA signal acknowledges the Hold request.

Pin Number:

40. Vcc

This is +5V power supply.

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INTERRUPTS IN 8085

2. INTERRUPTS IN 8085

The interrupt I/O is a process of data transfer whereby an external device or a peripheral can
inform the processor that is ready for communication and it requests attention. The process is
initiated by an external device and is asynchronous which means that it can be initiated at any
time without reference to the system clock. However, the response to an interrupt request is
directed and controlled by the microprocessor.

Interrupt – Hardware Interrupt and Software Interrupt:

Hardware Interrupts are interrupts which are non-deterministic, i.e., their time of occurrence
is unknown to us. Hardware interrupts may be generated due to power-off. [Examples: TRAP,
RST7.5, RST6.5, RST5.5and INTR].

Software interrupts are interrupts which are deterministic. RST instructions are commonly
used to set up software breakpoints. [Examples: RST0, RST1, RST2, RST3, RST4, RST5,
RST6, RST7].

Interrupt – Vectored Interrupt and Non-vectored Interrupt:

In case of vectored interrupt, the MPU knows which device is asking for interrupt, i.e.,
where to jump. The PC jumps to a specific predefined memory location. [Examples: TRAP,
RST7.5, RST6.5, RST5.5, RST0, RST1, RST2, RST3, RST4, RST5, RST6 and RST7].

In case of non-vectored interrupts, the MPU does not know where to jump. If a single
interrupt line is connected with a number of devices, then this type of interrupt takes place. In
this case, the MPU has to go in a procedure called Daisy Polling Chain, where the device near to
MPU gets priority. [Example: INTR].

Vectored Interrupts:

The 8085 instruction set includes eight RST (RESTART) instructions. These are 1-byte
call instructions that transfers the program execution to a specific location on page 00H., i.e.,
that compel the PC to jump to the memory location whose address is predefined, as listed in
following table [Table 1.1]:

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 Instructions Call Location (in Hex)
RST0 0000
RST1 0008
RST2 0010
RST3 0018
RST4 0020
RST5 0028
RST6 0030
RST7 0038

Table 1.1: Vectored Software Interrupts

Again, the 8085 has four hardware vectored interrupts. These are TRAP, RST7.5,
RST6.5 and RST5.5. These four are automatically vectored (transferred) to specific locations on
memory page 00H without any external hardware. The necessary hardware is already
implemented inside the 8085 MPU. These interrupts and their call locations are listed below
[Table 1.2]:

Interrupts Call Location (in Hex)

TRAP 0024
RST7.5 003C
RST6.5 0034
RST5.5 002C

Table 1.2: Vectored Hardware Interrupts

Now we can list all the vector interrupts and their corresponding call locations in a single
table. The table is listed below [Table 1.3]:

Instructions Call Location (in Hex)

RST0 0000
RST1 0008
RST2 0010
RST3 0018
RST4 0020
TRAP 0024
RST5 0028
RST5.5 002C
RST6 0030
RST6.5 0034
RST7 0038
RST7.5 003C

Table 1.3: Vectored Interrupts

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 If Interrupt Service Routine (ISR) is written in memory location whose address is
between two call locations of interrupts, then 8 bytes / 4 bytes are not sufficient for writing ISR.
Hence we can take help of jump instruction ‘JMP’. This jump instruction (3-byte instruction)
actually compels the PC to jump to the memory location whose address is given or specified, and
at that memory location full length ISR is written. These memory locations are usually ROM
locations.
We can take an example. Let the instruction “RST5” is written within a program. When the
processor encounters this instruction, the program is transferred to location 0028H. The ISR is
written somewhere else in memory (let between 2000 and 2100), and the jump instruction is
written at 0028 to specify the address (i.e., between 2000 and 21000 of the ISR.
[Between 2000 and 2100, some ISRs are loaded by the monitor program when the machine
gets loaded.]

Non- Vectored Interrupts:

Non-vectored interrupted are processed through a mechanism called Daisy Polling Chain.
In 8085, INTR is the only non-vectored interrupt and INTA′ is the interrupt acknowledge (active
low).

Interrupt – Maskable Interrupt and Non-maskable Interrupt:

The MPU can ignore or delay a certain interrupt at certain time when it is performing
some critical task. This is maskable interrupt. [Examples: RST7.5, RST6.5, RST5.5, RST0,
RST1, RST2, RST3, RST4, RST5, RST6, RST7, INTR].

The MPU has to respond a certain type of interrupt request immediately. This is non-
maskable interrupt. [Example: TRAP]

Interrupts based on Priority:

i. Vectored interrupt gets higher priority than non-vectored interrupts.

ii. As far as software interrupts are concerned, there is no priority because it is
known when the interrupts is going to take place.
iii. Hardware interrupts with higher number gets higher priority. But TRAP is
exceptional. TRAP has the highest priority
iv. Vectored interrupts with higher number gets higher priority. But TRAP is
exceptional. TRAP has the highest priority. For example, between RST7.5 and
RST7, the first one gets higher priority.

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INSTRUCTIONS ABOUT INTERRUPTS IN 8085

3. THE INSTRUCTIONS ABOUT INTERRUTPS

The 8085 interrupt process is controlled by the Interrupt Enable flip-flop, which is
internal to the processor and can be set or reset by using software instructions. If the flip-flop is
enabled and the input to the interrupt signal goes high, the microprocessor is interrupted.

The interrupt process should be enabled by writing the instruction EI in the main
program. The instruction EI sets the Interrupt Enable Flip-Flop. The instruction DI resets the FF
and disables the interrupt process.

Instruction

EI (Enable Interrupt)

 This is 1-byte instruction.

 The instruction sets the Interrupt Enable FF and enables the Interrupt process.
 System reset or an interrupt disables the interrupt disables the interrupt process.

Instruction

DI (Disable Interrupt)

 This is 1-byte instruction.

 The instruction resets the Interrupt Enable FF and disables the interrupt process.
 It should be included in a program segment where an interrupt from an outside source
cannot be tolerated.

The 8085 has five interrupt inputs (Figure). One is called INTR, three are called RST5.5,
RST6.5 and RST7.5, respectively, and the fifth is called TRAP, a non-maskable interrupt.

The TRAP has the highest priority, followed by RST7.5, RST6.5, RST5.5 and INTR, in
that order. [However, the TRAP has a lower priority than the Hold signal used for DMA].

TRAP is a non-maskable interrupt. It has the highest priority among the interrupt signals,
it need not be enabled and it cannot be disabled. It is level and edge-sensitive, meaning that the
input should go high and stay high to be acknowledged. It cannot be acknowledged again until it
makes a transition from high to low to high.

Figure 1.2 shows that when this interrupt is triggered, the program control is transferred
to location 0024 without any external hardware or the interrupt enable instruction EI. TRAP is
generally used for such critical events as power failure and emergency shut-off.

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 Input Pin Mask Location

RST7.5 D Q
003C
CLR mask

Reset
RST 7.5 Recognized

RST6.5
mask 0034

RST5.5
mask
002C

TRAP 0024

EI S Q

DI
RESET R
Any Interrupt Recognized CLR

Figure 1.2: Hardware for 8085 Vectored Interrupts

RST 7.5, RST6.5 and RST5.5

The maskable interrupts RST7.5, RST6.5 and RST5.5 (shown in Figure) are enabled
under program control with two instructions: EI (Enable Interrupt) described earlier and SIM
(Set Interrupt Mask) described below:

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 Instruction

SIM (Set Interrupt Mask)

 This is 1-byte instruction.

 The instruction can be used for three different functions
i) One function is to set mask for RST7.5, rst6.5 and rst5.5 interrupts. This
instruction reads the content of the accumulator and enables or disables the
interrupts according to the content of the accumulator. Bit B3 is control bit and
should be equal to 1 for bits B0, B1 and B2 to be effective. Logic 0 on B0, B1
and B2 will enable the corresponding interrupts and logic 1 will disable the
interrupts.
ii) The second function is to reset RST7.5 FF. Bit B4 is additional control for
RST7.5. If B4 is 1, RST7.5 is reset. This is used to override (or ignore) RST7.5
without servicing it.
iii) The third function is to implement serial I/O. Bits B7 and B6 of the accumulator
are used for serial I/O and do not affect the interrupts. Bit B6 = 1 enables the
serial I/O and bit B7 is used to transmit (output) bits.

7 B7 B6 B B5 B4 B3 B2 B1 B0
SOD SDE X R7.5 MSE M7.5 M6.5 M5.5

RST5.5 MASK 1 indicates

Masked/Disabled
RST6.5 MASK 0 indicates
Available/Unmasked
RST7.5 MASK /Enabled

Mask Set Enable (if 1, bits B0 to B2 will be effective)

RESET RST7.5: If 1, RST7.5 FF is reset OFF

Serial Data Enable (If 1, bit b7 is output to serial output data latch)

Serial Output Data (ignored if bit B6 is 0)

Figure 1.3: SIM INSTRUCTION FORMAT

Here we are concerned with RST7.5, RST6.5 and RST5.5 interrupts and not with serial I/O.

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How interrupt process is done in the 8085 is described below:

1. The interrupt process is enabled. The instruction EI sets the Interrupt Enable FF and one of
the inputs to the AND gates is set to logic 1. These AND gates activate the program
transfer to various vectored locations.
2. An appropriate bit pattern is loaded into the accumulator.
3. If bit B3 is 1, the respective interrupts are enabled according to bits B2- B0.
4. RST7.5, RST6.5 and RST5.5 interrupts are being monitored.
5. If bit B3 is 0, bits B2-B0 have no effect on previous conditions.
6. Bit B4 is 1. This resets RST7.5.

The entire interrupt process (except TRAP) is disabled by resetting the Interrupt Enable
FF. The FF can be reset in one of the following three ways:

 Instruction DI
 System Reset
 Recognition of an interrupt request
Figure shows that these three signals are ORed and the output of the OR gate is used to
reset the FF.

Triggering Levels:

These interrupts are sensitive to different types of triggering as listed below:

RST7.5: This is positive-edge sensitive and can be triggered with a short pulse. The request is
stored internally by the D flip-flop (Figure) until the microprocessor responds to the request or
until it is cleared by Reset or by bit B4 in the SIM instruction.

RST6.5 and RST5.5: these interrupts are level-sensitive, meaning that the triggering level
should be on until the microprocessor completes the execution of the current instruction. If the
microprocessor is unable to respond to these requests immediately, they shpuld be stored or held
by external hardware.

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 Pending Interrupts:

Because there are several interrupt lines, when one interrupt request is being served, other
interrupt request may occur and remain pending. The 8085 has an additional instruction called
RIM (Read Interrupt Mask) to sense these pending interrupts.

Instruction

RIM: Read Interrupt Mask

 This is 1-byte instruction.

 The instruction can be used for the following functions

i) To read interrupt masks. This instruction loads the accumulator with 8 bits
indicating the current status of the interrupt masks (Figure).
ii) To identify pending interrupts. Bit B4, B5 and B6 (Figure) identify the pending
interrupts.
iii) To receive serial data. Bit B7 (Figure) is used to receive serial data.

7 B7 B6 B5 B4 B3 B2 B1 B0
SID I7.5 I6.5 I5.5 IE M7.5 M6.5 M5.5

RST5.5 MASK 1 indicates

Masked/Disabled
RST6.5 MASK
0 indicates
Available/Unmaske
RST7.5 MASK d/Enabled

Interrupt Enable FF (1 enabled, 0 disabled)

RST 5.5 Pending Interrupt

1 indicates interrupt
RST 6.5 Pending Interrupt request pending

RST 7.5 Pending Interrupt 0 indicates interrupt

request is not pending
Serial Input Data bit, if any

Figure 1.4: RIM INSTRUCTION FORMAT

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ADDRESS / DATA BUS DEMULTIPLEXING

The 8085 uses a time multiplexed address-data bus. This is due to limited number of pins
on the 8085. Low-order 8-bits of the address appear on the AD bus during the first clock cycle
i.e., T1 state of a machine cycle. It then becomes the data bus during the second and third clock
cycles i.e., T2 and T3states.

ALE stands for address latch enable. It is used to distinguish whether the AD7 – AD0 bus
contains address bits A7 – A0 or data bits D7- D0. It is a single pulse issued during every T1 state
of the microprocessor

Since the lower 8-bits of the address information A7 to A0 is available at pin no.19 to pin no.12
only during T1 period, therefore, ALE pulse can be can be used to latch address A7 to A0 in an
external latch. ALE output is high during first half of the T1 period and its falling edge can be
used to latch the address bits A7 to A0 in an external latch e.g. 74LS373 register latch.

Fig.1.5a shows a schematic that uses a latch and the ALE signal to de multiplex the bus.
The bus AD7-AD0 is connected as the input to the latch 74LS373. The ALE signal is connected
to the enable (G) pin of the latch, and the output control (OC) signal of the latch is grounded.
When ALE goes high during the T1 state of a machine cycle, the latch is transparent and the
output of the latch changes according to the input. The CPU is putting lower-order bits of
address during this time. When the ALE goes LOW, the address bits get latched on the output
and remain so until the next ALE signal.

ALE

AD Bus AD7 A7
D Q

AD0 A0
D Q

Fig.1.5a: Latching of Lower Order Address in External Latch

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 Once saved in an external latch the lower order address A7 to A0 shall be available at the
output of the register latch for the subsequent states T2, T3, T4, T5 & T6, while pin no. 19 to pin
no.12 can then be utilized by the microprocessor for bi-directional operation. The falling edge of
the ALE can also be used to store status information being output by the 8085 during each
machine cycle. The ALE output is never tri-stated in the 8085. The manner of utilization of pins
19 to 12 is known as time multiplexed mode of operation.

The de-multiplexing of AD bus by latching lower byte of 16-bit address in external 8-bit
latch 74LS373 is shown in Fig.1.5b. Once the lower byte address is latched, the AD bus is
available for bi-directional data transfer. The 8-bit higher order address issued by microprocessor
in every T1 state along with latched lower byte address constitutes unidirectional 16-bit address
bus. The control signals put together constitutes bi-directional control bus, where some of the
signals are always input and some are always output. The three buses, address bus, data bus and
control bus together constitutes system bus.

8 16 Unidirectional
AD15- AD8 Address Bus
Intel A15-A0
8085 ALE G
8
74LS373 8
AD7- AD0 Latch
A7- A0
8
Bidirectional
D7- D0 Data Bus

Bidirectional Control Bus

Fig.1.5b: De-multiplexing of AD bus to Generate System Bus

The fact that ALE is required is a direct consequence of having a multiplexed data/address bus.
This is unlike the Intel 8080 microprocessor which is similar to the 8085 but where these buses
are not multiplexed. Some of the peripheral chips 8155/ 8156/ 8355/ 8755A have internal
multiplexing facility, therefore, ALE input pin of these peripheral chips is connected to ALE
output pin of the 8085, thus allowing a direct interface with the 8085. Thus IC chips internally
de-multiplex the AD bus using the ALE signal. Since a majority of peripheral devices do not
have the internal multiplexing facility, there is external hardware necessity for it.

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