Chapter 6: Memory

Management
 Background
Program must be brought (from disk) into memory
and placed within a process for it to be run
Main memory and registers are only storage, CPU can
access directly
Memory unit only sees a stream of:
addresses + read requests, or
address + data and write requests
Cache sits between main memory and CPU registers
Protection of memory is required to ensure correct
operation
 Protection
User processes must be restricted so that they only
access memory locations that "belong" to that
particular process.
We can provide this protection by using a pair of base
and limit registers define the logical address space of
a process.
The changing the contents of the base and limit
registers is a privileged activity, and it is allowed only
to the OS kernel.
Protection
 Protection
The base register holds the smallest legal physical
address and limit register specifies the size of the
range.
The process can legally access all addresses from
300040 to 420939 (inclusive)
Every memory access made by a user process is
checked against these two registers, and if a memory
access is attempted outside the valid range, then a
fatal error is generated.
The OS obviously has access to all existing memory
locations, as this is necessary to swap users' code
and data in and out of memory.
 Hardware Address Protection
CPU must check every memory access generated in
user mode to be sure it is between base and limit for
that user.
The instructions to loading the base and limit
registers are privileged.
Hardware Address Protection
 Address Binding
User programs typically refer to memory addresses
with symbolic names such as "i", "count", and
"average-Temperature".
These symbolic names must be mapped
or bound to physical memory addresses, which
typically occurs in several stages:
 Binding of Instructions and Data to Memory
Address binding of instructions and data to memory
addresses can happen at three different stages
Compile time: If memory location known a priori,
absolute code can be generated; must recompile
code if starting location changes
Load time: Must generate relocatable code if
memory location is not known at compile time.
Binding is delayed until load time.
Execution time: if the process can be moved
during its execution from one memory segment to
another, then binding delayed until run time
 Multistep
Processing
of a User
Program

• shows the various

stages of the
binding processes
and the units
involved in each
stage:
 Logical vs. Physical Address Space
Logical address – generated by the CPU; also
referred to as virtual address
Physical address – address seen by the memory
unit/hardware.
Addresses bound at compile time or load time have
identical logical and physical addresses.
Addresses created at execution time, however, have
different logical and physical addresses
Logical address space is the set of all logical
addresses generated by a program
Physical address space is the set of all physical
addresses corresponding to logical addresses.
 Memory-Management Unit (MMU)

The run time mapping from virtual/logical to physical

address is done by a hardware device called the
memory-management unit(MMU).
Base register now called relocation register.
The user program deals with logical addresses; it
never sees the real physical addresses.
Any memory references or manipulations are done
using purely logical addresses. Only when the
address sent to the physical memory chips then the
physical memory address generated.
Memory-Management Unit (MMU)
 Memory-Management Unit (Cont.)
The value in the relocation register is added to every
address generated by a user process at the time it is
sent to memory
Logical address bound to physical addresses
 Dynamic Loading
To obtain better memory-space utilization,
Rather than loading an entire program into memory
at once, dynamic loading loads up each routine as it
is called.
The advantage is that unused routines never be
loaded, reducing total memory usage and generating
faster program startup times.
All routines are kept on disk in a relocatable load
format.
The main program is loaded into memory and is
executed. Routines are loaded in to memory as they
are called.
 Dynamic Loading
When a routine needs to call another routine, the
calling routine first checks to see whether the other
routine has been loaded.
If it has not, the relocatable linking loader is called
to load the desired routine into memory. Then control
is passed to the newly loaded routine.
No special support from the operating system is
required
Implemented through program design
OS can help by providing libraries to implement
dynamic loading
 Dynamic Linking and Shared Libraries
Static linking – system libraries and program code
combined by the loader into the binary program
image and wasting both disk space and main memory
usage, because every program that included a certain
routine from the library would have their own copy of
that routine linked into their executable code.
With dynamic linking, only a stub is linked into the
executable module, containing references to the
actual library module linked in at run time.
Dynamic linking –linking postponed until execution
time
 Dynamic Linking and Shared Libraries
The code for some external routines is located and
loaded when the program is first run.
In dynamic linking, the names of the external libraries
/shared libraries are copied into the final executable.
The linking occurs at run time when the executable
file and libraries load to the memory.
The operating system performs dynamic linking.
 Dynamic Linking and Shared Libraries
Advantage of DLLs is that these libraries can be
shared among multiple processes, so that only one
instance/copy of the DLL is required in main memory.
Therefore, the size of the executable file is lower.
For this reason, DLLs are also known as shared
libraries, and are used extensively in Windows and
Linux systems.
It is possible to update and recompile the external
libraries. Moreover, if the shared library code is
already available in memory, there will be less load
time.
 Dynamic Linking and Shared Libraries
Small piece of code, stub, used to locate the
appropriate memory-resident library routine
Stub replaces itself with the address of the routine,
and executes the routine
Dynamic linking is particularly useful for libraries
Swapping
 Swapping
A process can be swapped temporarily out of
memory to a backing store and then brought back
into memory for continued execution.
If there is not enough memory available to keep all
running processes in memory at the same time,
then some processes who are not currently using
the CPU may have their memory swapped out to a
fast local disk called the backing store.
The swapping increases the degree of
multiprogramming in a system.
 Standard Swapping
Standard swapping involves moving entire
processes between main memory and a backing
store.
The backing store is commonly fast secondary
storage. It must be large enough to accommodate al
processes and it must provide direct access to these
memory images.
For a multithreaded process, all per-thread data
structures must be swapped as well.
 Standard Swapping
The operating system must also maintain metadata
for processes that have been swapped out, so they
can be restored when they are swapped back in to
memory.
The advantage of standard swapping is that the
system can accommodate more processes than
actual physical memory to store them.
The idle processes are good candidates for
swapping;
Most systems, including Linux and Windows, now
use a variation of swapping known as swapping with
paging.
 Contiguous Memory Allocation
Contiguous memory allocation is a classical memory
allocation model. Here, a system assigns
consecutive memory blocks (that is, memory blocks
having consecutive addresses) to a process.
when a process needs memory for execution. The
size of the process is compared with the amount of
contiguous main memory available to execute the
process.
If sufficient contiguous memory is found, the memory
is allocated and the process starts its execution.
Otherwise, the process is added to a queue of waiting
processes until sufficient free contiguous memory is
available.
 Contiguous Memory Allocation

The main memory must accommodate both the

operating system and the various user processes.
Limited resource, must allocate efficiently
Each process contained in single contiguous section
of memory.
The main memory is usually divided into two
partitions: one for the operating system and one for
the user processes.
Resident operating system, usually held in low
memory with interrupt vector
User processes then held in high memory
 Contiguous Memory Allocation

Array is a very good example of contiguous

memory allocation because for arrays OS allocate
contiguous memory.
Advantage of contiguous memory is that access
time is very less. You just need to remember the
base address.
A major disadvantage of contiguous memory
allocation is External Fragmentation.
 Memory Protection
Relocation registers(Base Register) used to protect
user processes from each other.
Base register contains value of smallest physical
address
Limit register contains range of logical addresses –
each logical address must be less than the limit
register
MMU maps logical address dynamically by adding
the limit register value to the value in the relocation
register.
Hardware Support for memory protection
 Memory Allocation
One method of allocating contiguous memory is to
divide all available memory into fixed number of
partitions (equal/variable size)
Each partition may contain one process.
Degree of multiprogramming limited by number of
partitions and it also restricts the maximum size of
each process, and is no longer used.
Fixed partition method may lead to internal
fragmentation.
 Variable Partition (Dynamic)
Variable-partition sizes are used for efficiency
Hole – one large block of available memory; holes of
various size are scattered throughout memory.
When a process arrives, it is allocated memory from a
hole large enough to accommodate it.
When a process terminates, it releases its block of
memory, which is then placed back in the set of holes.
If the new hole is adjacent to other holes, these
adjacent holes are merged to form one larger hole.
Operating system maintains information about:
a) allocated partitions b) free partitions (hole)
 Variable Partition
When a process terminates, it releases its block of
memory, which is then placed back in the set of
holes. If the new hole is adjacent to other holes,
these adjacent holes are merged to form one larger
hole.
 Memory Allocation

• This results in two noncontiguous holes

 Dynamic Storage-Allocation Problem
How to satisfy a request of size n from a list of free
holes? (Following strategies are used for selecting
free hole).
First-fit: Allocate the first hole that is big enough
Best-fit: Allocate the smallest hole that is big
enough; must search entire list,
Produces the smallest leftover hole
Worst-fit: Allocate the largest hole; must also
search entire list
Produces the largest leftover hole
which may be more useful than the smaller
leftover hole from a best-fit approach. (Justify ?)
 Dynamic Storage-Allocation Problem
First-fit and best-fit better than worst-fit in terms of
speed and storage utilization.
 Fragmentation
All the memory allocation strategies suffer
from external fragmentation, though first and best
fits experience the problems more than worst fit.
External fragmentation means that the available
memory is broken up into lots of little pieces, none of
which is big enough to satisfy the next memory
requirement, although the sum total could.
Memory fragmentation can be internal as well as
external.
 Fragmentation

External Fragmentation – total memory space

exists to satisfy a request, but it is not contiguous
Internal Fragmentation – allocated memory may
be slightly larger than requested memory; this size
difference is memory internal to a partition, but not
being used. This difference between these two sizes
is known as internal fragmentation.
First fit analysis reveals that given N blocks
allocated, 0.5 N blocks lost to fragmentation.
 Solution to Fragmentation (Cont.)
Reduce external fragmentation by compaction
Shuffle memory contents to place all free memory
together in one large block
Compaction is possible only if relocation is
dynamic, and is done at execution time
Fragmentation is a general problem in computing that
can occur anywhere, we must manage blocks of
memory and data.
One more solution to external fragmentation: paging.
Compaction
 Paging
Paging is a memory management scheme that
eliminates the need for contiguous allocation of
physical memory.
This scheme permits the physical address space of
a process can be non-contiguous.
The Physical Address Space is conceptually divided
into a number of fixed-size blocks, called frames.
The process (logical address Space) is also divided
into fixed-size blocks, called pages.
Page Size = Frame Size
Size is power of 2, between 512 bytes and 16
Mbytes
 Paging
Avoids external fragmentation
Avoids problem of varying sized memory chunks
To run a program of size N pages, need to find N
free frames and load program
Set up a page table to translate logical to physical
addresses
 Example of Paging in OS
The main memory size is 16 KB and Frame size is 1
KB.
Here, the main memory will be divided into the
collection of 16 frames of 1 KB each.
There are 4 separate processes in the system that is
A1, A2, A3, and A4 of 4 KB each.
Here, all the processes are divided into pages of 1
KB each so that operating system can store one
page in one frame.
At the beginning of the process, all the frames
remain empty so that all the pages of the processes
will get stored in a contiguous way.
 Example

A2 and A4 are moved to the waiting state after some

time.
Therefore, eight frames become empty, and so other
pages can be loaded in that empty blocks.
The process A5 of size 8 pages (8 KB) are waiting in
the ready queue.
This allows to load the pages of process A5 in place
of A2 and A4.
 Paging
Logical Address or Virtual Address (represented in
bits): An address generated by the CPU
Logical Address Space or Virtual Address Space(
represented in words or bytes): The set of all logical
addresses generated by a program
Physical Address (represented in bits): An address
actually available on memory unit
Physical Address Space (represented in words or
bytes): The set of all physical addresses.
 Logical Address
Address generated by CPU is divided into
Page number(p): Number of bits required to
represent the pages in Logical Address Space or
Page number
Page offset(d): Number of bits required to
represent particular word in a page or page size of
Logical Address Space or word number of a page or
page offset.
 Physical Address
Physical Address is divided into
Frame number(f): Number of bits required to
represent the frame of Physical Address Space or
Frame number.
Frame offset(d): Number of bits required to
represent particular word in a frame or frame size of
Physical Address Space or word number of a frame
or frame offset.
 Logical Address
For given logical address space 2m and page size
2n
Physical Address
Paging Hardware
Paging Model of Logical and Physical Memory
 Example

• Physical Address = 12 bits, then Physical

Address Space = 4 K words/bytes
• Logical Address = 13 bits, then Logical
Address Space = 8 K words
• Page size = frame size = 1 K words/bytes
(assumption)
 Paging Example
Logical address: n = 2 and m = 4. Using a page
size of 4 bytes and a physical memory of 32 bytes (8
frames)
Paging Example
 Paging -- Calculating internal fragmentation

Page size = 2,048 bytes

Process size = 72,766 bytes
35 pages + 1,086 bytes
Internal fragmentation of 2,048 - 1,086 = 962 bytes
 Free Frames

Before allocation After allocation

 Implementation of Page Table
Page table is kept in main memory
Page-table base register (PTBR) points to the
page table
Page-table length register (PTLR) indicates
size of the page table
In this scheme every data/instruction access
requires two memory accesses
One for the page table and one for the data /
instruction
 Implementation of Page Table with TLB
The two memory access problem can be solved by
the use of a special fast-lookup hardware cache
called translation look-aside buffers (TLBs)
The TLB is associative, high speed memory.
TLBs typically small (64 to 1,024 entries)
 Translation Look-Aside Buffer

On a TLB miss, value is loaded into the TLB for

faster access next time
Associative memory – parallel search
Address translation (p, d)
If p is in associative register, get frame # out
Otherwise get frame # from page table in memory
 TLB

Page # Frame #
Paging Hardware With TLB
 Effective Access Time
Hit ratio – percentage of times that a page number
is found in the TLB
An 80% hit ratio means that we find the desired
page number in the TLB 80% of the time.
Suppose that 10 nanoseconds used to access
memory.
If we find the desired page in TLB then a
mapped-memory access take 10 ns
Otherwise we need two memory access so it is
20 ns
 Effective Access Time
Effective Access Time (EAT)
EAT = 0.80 x 10 + 0.20 x 20 = 12
nanoseconds
implying 20% slowdown in access time
Consider amore realistic hit ratio of 99%,
EAT = 0.99 x 10 + 0.01 x 20 = 10.1ns
implying only 1% slowdown in access time.
 Valid-invalid (Present/Absent) bit
Valid-invalid(1/0) bit attached to each entry in the
page table:
“valid” indicates that the associated page is in the
memory’
“invalid” indicates that the page is not in the
memory’and generates page fault.
Valid (v) or Invalid (i) Bit In A Page Table
 Shared Pages
Shared code
One copy of read-only (reentrant) code shared
among processes (i.e., text editors, compilers,
window systems)
Similar to multiple threads sharing the same
process space
Also useful for inter-process communication if
sharing of read-write pages is allowed
Private code and data
Each process keeps a separate copy of the code
and data. The pages for the private code and
data can appear anywhere in the logical address
space
Shared Pages Example
Shared Pages Example
 Structure of the Page Table
Memory structures for paging can get huge using
straight-forward methods
Consider a 32-bit logical address space as on
modern computers
Page size of 4 KB (212)
Page table would have 1 million entries (232 / 212)
If each entry is 4 bytes ➔ each process 4 MB of
physical address space for the page table alone.
Which is too large to reasonably keep in
contiguous memory.
 Two-Level Paging Example
A logical address (on 32-bit machine with 4K page
size) is divided into:
a page number consisting of 20 bits
a page offset consisting of 12 bits (4K frame)
One option is to use a two-tier paging system, i.e. to
page the page table.
the 20 bits described above could be broken down
into two 10-bit page numbers. The first identifies an
entry in the outer page table, which identifies where
in memory to find one page of an inner page table.
The second 10 bits finds a specific entry in that inner
page table, which in turn identifies a particular frame
in physical memory
 Two-Level Paging Example

Thus, a logical address is as follows:

where p1 is an index into the outer page table,

and p2 is the displacement within the page of
the inner page table and is known as forward-
mapped page table
A two-level page-table scheme
Address-Translation Scheme
 64-bit Logical Address Space
Even two-level paging scheme not sufficient
If page size is 4 KB (212)
Then page table has 252 entries
If two level scheme, inner page tables could be 210
4-byte entries
Address would look like
 64-bit Logical Address Space

Outer page table has 242 entries or 244 bytes

One solution is to add a 2nd outer page table
Three-level Paging Scheme
Swapping with Paging
 Segmentation
Segmentation is a memory management technique
in which each job/program(memory) is divided into
several segments/parts of different sizes. Each
segment can be allocated to a process
Segmentation gives user’s view of the
process(Memory) which paging does not give.
The details about each segment are stored in a table
called a segment table
Segment table contains:
Base: It is the base address of the segment
Limit: It is the length of the segment.
 Segmentation
A program is a collection of segments. A segment is
a logical unit such as:
main program
procedure
function
method
object
local variables, global variables
common block
stack, symbol table
arrays
User’s view of the program
Logical View of Segmentation

1
1 4
2

3 2
4
3

user space physical memory space

 Segmentation Architecture
Logical address consists of a two tuple:
<segment-number, offset>,
Segment table – maps to physical addresses; each
table entry has:
base – contains the starting physical address
where the segments reside in memory
limit – specifies the length of the segment
Segment-table base register (STBR) points to the
segment table’s location in memory
Segment-table length register (STLR) indicates
number of segments used by a program;
segment number s is legal if s < STLR
Segmentation Hardware
End of Chapter 6