VHDL Stands For VHSIC Hardware Description Language
VHDL Stands For VHSIC Hardware Description Language
VHDL Stands For VHSIC Hardware Description Language
What is HDL?
HDL stands for Hardware Description Language. It is a programming
language that is used to describe, simulate, and create hardware like digital circuits
(ICS). HDL is mainly used to discover the faults in the design before implementing it
in the hardware.
What is VHDL?
VHDL stands for Very High-Speed Integration Circuit HDL (Hardware Description
Language). It is an IEEE (Institute of Electrical and Electronics Engineers) standard
hardware description language that is used to describe and simulate the behavior of
complex digital circuits.
The most popular examples of VHDL are Odd Parity Generator, Pulse Generator,
Priority Encoder, Behavioral Model for 16 words, 8bit RAM
o The Entity is used to specify the input and output ports of the circuit. An Entity
usually has one or more ports that can be inputs (in), outputs (out), input-
outputs (in out), or buffer.
o An Entity may also include a set of generic values that are used to declare
properties of the circuit.
o Entity Declaration
o Simplified syntax
o entity entity_name is
o ort (
o port_1_name : mode data_type;
o ort_2_name : mode data_type;
o .......
o Port_n_name : mode data_type
o );
o end entity_name;
o entiy orgate is
o port (
o a : in std_logic;
o b : in std_logic;
o c : out std_logic
o );
o end orgate;
o Using generic
If an entity is generic, then it must be declared before the ports. Generic does not
have a mode, so it can only pass information into the entity.
Syntax:
1. entity entity_name is
2. generic (
3. generic_1_name : data_type;
4. generic_2_name : data_type;
5. ........
6. generic_n_name : data_type
7. );
8. port (
9. port_1_name : mode data_type;
10. port_2_name : mode data_type;
11. ........
12. Port_n_name : mode data_type
13. );
14. end entity_name;
Example:
1. entity Logic_Gates is
2. generic (Delay : Time := 10ns);
3. port (
4. Input1 : in std_logic;
5. Input2 : in std_logic;
6. Output : out std_logic
7. );
8. end Logic_Gates;
Modes of Port
in Input port
out Output port
inout Bidirectional port
buffer Buffered output port
2. Architecture
Architecture is the actual description of the design, which is used to describe how the
circuit operates. It can contain both concurrent and sequential statements.
Architecture Declaration
1. architecture architecture_name of entity_name is
2. begin
3. (concurrent statements )
4. end architecture_name;
Example:
1. architecture synthesis of andgate is
2. begin
3. c <= a AND b;
4. end synthesis;
3. Configuration
A configuration defines how the design hierarchy is linked together. It is also used to
associate architecture with an entity.
Configuration Declaration
1. configuration configuration_name of entity_name is
2. --configuration declarations
3. for architecture_name
4. for instance_label : component_name
5. use entity library_name.entity_name(architecture_name);
6. end for;
7. --
8. end for;
9. end [configuration] [configuration_name];
Example:
1. configuration demo_config of even_detector_testbench is
2. for tb_archi
3. for uut : even_detector
4. use entity work.even_detector (sop_archi);
5. end for;
6. end for;
7. end demo_config;
AND gates have two inputs and one output, and they implement the
boolean logic of multiplication. Its equation is as follows:
Y(A and B) = A.B
Logic diagram and logic equation of NAND gate
NAND gates have two inputs and one output and implement the inverse
boolean logic of multiplication. Its equation is as follows:
Y (A nand B) = = A|B =
Logic diagram and logic equation of OR gate
OR gates have two inputs and one output, and they implement the boolean
logic of addition. Its equation is as follows:
Y (A or B) = A + B
Logic diagram and logic equation of NOR gate
NOR gates have two inputs and one output, and they implement the
inverse boolean logic of addition. Its equation is as follows:
Y (A nor B) = =
Logic diagram and logic equation of NOT gate
NOT gates have one input and one output, and it implements the boolean
logic of inversion. It is an inverter. Its equation is as follows:
Y (not A) = A’ =
Logic diagram and logic equation of XOR gate
XOR gates have two inputs and one output, and they implement the special
boolean logic of inequality detection. The EXOR gate gives a high output
every time it detects an inequality in the inputs. Its equation is as follows:
Y (A exor B) = A B = AB’ + A’B
Logic diagram and logic equation of XNOR gate
XNOR gates have two inputs and one output, and they implement the
special boolean logic of equality detection. The EXNOR gate gives a high
output every time it detects equality in the inputs. Its equation is as follows:
Y (A exnor B) = = A’B’ + AB
Now that we have the logic equations of all the gates, we can begin writing
the code by first declaring the architecture-entity pair. Here we will show
that the architecture we are following is dataflow, and we will declare our
input and output ports.
We are naming our entity as ALLGATES_SOURCE.
You can name it anything and also use the underscore symbol. This is just
for better file management. We will apply the same inputs to all the logic
gates and take separate outputs from each of them. So the syntax will be
like this:
entity ALLGATES_SOURCE is
P, Q, R, S, T, U, V : out STD_LOGIC);
end ALLGATES_SOURCE;
begin
Next, all that is left to do is assign the outputs to their respective boolean
expressions for each logic gate. This is done using the assignment
operator. The logic function is implemented using the appropriate operator
for the logic. These operators are called logic operators. For example, to
implement AND logic, we can simply use the and operator.
You can read all about the different operators available in VHDL here.
P <= A and B;
Q <= A nand B;
R <= A or B;
S <= A nor B;
T <= not A;
U <= A xor B;
V <= A xnor B;
end dataflow;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ALLGATES_SOURCE is
P, Q, R, S, T, U, V : out STD_LOGIC);
end ALLGATES_SOURCE;
begin
--- you have to remember the commands for boolean logic in VHDL as shown
below
P < = A and B;
Q < = A nand B;
R <= A or B;
S <= A nor B;
T <= not A;
U <= A xor B;
V <= A xnor B;
end dataflow;
Library ieee;
use ieee.std_logic_1164.all;
entity half_adder is
port(a,b:in bit; sum,carry:out bit);
end half_adder;
entity half_sub is
port(a,c:in bit; d,b:out bit);
end half_sub;
entity full_sub is
port(a,b,c:in bit; sub,borrow:out bit);
end full_sub;
entity mux is
port(S1,S0,D0,D1,D2,D3:in bit; Y:out bit);
end mux;
entity demux is
port(S1,S0,D:in bit; Y0,Y1,Y2,Y3:out bit);
end demux;
entity enc is
port(i0,i1,i2,i3,i4,i5,i6,i7:in bit; o0,o1,o2: out bit);
end enc;
entity dec is
port(i0,i1,i2:in bit; o0,o1,o2,o3,o4,o5,o6,o7: out bit);
end dec;
entity srflip is
port(r,s,clk:in bit; q,qbar:buffer bit);
end srflip;
entity jk is
port(
j : in STD_LOGIC;
k : in STD_LOGIC;
clk : in STD_LOGIC;
reset : in STD_LOGIC;
q : out STD_LOGIC;
qb : out STD_LOGIC
);
end jk;
architecture virat of jk is
begin
jkff : process (j,k,clk,reset) is
variable m : std_logic := '0';
begin
if (reset = '1') then
m : = '0';
elsif (rising_edge (clk)) then
if (j/ = k) then
m : = j;
elsif (j = '1' and k = '1') then
m : = not m;
end if;
end if;
q <= m;
qb <= not m;
end process jkff;
end virat;
entity dflip is
port(d,clk:in bit; q,qbar:buffer bit);
end dflip;
entity Toggle_flip_flop is
port(
t : in STD_LOGIC;
clk : in STD_LOGIC;
reset : in STD_LOGIC;
dout : out STD_LOGIC
);
end Toggle_flip_flop;
begin
if (reset = '1') then
m : = '0';
elsif (rising_edge (clk)) then
if (t = '1') then
m : = not m;
end if;
end if;
dout < = m;
end process tff;
end virat;
entity counter is
port(Clock, CLR : in std_logic;
Q : out std_logic_vector(3 downto 0)
);
end counter;
begin
if (CLR = '1') then
tmp < = "0000";
elsif (Clock'event and Clock = '1') then
mp <= tmp + 1;
end if;
end process;
Q <= tmp;
end virat;