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M. Tech. EXAMINATION, May 2019: No. of Printed Pages: 03 Roll No. ......................

This document is an exam paper for an M. Tech. course in ECE(VLSI). It contains 8 questions across 4 units on topics related to RTL simulation and synthesis with PLDs. Students are instructed to attempt 5 questions total, selecting at least one from each unit. The questions cover multi-clock domain design strategies, entity and architecture declarations for a magnitude comparator in VHDL, programmable logic devices, floorplanning, power analysis, low power design techniques, sources of power dissipation, IP cores, and netlists.

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85 views2 pages

M. Tech. EXAMINATION, May 2019: No. of Printed Pages: 03 Roll No. ......................

This document is an exam paper for an M. Tech. course in ECE(VLSI). It contains 8 questions across 4 units on topics related to RTL simulation and synthesis with PLDs. Students are instructed to attempt 5 questions total, selecting at least one from each unit. The questions cover multi-clock domain design strategies, entity and architecture declarations for a magnitude comparator in VHDL, programmable logic devices, floorplanning, power analysis, low power design techniques, sources of power dissipation, IP cores, and netlists.

Uploaded by

Harshini A
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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No. of Printed Pages : 03 Roll No. .......................

18AA1201
M. Tech. EXAMINATION, May 2019
(First Semester)
(C Scheme) (Re-appear)
ECE(VLSI)
MTVLSI501C
RTL Simulation and Synthesis with PLDs

Time : 3 Hours] [Maximum Marks : 75

Before answering the question-paper candidates


should ensure that they have been supplied to correct
and complete question-paper. No complaint, in this
regard, will be entertained after the examination.

Note : Attempt Five questions in all, selecting at


least one question from each Unit. All
questions carry equal marks.

(1-04/32) M-18AA1201 P.T.O.

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Unit I 4. (a) What is floor planning ? Explain with
proper illustrations. 8
1. Explain need and design strategies for multi-
(b) What is Power Analysis ? Why is it
clock domain designs. 15
important for VLSI circuits. 7
2. (a) Write an entity declaration for a 4 bit
Unit III
magnitude comparator. Name the output
port altb for "a less than b". 5. Enlist and explain low power VLSI design
techniques. 15
(b) Write four architecture bodies for the
entity declaration in Question 2(a) 6. (a) What are the sources of power dissipation
(above): One using an if-then-else in VLSI circuits ? 8

statement, one using Boolean equations, (b) Explain dynamic power supression in
VLSI systems. 7
one using a when-else statement, and one
using component instantiation statements. Unit IV

Unit II 7. Explain I.P. in different forms. 15

3. (a) What are Programmable logic devices ? 8. Write short notes on the following : 15
Explain in details. 8 (a) Netlist

(b) What is ESD protection ? Explain in (b) Physical IP

details. 7 (c) Speed issues.

M-18AA1201 2 (1-04/33) M-18AA1201 3 60

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