ZIGER: Annotation of AIGER with Hierarchical Information

BVSRC EECS-Department University of California at Berkeley http://www.bvsrc.org March 3, 2011

Hierarchical Model

For synthesis and verication, a RTL design will be parsed and converted into a hierarchical model and later translated/optimized in to a attened bit-level model. AIGER model captures the attened bit-level model, though the highlevel information in the hierarchical model is lost. To capture high-level abstraction in the hierarchical model and pass it into the AIGER model we propose to annotate existing AIGER constructs with hierarchical information in terms of the following: Word A word is an ordered list of bit/signals. Given the AIGER model, it is a list of Literals in the AIGER model. Port P ort corresponds to the ports in RTL module denition as the interface connecting between instances. Each port is a word with an input/output attribute to indicate this port is either an input or output of the instance. Box A box corresponds to an instance in the hierarchical model. In its minimum, we captures its boundary denition through the list of port denitions.

Ziger C++ Denitions

Figure 1 gives the C++ denitions of the Ziger classes. ziger s The container for the word, port and box annoations. ziger box s The denition of a box ziger port s Denition of a port

ziger word s Denition of a word ziger dir t Enum type of the port directions aiger ns :: Lit The Literal denition in the AIGER format. namespace ziger_ns{ typedef aiger_ns::Lit Lit; typedef enum ziger_dir_t { dir_IN=0, dir_OUT=1, dir_Undef=2 } ziger_dir_t ; typedef typedef uint32_t ziger_word_t ; uint32_t ziger_name_t ;

class ziger_word_s{ vector<Lit> _lits; // a word is a list of literals }; class ziger_port_t{ ziger_name_t _nid; // name index into ziger_s::_names ziger_word_t _wid; // word index into ziger_s::_words ziger_dir_t _dir; // port direction }; class ziger_box_s { vector<ziger_port_t> _ports; // a box is a list of port definitions }; class ziger_s { vector<char *> _names; vector<ziger_box_s> _boxes; vector<ziger_word_s> _words; }; } Figure 1: Denition of Box Information

Extended AIGER File Format

TBD, upon Niklas/Alans extenstion description.

Example

In this Section, we illustrate the hierarchical information captured from a RTL design module in Figure 2. module counter ( clk, reset, result, ena ); input clk; input reset; input ena; output [7:0] result; reg [7:0] result; always @(posedge clk or posedge reset) begin if (reset) begin result <= 0; end else if (ena) begin result <= result + 1; end end property a0; @(posedge clk) disable iff (reset) result < 126; endproperty p_a0: assert property(a0); endmodule Figure 2: Verilog Counter Module For the Verilog module in Figure 2, the box information is captured in the following: word: w 0 /counter/clk edge_Undef word: w 1 /counter/reset edge_Zero word: w 2 /counter/result[7:0] +16 +14 +12 3

+10 +8 +6 +4 +2 word: w 3 /counter/ena +21 word: w 4 /counter/i2/o edge_One word: w 5 /counter/add_3/cin edge_Zero word: w 6 /counter/add_3/a[7:0] +16 +14 +12 +10 +8 +6 +4 +2 word: w 7 /counter/add_3/b[7:0] edge_Zero edge_Zero edge_Zero edge_Zero edge_Zero edge_Zero edge_Zero edge_One word: w 8 /counter/add_3/o[7:0] -70 -63 -56 -49 -42 -35 -28 -2 word: w 9 /counter/add_3/cout edge_Undef word: w 10 /counter/mux_4/d0[7:0] +16 +14 +12 +10 +8 4

+6 +4 +2 word: w 11 /counter/mux_4/d1[7:0] -70 -63 -56 -49 -42 -35 -28 -2 word: w 12 /counter/mux_4/cond +21 word: w 13 /counter/mux_4/o[7:0] -72 -65 -58 -51 -44 -37 -30 -24 word: w 14 /counter/i7/i edge_Undef word: w 15 /counter/i7/o edge_Undef word: w 16 /counter/LessThan_7/cin edge_Zero word: w 17 /counter/LessThan_7/a[7:0] +16 +14 +12 +10 +8 +6 +4 +2 word: w 18 /counter/LessThan_7/b[7:0] edge_Zero edge_One edge_One edge_One edge_One edge_One edge_One 5

edge_Zero word: w 19 /counter/LessThan_7/o edge_Undef word: w 20 /counter/i9/a0 edge_Zero word: w 21 /counter/i9/a1 edge_Undef word: w 22 /counter/i9/o edge_Undef word: w 23 /counter/i10/a0 edge_Undef word: w 24 /counter/i10/a1 edge_Undef word: w 25 /counter/i10/o edge_Undef word: w 26 /counter/p_a0/c edge_Undef word: w 27 /counter/result_reg/q[7:0] +16 +14 +12 +10 +8 +6 +4 +2 box: //counter w 0 IN /counter/clk w 1 IN /counter/reset w 2 OUT /counter/result[7:0] w 3 IN /counter/ena box: /counter/i1 w -1 IN port_Undef box: /counter/i2 w 4 OUT /counter/i2/o box: /counter/add_3 w 5 IN /counter/add_3/cin w 6 IN /counter/add_3/a[7:0] w 7 IN /counter/add_3/b[7:0] w 8 OUT /counter/add_3/o[7:0] w 9 OUT /counter/add_3/cout box: /counter/mux_4 6

w w w w

10 11 12 13

IN IN IN OUT

/counter/mux_4/d0[7:0] /counter/mux_4/d1[7:0] /counter/mux_4/cond /counter/mux_4/o[7:0]

box: /counter/i7 w 14 IN /counter/i7/i w 15 OUT /counter/i7/o box: /counter/LessThan_7 w 16 IN /counter/LessThan_7/cin w 17 IN /counter/LessThan_7/a[7:0] w 18 IN /counter/LessThan_7/b[7:0] w 19 OUT /counter/LessThan_7/o box: /counter/i9 w 20 IN /counter/i9/a0 w 21 IN /counter/i9/a1 w 22 OUT /counter/i9/o box: /counter/i10 w 23 IN /counter/i10/a0 w 24 IN /counter/i10/a1 w 25 OUT /counter/i10/o box: /counter/p_a0 w 26 IN /counter/p_a0/c box: /counter/result_reg w 27 OUT /counter/result_reg/q[7:0]