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TB Memory

This document describes a testbench module for testing a memory module. It defines the ports and parameters of the memory, generates a clock signal, writes data to different addresses and reads it back to verify functionality.

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jallaravi
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26 views

TB Memory

This document describes a testbench module for testing a memory module. It defines the ports and parameters of the memory, generates a clock signal, writes data to different addresses and reads it back to verify functionality.

Uploaded by

jallaravi
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as TXT, PDF, TXT or read online on Scribd
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`timescale 1 ns/ 1 ps

module tb_memory;

localparam WIDTH = 8, DEPTH=16;

reg clk_i=0 ;

reg wr_en =0;


reg [$clog2(DEPTH)-1:0] wr_addr=0;
reg [WIDTH-1:0] wr_data=0;

// rd port
reg [$clog2(DEPTH)-1:0] rd_addr=0;
wire[WIDTH-1: 0] rd_data;

localparam T=10;

//clock generator
always #(T/2) clk_i =~clk_i;

integer i=0;

// module INST
memory U_MEM (
.clk_i (clk_i ),
.wr_en (wr_en ),
.wr_addr (wr_addr),
.wr_data (wr_data),

.rd_addr (rd_addr),
.rd_data (rd_data)
);

task wr_tx(
input [WIDTH-1:0] w_addr,
input [WIDTH-1:0] w_data
);
begin
$display ("-------------------- WR TRANSACTION--------------");
$display ("Writing addr=%h with data = %h",w_addr, w_data);
@(negedge clk_i);
wr_en = 1'b1;
wr_data = w_data;
wr_addr = w_addr;

@(negedge clk_i);
wr_en = 1'b0;
end
endtask

task rd_tx(
input [$clog2(DEPTH)-1:0] r_addr,
output [WIDTH-1:0] r_data);
begin
$display ("-------------------- RD TRANSACTION--------------");
//$display ("Reading address = %h", r_addr);
@(negedge clk_i);
rd_addr = r_addr;

@(posedge clk_i); // latched address here and outputs data on next pos edge

@(posedge clk_i);
r_data = rd_data;
$display ("Reading address = %h read data = %h", r_addr,r_data);

end
endtask

reg [WIDTH-1:0] tmp_rd_data;

integer mem_addr = 0;

initial begin
$dumpfile ("waveform.vcd");
//$monitor ("wr_addr=%h wr_data =%h rd_addr=%h rd_data=
%h",wr_addr,wr_data,rd_addr,rd_data);
$dumpvars (0,tb_memory);

for (mem_addr=0;mem_addr<16;mem_addr=mem_addr+1) begin


wr_tx (mem_addr,mem_addr+1);
#100;

@(posedge clk_i);
rd_tx(mem_addr,tmp_rd_data);
//$display ("Read data =%h",tmp_rd_data);
end

#100;
$finish;
end

endmodule

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