DIGITAL SYSTEM DESIGN LAB

Course Code Category Hours/Week Credits Maximum marks

L T P C CIA SEE Total
A5EC13 PCC - - 3 1.5 30 70 100

Course Objectives:
1. To get familiarity with functionalities of IC’s.
2. To learn how to design a Boolean expression using ICs.
3. To learn designing of combinational and sequential logic circuits
4. To learn complex circuits like counter using the combination of ICs.
Course Outcomes:
After going through this course the student will be able to
1. Verify the functionality of various Digital ICs.
2. Design any digital logic circuits using ICs
3. Design and verify the functionality of combinational circuits.
4. Design and verify the functionality of sequential circuits.

To Verify the functionality of the following using IC’s

1. Study of logic gates and verify their truth tables.
2. Implement Boolean function using AOI logic.
3. Adder and sub-tractors.
4. BCD to EXCESS-3 converter.
5. Binary to gray /gray to binary code converter.
6. Verification of truth tables of R-S flip-flop , J-K flip-flop , T flip-flop and D flip-flop.
7. Implementation and verification of decoder.
8. Implementation and verification of encoder.
9. Implementation of 4x1 multiplexer.
10. Design shift register using Flip – flop ICs.
11. Design and verify the 4-bit synchronous counter.
12. To design and verify 4 bit ripple (asynchronous counter).
13. Implement a 4-bit ring/Johnson counter.

Reference Books :
1. Digital Design – Morris Mano, PHI, 3rd Edition.
2. Switching Theory and Logic Design – A. Anand Kumar, PHI, 2nd Edition.
3. Switching and Finite Automata Theory – Zvi Kohavi & Niraj K, Jha, 3rd Edition, Cambridge.

1. Study of Logic Gates and Verify their Truth Tables

Aim: - Verification and interpretation of truth tables for AND, OR, NOT, NAND, NOR Exclusive
OR (EX-OR), Exclusive NOR (EX-NOR) Gates.

Equipment Required:

SL.No Component Specification Quantity

1 AND Gate IC 7408 1
2 NAND Gate IC 7400 1
3 OR Gate IC 7432 1
4 NOR Gate IC 7402 1
5 XOR Gate IC 7486 1
6 NOT Gate IC 7404 1
7 IC trainer Kit - 1
8 Connecting - Asper required
Wires/Patch Chords

Theory:
Logic gates are electronic circuits which perform logical functions on one or more inputs
toproduce one output. There are seven logic gates. When all the input combinations of a logic gate
are written in a series and their corresponding outputs written along them, then this input/ output
combination is called Truth Table.OR, AND and NOT are basic gates. NAND, NOR are known as
universal gates. Various gates and their working is explained here.
AND GATE:
The AND gate performs a logical multiplication commonly known as AND function. The outputis
high when both the inputs are high. The output is low level when any one of the inputs is low.
OR GATE:
The OR gate performs a logical addition commonly known as OR function. The output is
highwhen any one of the inputs is high. The output is low level when both the inputs are low.
NOTGATE
The NOT gate is called an inverter. The output is high when the input is low. The output is
lowwhen the input is high.
NAND GATE:
The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low
andany one of the input is low .The output is low level when both inputs are high.

NOR GATE:
The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low.
Theoutput is low when one or both inputs are high.

X-OR GATE:
The output is high when any one of the inputs is high. The output is low when both the inputs
arelow and both the inputs are high.

PROCEDURE:
1. Connect the trainer kit to ac power supply.
 2. Connect the inputs of any one logic gate to the logic sources and its output to the logic
indicator.
3. Apply various input combinations and observe output for each one.
4. Verify the truth table for each input/ output combination.
5. Repeat the process for all other logic gates.
6. Switch off the ac power supply.

CIRCUIT DIAGRAMS:
GateNumber Truth Table Pin digram
IC 7408 AND
gate

A B C=A.B
0 0 0
0 1 0
1 0 0
1 1 1

IC 7408
NAND gate
A B C=(A.B
)’
0 0 1
0 1 1
1 0 1
1 1 0

IC 7432 OR A B C=A+B
Gate
0 0 0
0 1 1
1 0 1
1 1 1
IC 7402 NOR
Gate

A B C=A+B
0 0 0
0 1 1
1 0 1
1 1 1

IC 7486 EX-OR
Gate

A B C=A’B
+AB’
0 0 0
0 1 1
1 0 1
1 1 0

IC 7404 NOT
Gate A A’
0 1
1 0
PRECAUTIONS:

1. Make the connections according to the IC pindiagram.

2. The connections should betight.
3. The Vcc and ground should be applied carefully at the specified pinonly.

RESULT:Verified all the .logic gates with their Truth Tables

2. IMPLEMENTATION OF BOOLENA EXPRESSION USING AOI LOGIC

Aim: - A. Implement Exclusive-OR gate using AOI logic.

B. Implement Boolean function F=xy+x’y’+y’z using AOI logic

EQIPMENT REQUIRED:

SL.No Component Specification Quantity

1 AND Gate IC 7408 1
2 OR Gate IC 7432 1
3 NOT Gate IC 7404 1
4 IC trainer Kit - 1
5 Connecting - Asper required
Wires/Patch Chords
THEORY: A binary variable can take the value of 0 or 1. A Boolean function is an expression
formed withbinary variables, the two binary operators OR and AND, and unary operator NOT,
parentheses, and an equal sign. For a given value of the variables, the function can be either 0 or
1.Boolean function represented as an algebraic expression may be transformed from an algebraic
expression into a logic diagram composed of AND, OR, and NOT gates. Every Boolean
function can be realized by a And-Or-Not gates i.e. using AOI logic.

LOGIC DIAGRAM:

1. F=A’b+AB’

2. F=xy+x’y’+y’z

PROCEDURE:
 1. Connect the trainer kit to ac power supply.
2. Verify the gates and make connections as per circuit diagram-A.
3. Apply various input combinations and observe output for each one.
4. Verify the truth table for each input/ output combination.
5. Repeat the process for circuit diagram-B.
6. Switch off the ac power supply.
Truth Tables:

1. EX-OR Gate: 2. F= xy+x’y’+y’z

X Y Z XY X’ Y’Z F
Y
0 0 0 0 0 0 0
0 0 1 0 0 1 1
0 1 0 0 1 0 1
0 1 0 0 1 0 1
1 0 0 0 0 0 0
1 0 1 0 0 1 1
1 1 0 1 0 0 1
1 1 1 1 0 0 1

A B A’B+AB’
0 0 0
0 1 1
1 0 1
1 1 0

RESULT: Implemented and verified boolean expressions using AOI Logic

3. ADDER AND SUBTRACTORS

Aim: - To design and construct half adder, full adder using logic gates and verify the truth table.

EQUIPMENT REQUIRED:
 SL.No Component Specification Quantity
1 AND Gate IC 7408 1
2 OR Gate IC 7432 1
3 NOT Gate IC 7404 1
4 EX-OR Gate IC 7486 1
5 IC trainer Kit - 1
6 Connecting - Asper required
Wires/Patch Chords

THEORY:

HALF ADDER: A half adder has two inputs for the two bits to be added and two outputs one from
the sum ‘ S’ and other from the carry ‘ c’ into the higher adder position. Above circuit is
called as a carry signal from the addition of the less significant bits sum from the X-OR Gate the
carry out from the AND gate.

FULL ADDER:A full adder is a combinational circuit that forms the arithmetic sum of input; it
consists of three inputs and two outputs. A full adder is useful to add three bits at a time but a half
adder cannot do so. In full adder sum output will be taken from X-OR Gate, carry output will be
taken from OR Gate.

HALF SUBTRACTOR: The half subtractor is constructed using X-OR and AND Gate. The half
subtractor has two input and two outputs. The outputs are difference and borrow. The difference can
be applied using X- OR Gate, borrow output can be implemented using an AND Gate and an
inverter.

FULL SUBTRACTOR:The full subtractor is a combination of X-OR, AND, OR, NOT

Gates. In a full subtractor the logic circuit should have three inputs and two outputs. The two half
subtractor put together gives a full subtractor .The first half subtractor will be C and A B. The
output will be difference output of full subtractor. The expression AB assembles the borrow output
of the half subtractor and the second term is the inverted difference output of first X-OR

CIRCUIT DIAGRAMS:

HALF ADDER:

A B Sum Carry
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
FULL ADDER:
A B Cin Sum Carryout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

A B Difference Borrow
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
HALF SUBTRACTOR:
FULL SUBTRACTOR:

A B Bin Difference Borrow

0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
PROCEDURE:

(i) Verify the gates and make Connections as per logic diagram.
(ii) Connect Pin-14 of all ICs to +5V and Pin-7 to ground.
(iii) Apply various combinations of inputs to A,B,C according to truth table.
(iv) Observe and note down the output readings for SUM and CARRY for different
combinations of inputs and verify the truth table.

RESULT: Implemented half adder and full adder and verified the truth tables
 4. BCD TO EXCESS-3 CONVERTER

AIM: To Design and Implement BCD TO EXCESS-3 CONVERTER and verify the truth table

EQUIPMENT REQUIRED:

SL.No Component Specification Quantity

1 AND Gate IC 7408 1
2 OR Gate IC 7432 1
3 NOT Gate IC 7404 1
4 EX-OR Gate IC 7486 1
5 IC trainer Kit - 1
6 Connecting - Asper required
Wires/Patch Chords

THEORY:

The availability of large variety of codes for the same discrete elements of
information results in the use of different codes by different systems. A conversion circuit
must be inserted between the two systems if each uses different codes for same information.
Thus, code converter is a circuit that makes the two systems compatible even though each
uses different binary code.

Binary Coded Decimal:Binary Coded Decimal is a method of using binary digits to

represent the decimal digits 0 through 9. It is possible to assign weights to the binary bits
according to their positions. The weights in the BCD code are 8, 4, 2 and 1. Ex: (137) 10 - BCD
equivalent (0001 0011 0111)2

Excess-3 Code:This is an un-weighted code. Its code assignment is obtained from the
corresponding value of BCD after the addition of (0011)2.

BCD to Excess-3 (or) Excess-3 to BCD:Since each code uses four bits to represent a decimal
digit, there must be four inputs and four output variables. The input variable are designated as
B3, B2, B1, B0 and the output variables are designated as E3, E2, E1, E0 in the truth table.
Four binary variables have sixteen different input combinations, only ten of the input
combinations are listed in the truth table.The six bit combinations not listed for the input
variables are don’t care combination. The Boolean functions are obtained from K-Map
for each output variable. The combinational logic for t he code converters are
designed according the Boolean expressions fromK-Map simplification. The Boolean
expressions from the K-Map are shown below. Each one of the four maps represents one of the
four outputs of the circuit as a function of the four input variables. A two-level logic diagram
may be obtained directly from the Boolean expressions derived by the maps. These are various
other possibilities for a logic diagram that implements this circuit.
TRUTH TABLE:

BCD CODE EXCESS-3 CODE

A B C D W X Y Z
0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0
1 0 1 0 X X X X
1 0 1 1 X X X X
1 1 0 0 X X X X
1 1 0 1 X X X X
1 1 1 0 X X X X
1 1 1 1 X X X X

K-Map:

13
CIRCUIT DIAGRAM:

RESULT:the output of BCD to EXCESS-3 Code converter is verified.

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 5. BINARY TO GRAY / GRAY TO BINARY CODE CONVERTER

AIM: verify the truth tables of gray to binary and binary to gray code converter.

EQUIPMENT REQUIRED:

SL.No Component Specification Quantity

1 NOT Gate IC 7404 1
2 EX-OR Gate IC 7486 1
3 IC trainer Kit - 1
4 Connecting - Asper required
Wires/Patch Chords
THEORY:

BINARY TO GRAY CONVERSIONGray Code system is a binary number system in which

every successive pair of numbers differs in only one bit. It is used in applications in which the
normal sequence of binary numbers generated by the hardware may produce an error or
ambiguity during the transition from one number to the next.
For example, the states of a system may change from 3(011) to 4(100) as- 011 — 001
— 101 — 100. Therefore there is a high chance of a wrong state being read while the system
changes from the initial state to the final state.
This could have serious consequences for the machine using the information. The Gray code
eliminates this problem since only one bit changes its value during any transition between two
numbers To find the corresponding digital circuit, we will use the K-Map technique for each of
the gray code bits as output with all of the binary bits as input.

TRUTH TABLE:

BINARY TO GRAY CONVERSION:

BINARY CODE GRAY CODE

B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
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 1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1

B3= G3

B2 ⊕ B3

=G2B1 ⊕ B2

=G1B0⊕B1=

G0

GRAYTO BINARYCODECONVERTER

G0⊕G1⊕G2⊕G3=B0G1⊕

G2⊕G3=B1

G2⊕G3=B2G3

=B3

16
 GRAY CODE BINARY CODE
G3 G2 G1 G0 B3 B2 B1 B0
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
RESULT:truth tables of Binary to gray/ gray to binary are verified

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 6. VERIFICATION OF 4-BIT COMPARATOR
AIM: 1.To verify the operation of 4 bit comparator using IC 7485.

APPARATUS REQUIRED :

1. CDS Board / Bread Boar

2. Regulated power supply
3. Function generator
4. Connecting patch chords

COMPONENTS REQUIRED:

1. IC 7485: 1No.

PIN DIAGRAM:

18
LOGIC DIAGRAM

Truth table :

THEORY:

Magnitude Comparator is a logical circuit , which compares two signals A and B and
generates three logical outputs, whether A > B, A = B, or A < B . The basic function of a
comparator is to compare the magnitudes of two binary quantities to determine the relationship
of those quantities. IC 7485 is a high speed 4-bit Magnitude comparator , which compares two
4-bit words . It consists of three cascading inputs i.e IA<B, IA=B, IA>B with pin numbers
2,3,4. These inputs allow several comparators to be cascaded for comparison of any number of
bits greater than four. The IA = B Input must be held high for proper compare operation.

PROCEDURE:

1. Connect the circuit as per the pin configuration. Feed the 4-bit binary words A0, A1 ,
A2 , A3 and B0 , B1 , B2 , B3 from the logic input switches.

19
 2. Pin 3 of IC 7485 should be at logic ‘1’ to enable compare operation and pin2, pin4 at
logic ‘0’.
3. Observe the output A>B, A=B , and A<B on logic indicators. The outputs must be 1 or
0 respectively.
4. Repeat the steps 1 ,2 and 3 for various inputs A0 ,A1 , A2 , A3 and B0 , B1 , B2 , B3
and observe the outputs at A>B , A=B and A<B .

RESULT: The verification of 4 bit magnitude comparator is verified using IC 7485

7. VERIFICATION OF TRUTHTABLES OF R-S FLIP-FLOP, JK FLIP-FLOP,T FLIP-

FLOP, D FLIP-FLOP

AIM:To verify the truth tables of

1)SR Flip Flop
2) T type Flip Flop.
3) D type Flip Flop.
4) JK Flip Flop.

EQUIPMENT REQUIRED:

SL.No Component Specification Quantity

1 NOT Gate IC 7404 1
2 EX-OR Gate IC 7408 1
3 NOR Gate IC 7402 1
4 NAND Gate IC 7400 1
5 IC trainer Kit - 1
6 Connecting - Asper required
Wires/Patch Chords
THEORY:

Logic circuits that incorporate memory cells are called sequential logic circuits; their output
depends not only upon the present value of the input but also upon the previous
values.Sequential logic circuits often require a timing generator (a clock) for their
operation.BThe latch (flip-flop) is a basic bi-stable memory element widely used in sequential
logiccircuits. Usually there are two outputs, Q and its complementary value.Some of the most
widely used latches are listed below.

SR LATCH:

20
An S-R latch neither consists of two cross-coupled NOR gates. An S-R flip-flop can also be
design using cross-coupled NAND gates as shown. The truth tables of the circuits are shown
below. A clocked S-R flip-flop has an additional clock input so that the S and R inputs are
active only when the clock is high. When the clock goes low, the state of flip-flop is latched and
cannot change until the clock goes high again.

Therefore, the clocked S-R flip-flop is also called “enabled” S-R flip-flop. A D latch combines
the S and R inputs of an S-R latch into one input by adding an inverter. When the clock is high,
the output follows the D input, and when the clock goes low, the state is latched. A S-R flip-
flop can be converted to T-flip flop by connecting S input to Qb and R to Q.

CIRCUIT DIAGRAMS:

1. SR FLIPFLOP:

TRUTH TABLE :

21
 2. JK FLIP-FLOP:

TRUTH TABLE:

22
3. D FLIP-FLOP:

TRUTH TABLE:

23
4. T FLIP-FLOP:

TRUTH TABLE:
24
PROCEDURE:

• Check all the components for their working.

• Insert the appropriate IC into the IC base.
• Make connections as shown in the circuit diagram.
• Verify the Truth Table and observe the outputs.

RESULT:Truth tables of flip-fops are verified

8. IMPLEMENTATION AND VERIFICATION OF DECODER

25
AIM: To verify the operation and truth table of 3 – 8 decoder using IC 74138.

APPARATUS REQUIRED:

1. Bread Board / CDC Board.

2. Regulated power supply
3. Function generator.
4. Connecting Wires.

COMPONENTS REQUIRED:

1. IC74138 :1No

PIN DIAGRAM:

LOGIC DIAGRAM:

26
TRUTH TABLE:

27
 THEORY:

A decoder is a combinational circuit that connects the binary information from ‘n’ input lines
to a maximum of 2n unique out put lines . If the n – bit decoded information has unused
combinations, the decoder output will have fewer the 2n outputs. Here 3 inputs are decoded into
eight outputs, each output representing one of the minterms of 3 input variables. IC74138 is the
3*8decoder which contains three inputs and eight outputs and also three enables out of them two are
active low and one is active high. Decoders are used in the circuit where required to get more outputs
than that of the inputs which also used in the chip designing process for reducing the IC chip area.

PROCEDURE:

1. Connect G1,G2A,G2B enable inputs to 6,5,4 terminals.

2. Change the values of G1,G2A,G2B,A,B,and C, and observe the outputs Y0

to Y7

RESULT: 3 – 8 Decoder is verified with IC 74138 and truth table is observed.

28
 9. Implementation and verification of Encoder

AIM:
To set up a circuit of Decimal-to-BCD Encoder using
LEARNING OBJECTIVE:
 To learn about various applications of Encoders
 To learn to do code conversion using encoders

COMPONENTS REQUIRED:
IC 74148

THEORY:-

An encoder is a combinational logic circuit .It is the reverse of a decoder function. It has 2 to
the power n input and n output lines. An encoder accepts an active level on one of its inputs
representing a digit such as a decimal /octal digit and it convert to coded output. 
Encoder is used at the starting stage to encode the message into a unique code. Encoder encodes
different types of messages into various forms. In Digital Circuits it encodes a decimal value
into a binary word. The encoded binary word has number of bits associated with it. The number
of bits depends upon the decimal value which is being encoded.

29
IC DIAGRAM & TRUTH TABLE:-

IC DIAGRAM

30
RESULT:Truth table of decoder has been verified

31
 10. IMPLEMENTATION OF 8X1 MULTIPLEXER

AIM: To verify the operation and truth table of 8:1 multiplexer using IC 74151.

APPARATUS REQUIRED:

1. Bread Board/ CDS Board

2. Connecting patch chords.
3. Regulated power supply.
4. Function generator.

COMPONENTS REQUIRED:

1. IC 74151 :1 No.

PIN DIAGRAM:

32
LOGIC DIAGRAM:

TRUTH TABLE:

E’ C B A I0 I1 I2 I3 I4 I5 I6 I7 Y
0 0 0 0 0 X X X X X X X 0
0 0 0 0 1 X X X X X X X 1
0 0 0 1 X 0 X X X X X X 0
0 0 0 1 X 1 X X X X X X 1
0 0 1 0 X X 0 X X X X X 0
0 0 1 0 X X 1 X X X X X 1
0 0 1 1 X X X 0 X X X X 0
0 0 1 1 X X X 1 X X X X 1
0 1 0 0 X X X X 0 X X X 0
0 1 0 0 X X X X 1 X X X 1
0 1 0 1 X X X X X 0 X X 0
0 1 0 1 X X X X X 1 X X 1
0 1 1 0 X X X X X X 0 X 0
0 1 1 0 X X X X X X 1 X 1
0 1 1 1 X X X X X X X 0 0
0 1 1 1 X X X X X X X 1 1

THOERY:

Multiplexer means many to one. A multiplexer is a circuit with many inputs but
only one output. By using control signals (select lines ) we can select any input to the output.
Multiplexer is also called as data selector because the output bit depends on the input data bit
that is selected. The general idea about the multiplexing the circuit has N input signals, M
control signals and 1 output signal

33
 8 X 1 Multiplexer has 8 input signals and one output signal, three data control
or select lines. These data control lines are nothing but 3-bit binary code on the data control
signal inputs which will allow the data on the corresponding data input to pass through to the
data output.

PROCEDURE:

1. Connect the circuit as shown in fig.2.

2. Apply E=0 to enable the circuit.
3. Apply A=0, B=0,C=0 to select the input ‘I0’ at the output for both ‘0’ and ‘1’.
4. Repeat step for various values of A,B,C to select different inputs (I1 – I7) at output.
5. Draw and verify the truth table.
RESULT: The Truth table of 8:1 Multiplexer is verified by using IC 74151.

34
 11. VERIFICATION OF UNIVERSAL SHIFT REGISTER

AIM: To study the following applications of universal shift register using IC 74194

a) Shift right logic

b) Shift left logic
COMPONENTS REQUIRED:

1. Bread Board
2. Connecting patch chords
3. IC74194

PIN DIAGRAM:

CIRCUIT DIAGRAM:

35
THEORY:

A register is a digital circuit with two basic functions: data storage and data movement. The
storage capacity of a register makes it an important type of memory device. A register can
consist of one or more flip – flops used to store and shift data. The storage capacity of a register
is the total number of bits of digital data it can retain. Each stage(flip flop) in a shift register
represents one bit of storage capacity, therefore the number of stages in a register determines its
storage capacity. The shifting capability of a register permits the movement of data from stage
to stage within the register or into or out of the register upon application of clock pulses.

A universal shift register is one which has both serial and parallel input and output
capability. The IC 74194 is an example of a universal bidirectional shift register in integrated
circuit form. It is a 16-pin IC with two mode control inputs S0, S1, two serial data inputs DSR ,
DSL , four parallel data inputs P0,P1,P2,P3 , and four parallel data outputs Q0,Q1,Q2,Q3.

PROCEDURE:

1. Connect the circuit as shown in the figure1.

STEP:1 MASTER RESET

Set the inputs as below and observe the outputs as per table.

STEP:2 SHIFT LEFT LOGIC ‘ 0 ‘.

Set Q0 , Q1 , Q2 , Q3 to ‘ 1 1 1 1 ‘ by putting DSL to Logic ‘ 1 ‘ .

While running the above step, change the logic input DSL to logic ‘ 0 ‘

And S0 to logic ‘ 0 ‘ in the same sequence .Observe the following outputs after each clock
pulse and verify .

36
STEP: 3 SHIFT LEFT LOGIC ‘1’

Now switch DSL input to logic ‘ 1 ‘ and observe the shifting of logic ‘ 1 ‘ s to left as below .
Observe the following outputs after each clock pulse and verify.

STEP : 4 . SHIFT RIGHT LOGIC ‘ 0 ‘

Set the Q0 Q1 Q2 Q3 to 1 1 1 1 by setting DSR input to logic ‘ 1 ‘ .

Repeat step 3 and parallel load logic ‘ 1 ‘ s in all the 4 outputs .

Change the logic inputs of DSR to logic 0 and then of S1 to logic ‘ 0 ‘

in the same sequence . Observe the following outpus after each clock pulse and verify .

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STEP: 5 SHIFT RIGHT LOGIC ‘1’

Now at this condition of all ‘ 0 ‘ at the outputs switch DSR to logic ‘1’ this will enable all
logic as serial data and logic ‘ 1 ‘ s will be shifted successively with each clock pulse as shown
below .Observe the following table and verify the outputs .

RESULT: Verified the operation of universal shift register using IC 74194

38
 12. DESIGN AND VERIFY THE 4-BIT SYNCHRONOUS COUNTER

AIM: -Design, and verify the 4-bit synchronous counter.

EQUIPMENT REQUIRED:-

S.No. COMPONENT SPECIFICATION QTY.

1 JK FLIP FLOP IC 7476 2

2. 4 I/P AND GATE IC 7411 1

3. OR GATE IC 7432 1

4. XOR GATE IC 7486 1

5. NOT GATE IC 7404 1

6. IC TRAINER KIT - 1

7. PATCHCORDS - 35

THEORY:-
Synchronous counter: - A simple way of implementing the logic for each bit of an ascending
counter (which is what is depicted in the image to the right) is for each bit to toggle when all of
the less significant bits are at a logic high state. For example, bit 1 toggles when bit 0 is logic
high; bit 2 toggles when both bit 1 and bit 0 are logic high; bit 3 toggles when bit 2, bit 1 and
bit 0 are all high; and so on. Synchronous counters can also be implemented with hardware
finite state machines. Hardware-based counters are of this type and they can be implemented
using the IC 7476

39
IC DIAGRAM:

TRUTH TABLE:
Input Present State Next State A B C

Up/ QA QB QC QA+1 Q B+1 QC+1 JA KA JB KB JC KC

Down

0 0 0 0 1 1 1 1 X 1 X 1 X

0 1 1 1 1 1 0 X 0 X 0 X 1

0 1 1 0 1 0 1 X 0 X 1 1 X

0 1 0 1 1 0 0 X 0 0 X X 1

0 1 0 0 0 1 1 X 1 1 X 1 X

0 0 1 1 0 1 0 0 X X 0 X 1

40
 0 0 10 001 0X X1 1X

0 001 000 0X 0X X1

LOGIC DIAGRAM:

PROCEDURE:-

(i) Connections are given as per circuit diagram.

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 (ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.
PRECAUTIONS:-

1. All ICs should be checked before starting the experiment.

2. All the connection should be tight.

3. Always connect ground first and then connect Vcc.

4. Suitable type wire should be used for different types of circuit.

5. The kit should be off before change the connections.

6. After completed the experiments switch off the supply of the apparatus

RESULT: -Study of 4 bit synchronous counters and verified its truth table.

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13. TO DESIGN AND VERIFY 4-BIT RIPPLE COUNTER ( ASYNCHRONOUS
COUNTER)

AIM: - To design and verify 4 bit ripple (asynchronous counter).

APPARATUS REQUIRED:-

S.No. COMPONENT SPECIFICATION QTY.

1. JK FLIP FLOP IC 7476 2

2. NAND GATE IC 7400 1

3. IC TRAINER KIT - 1

4. PATCHCORDS - 30

THEORY:-

A counter is a register capable of counting number of clock pulse arriving at its clock input.

Counter represents the number of clock pulses arrived. A specified sequence of states appears

as counter output. This is the main difference between a register and a counter. There are two

types of counter, synchronous and asynchronous. In synchronous common clock is given to all

flip flop and in asynchronous first flip flop is clocked by external pulse and then each

successive flip flop is clocked by Q or Q output of previous stage. A soon the clock of second

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stage is triggered by output of first stage. Because of inherent propagation delay time all flip

flops are not activated at same time which results in asynchronous operation.

PIN DIAGRAM FOR IC 7476:

LOGIC DIAGRAM FOR 4 BIT

RIPPLE COUNTER:

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TRUTH TABLE:-

CLK QA QB QC QD

0 0 0 0 0

1 1 0 0 0

2 0 1 0 0

3 1 1 0 0

4 0 0 1 0

5 1 0 1 0

6 0 1 1 0

7 1 1 1 0

8 0 0 0 1

9 1 0 0 1

10 0 1 0 1

11 1 1 0 1

12 0 0 1 1

13 1 0 1 1

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 14 0 1 1 1

15 1 1 1 1

PROCEDURE:-

 Connections are given as per circuit diagram.

 Logical inputs are given as per circuit diagram.
 Observe the output and verify the truth table.
PRECAUTIONS:-

1. All ICs should be checked before starting the experiment .

2. All the connection should be tight.
3. Always connect ground first and then connect Vcc.
4. Suitable type wire should be used for different types of circuit.
5. The kit should be off before change the connections .
6. Aft er completed the experiments switch off the supply of the apparatus.

RESULT: - Study of 4 bit synchronous counter and verified its truth table .

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