®

ICL7660S

Data Sheet March 6, 2008 FN3179.5

Super Voltage Converter Features

The ICL7660S Super Voltage Converter is a monolithic • Guaranteed Lower Max Supply Current for All
CMOS voltage conversion IC that guarantees significant Temperature Ranges
performance advantages over other similar devices. It is a • Wide Operating Voltage Range 1.5V to 12V
direct replacement for the industry standard ICL7660 offering • 100% Tested at 3V
an extended operating supply voltage range up to 12V, with
• No External Diode Over Full Temperature and Voltage
lower supply current. No external diode is needed for the Range
ICL7660S. In addition, a Frequency Boost pin has been
• Boost Pin (Pin 1) for Higher Switching Frequency
incorporated to enable the user to achieve lower output
impedance despite using smaller capacitors. All • Guaranteed Minimum Power Efficiency of 96%
improvements are highlighted in the “Electrical Specifications” • Improved Minimum Open Circuit Voltage Conversion
section on page 3. Critical parameters are guaranteed over Efficiency of 99%
the entire commercial, industrial and military temperature • Improved SCR Latchup Protection
ranges. • Simple Conversion of +5V Logic Supply to ±5V Supplies
The ICL7660S performs supply voltage conversion from • Simple Voltage Multiplication VOUT = (-)nVIN
positive to negative for an input range of 1.5V to 12V, • Easy to Use - Requires Only 2 External Non-Critical
resulting in complementary output voltages of -1.5V to -12V. Passive Components
Only 2 non-critical external capacitors are needed for the • Improved Direct Replacement for Industry Standard
charge pump and charge reservoir functions. The ICL7660S ICL7660 and Other Second Source Devices
can be connected to function as a voltage doubler and will • Pb-Free Available (RoHS Compliant)
generate up to 22.8V with a 12V input. It can also be used as
a voltage multiplier or voltage divider. Applications
The chip contains a series DC power supply regulator, RC • Simple Conversion of +5V to ±5V Supplies
oscillator, voltage level translator, and four output power • Voltage Multiplication VOUT = ±nVIN
MOS switches. The oscillator, when unloaded, oscillates at a
• Negative Supplies for Data Acquisition Systems and
nominal frequency of 10kHz for an input supply voltage of Instrumentation
5.0V. This frequency can be lowered by the addition of an
• RS232 Power Supplies
external capacitor to the “OSC” terminal, or the oscillator
may be over-driven by an external clock. • Supply Splitter, VOUT = ±VS/2

The “LV” terminal may be tied to GND to bypass the internal

series regulator and improve low voltage (LV) operation. At
medium to high voltages (3.5V to 12V), the LV pin is left
floating to prevent device latchup.

Pinout
ICL7660S
(8 LD PDIP, SOIC)
TOP VIEW

BOOST 1 8 V+

CAP+ 2 7 OSC

GND 3 6 LV

CAP- 4 5 VOUT

1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2004, 2005, 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
 ICL7660S

Ordering Information
TEMP. RANGE
PART NUMBER PART MARKING (°C) PACKAGE PKG. DWG. #
ICL7660SCBA 7660 SCBA 0 to +70 8 Ld SOIC M8.15
ICL7660SCBA-T 7660 SCBA 0 to +70 8 Ld SOIC Tape and Reel M8.15
(Note 3)
ICL7660SCBAZ 7660 SCBAZ 0 to +70 8 Ld SOIC M8.15
(Note 1) (Pb-free)
ICL7660SCBAZ-T 7660 SCBAZ 0 to +70 8 Ld SOIC Tape and Reel M8.15
(Notes 1, 3) (Pb-free)
ICL7660SCPA 7660S CPA 0 to +70 8 Ld PDIP E8.3
ICL7660SCPAZ 7660S CPAZ 0 to +70 8 Ld PDIP* E8.3
(Note 1) (Pb-free)
ICL7660SIBA 7660 SIBA -40 to +85 8 Ld SOIC M8.15
ICL7660SIBAT 7660 SIBA -40 to +85 8 Ld SOIC Tape and Reel M8.15
(Note 3)
ICL7660SIBAZ 7660 SIBAZ -40 to +85 8 Ld SOIC M8.15
(Note 1) (Pb-free)
ICL7660SIBAZT 7660 SIBAZ -40 to +85 8 Ld SOIC Tape and Reel M8.15
(Notes 1, 3) (Pb-free)
ICL7660SIPA 7660 SIPA -40 to +85 8 Ld PDIP E8.3
ICL7660SIPAZ 7660S IPAZ -40 to +85 8 Ld PDIP* E8.3
(Note 1) (Pb-free)
*Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
NOTES:
1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100%
matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering
operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
2. Add /883B to part number if 883B processing is required.
3. Please refer to TB347 for details on reel specifications.

2 FN3179.5
March 6, 2008
 ICL7660S

Absolute Maximum Ratings Thermal Information

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +13.0V Thermal Resistance (Typical, Note 5) θJA (°C/W)
LV and OSC Input Voltage (Note 4) 8 Ld PDIP* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
V+ < 5.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to V+ + 0.3V 8 Ld Plastic SOIC. . . . . . . . . . . . . . . . . . . . . . . . . . . 160
V+ > 5.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . V+ -5.5V to V+ +0.3V Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
Current into LV (Note 4) http://www.intersil.com/pbfree/Pb-FreeReflow.asp
V+ > 3.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20μA
Output Short Duration *Pb-free PDIPs can be used for through hole wave solder
VSUPPLY ≤ 5.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous processing only. They are not intended for use in Reflow solder
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C processing. applications.

Operating Conditions
Temperature Range
ICL7660SI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
ICL7660SC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.

NOTES:
4. Connecting any terminal to voltages greater than V+ or less than GND may cause destructive latchup. It is recommended that no inputs from
sources operating from external supplies be applied prior to “power up” of ICL7660S.
5. θJA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications V+ = 5V, TA = +25°C, OSC = Free running, Test Circuit Figure 12, Unless Otherwise Specified.

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Supply Current (Note 8) I+ RL = ∞ , +25°C - 80 160 µA

0°C < TA < +70°C - - 180 µA

-40°C < TA < +85°C - - 180 µA

-55°C < TA < +125°C - - 200 µA

Supply Voltage Range - High V+H RL = 10k, LV Open, TMIN < TA < TMAX 3.0 - 12 V
(Note 9)

Supply Voltage Range - Low V+L RL = 10k, LV to GND, TMIN < TA < TMAX 1.5 - 3.5 V

Output Source Resistance ROUT IOUT = 20mA - 60 100 Ω

IOUT = 20mA, 0°C < TA < +70°C - - 120 Ω

IOUT = 20mA, -25°C < TA < +85°C - - 120 Ω

IOUT = 20mA, -55°C < TA < +125°C - - 150 Ω

IOUT = 3mA, V+ = 2V, LV = GND, - - 250 Ω

0°C < TA < +70°C

IOUT = 3mA, V+ = 2V, LV = GND, - - 300 Ω

-40°C < TA < +85°C

IOUT = 3mA, V+ = 2V, LV = GND, - - 400 Ω

-55°C < TA < +125°C

Oscillator Frequency (Note 7) fOSC COSC = 0, Pin 1 Open or GND 5 10 - kHz

COSC = 0, Pin 1 = V+ - 35 - kHz

Power Efficiency PEFF RL = 5kΩ 96 98 - %

TMIN < TA < TMAX RL = 5kΩ 95 97 - -

Voltage Conversion Efficiency VOUTEFF RL = ∞ 99 99.9 - %

3 FN3179.5
March 6, 2008
 ICL7660S

Electrical Specifications V+ = 5V, TA = +25°C, OSC = Free running, Test Circuit Figure 12, Unless Otherwise Specified. (Continued)

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Oscillator Impedance ZOSC V+ = 2V - 1 - MΩ

V+ = 5V - 100 - kΩ

NOTES:
6. Derate linearly above +50°C by 5.5mW/°C
7. In the test circuit, there is no external capacitor applied to pin 7. However, when the device is plugged into a test socket, there is usually a very
small but finite stray capacitance present, of the order of 5pF.
8. The Intersil ICL7660S can operate without an external diode over the full temperature and voltage range. This device will function in existing
designs which incorporate an external diode with no degradation in overall circuit performance.
9. All significant improvements over the industry standard ICL7660 are highlighted.

Typical Performance Curves (Test Circuit Figure 12)

12 250

OUTPUT SOURCE RESISTANCE (W)

TA = +125°C
10
200
SUPPLY VOLTAGE (V)

8 TA = +25°C
SUPPLY VOLTAGE RANGE
150
(NO DIODE REQUIRED)
6 TA = -55°C

100
4

2 50

0
0
-55 -25 0 25 50 100 125 0 2 4 6 8 10 12

TEMPERATURE (°C) SUPPLY VOLTAGE (V)

FIGURE 1. OPERATING VOLTAGE AS A FIGURE 2. OUTPUT SOURCE RESISTANCE AS A

FUNCTION OF TEMPERATURE FUNCTION OF SUPPLY VOLTAGE

350 98
POWER CONVERSION EFFICIENCY (%)
OUTPUT SOURCE RESISTANCE (Ω)

96 V+ = 5V
300
94 TA = +25°C
250 IOUT = 1mA
IOUT = 3mA, 92
200 IOUT = 20mA, V+ = 2V 90
V+ = 5V
150 88
IOUT = 20mA,
V+ = 5V 86
100
84
50 82
IOUT = 20mA,
V+ = 12V 80
0
-50 -25 0 25 50 75 100 125 100 1k 10k 50k
TEMPERATURE (°C) OSC FREQUENCY fOSC (Hz)

FIGURE 3. OUTPUT SOURCE RESISTANCE AS A FIGURE 4. POWER CONVERSION EFFICIENCY AS A

FUNCTION OF TEMPERATURE FUNCTION OF OSCILLATOR FREQUENCY

4 FN3179.5
March 6, 2008
 ICL7660S

Typical Performance Curves (Test Circuit Figure 12) (Continued)

10 20
V+ = 5V

OSCILLATOR FREQUENCY fOSC (kHz)

OSCILLATOR FREQUENCY fOSC (kHz)

9
TA = +25°C 18
8

7 16
6
14
5
V+ = 10V
4 12
3
10
2
V+ = 5V
1 8
0
1 10 100 1k -55 -25 0 25 50 75 100 125
COSC (pF) TEMPERATURE (°C)

FIGURE 5. FREQUENCY OF OSCILLATION AS A FUNCTION FIGURE 6. UNLOADED OSCILLATOR FREQUENCY AS A

OF EXTERNAL OSCILLATOR CAPACITANCE FUNCTION OF TEMPERATURE

1 100 100

POWER CONVERSION EFFICIENCY (%)

V+ = 5V
90 90
0 TA = +25°C
80 80

SUPPLY CURRENT (mA)

OUTPUT VOLTAGE (V)

-1 70 70

60 60
-2 50 50

40 40
-3
30 30

20 V+ = 5V 20
-4
10 TA = +25°C 10

-5 0 0
0 10 20 30 40 0 10 20 30 40 50 60
LOAD CURRENT (mA) LOAD CURRENT (mA)

FIGURE 7. OUTPUT VOLTAGE AS A FUNCTION FIGURE 8. SUPPLY CURRENT AND POWER CONVERSION
OF OUTPUT CURRENT EFFICIENCY AS A FUNCTION OF LOAD
CURRENT

2 100
V+ = 2V 90
TA = +25°C
SUPPLY CURRENT (mA) (NOTE 9)
80 16
1
POWER CONVERSION
OUTPUT VOLTAGE (V)

70 14
EFFICIENCY (%)

60 12

0 50 10
40 8
30 6
-1 V+ = 2V
20 4
TA = +25°C
10 2
-2 0 0
0 1 2 3 4 5 6 7 8 9 0 1.5 3.0 4.5 6.0 7.5 9.0
LOAD CURRENT (mA) LOAD CURRENT (mA)

FIGURE 9. OUTPUT VOLTAGE AS A FUNCTION OF OUTPUT FIGURE 10. SUPPLY CURRENT AND POWER CONVERSION
CURRENT EFFICIENCY AS A FUNCTION OF LOAD CURRENT

5 FN3179.5
March 6, 2008
 ICL7660S

Typical Performance Curves (Test Circuit Figure 12) (Continued)

V+ = 5V
C1 = C2 = 1mF
TA = +25°C
400 I = 10mA

OUTPUT RESISTANCE (Ω)

C1 = C2 = 10mF
300

C1 = C2 = 100mF
200

100

100 1k 10k 100k

OSCILLATOR FREQUENCY (Hz)

FIGURE 11. OUTPUT SOURCE RESISTANCE AS A FUNCTION OF OSCILLATOR FREQUENCY

NOTE:
10. These curves include in the supply current that current fed directly into the load RL from the V+ (See Figure 12). Thus, approximately half the
supply current goes directly to the positive side of the load, and the other half, through the ICL7660S, to the negative side of the load. Ideally,
VOUT ∼ 2VIN, IS ∼ 2IL, so VIN x IS ∼ VOUT x IL.

Detailed Description approach is that in integrating the switches, the substrates of

S3 and S4 must always remain reverse biased with respect
The ICL7660S contains all the necessary circuitry to
to their sources, but not so much as to degrade their “ON”
complete a negative voltage converter, with the exception of
resistances. In addition, at circuit start-up, and under output
2 external capacitors which may be inexpensive 10µF
short circuit conditions (VOUT = V+), the output voltage must
polarized electrolytic types. The mode of operation of the
be sensed and the substrate bias adjusted accordingly.
device may be best understood by considering Figure 12,
Failure to accomplish this would result in high power losses
which shows an idealized negative voltage converter.
and probable device latch-up.
Capacitor C1 is charged to a voltage, V+, for the half cycle
when switches S1 and S3 are closed. (Note: Switches S2 This problem is eliminated in the ICL7660S by a logic network
and S4 are open during this half cycle). During the second which senses the output voltage (VOUT) together with the
half cycle of operation, switches S2 and S4 are closed, with level translators, and switches the substrates of S3 and S4 to
S1 and S3 open, thereby shifting capacitor C1 to C2 such the correct level to maintain necessary reverse bias.
that the voltage on C2 is exactly V+, assuming ideal switches
The voltage regulator portion of the ICL7660S is an integral
and no load on C2. The ICL7660S approaches this ideal
part of the anti-latchup circuitry, however its inherent voltage
situation more closely than existing non-mechanical circuits.
drop can degrade operation at low voltages. Therefore, to
V+ improve low voltage operation “LV” pin should be connected
IS V+ to GND, disabling the regulator. For supply voltages greater
1 8 (+5V)
than 3.5V the LV terminal must be left open to insure latchup
2 7 IL
ICL7660S proof operation, and prevent device damage.
C1 +
3 6 RL
10µF -
Theoretical Power Efficiency
4 5 -VOUT
Considerations
C2 - In theory, a voltage converter can approach 100% efficiency
10µF + if certain conditions are met:

1. The drive circuitry consumes minimal power.

NOTE: For large values of COSC (>1000pF) the values of C1 and C2 2. The output switches have extremely low ON resistance
should be increased to 100µF.
and virtually no offset.
FIGURE 12. ICL7660S TEST CIRCUIT
3. The impedance of the pump and reservoir capacitors are
negligible at the pump frequency.
In the ICL7660S, the 4 switches of Figure 13 are MOS
power switches; S1 is a P-Channel devices and S2, S3 and
S4 are N-Channel devices. The main difficulty with this

6 FN3179.5
March 6, 2008
 ICL7660S

The ICL7660S approaches these conditions for negative Typical Applications

voltage conversion if large values of C1 and C2 are used.
ENERGY IS LOST ONLY IN THE TRANSFER OF CHARGE Simple Negative Voltage Converter
BETWEEN CAPACITORS IF A CHANGE IN VOLTAGE The majority of applications will undoubtedly utilize the
OCCURS. The energy lost is defined by: ICL7660S for generation of negative supply voltages.
1 Figure 14 shows typical connections to provide a negative
E = --- C 1 ( V 1 2 – V 2 2 ) (EQ. 1)
2 supply where a positive supply of +1.5V to +12V is available.
Keep in mind that pin 6 (LV) is tied to the supply negative
where V1 and V2 are the voltages on C1 during the pump (GND) for supply voltage below 3.5V.
and transfer cycles. If the impedances of C1 and C2 are
relatively high at the pump frequency (refer to Figure 13) V+
compared to the value of RL, there will be substantial
difference in the voltages V1 and V2. Therefore it is not only 1 8
desirable to make C2 as large as possible to eliminate output 10µF
2 7
voltage ripple, but also to employ a correspondingly large ICL7660S
+
3 6
value for C1 in order to achieve maximum efficiency of - RO VOUT
operation. 4 5
-
- V+
VOUT = -V+
8 S1 2 S2 10µF + +
VIN

14A. 14B.
C1
3 3
FIGURE 14. SIMPLE NEGATIVE CONVERTER AND ITS
OUTPUT EQUIVALENT
C2
The output characteristics of the circuit in Figure 14 can be
S3 S4 5
approximated by an ideal voltage source in series with a
4 VOUT = -VIN resistance as shown in Figure 14B. The voltage source has
a value of -(V+). The output impedance (RO) is a function of
the ON resistance of the internal MOS switches (shown in
7
Figure 13), the switching frequency, the value of C1 and C2,
FIGURE 13. IDEALIZED NEGATIVE VOLTAGE CONVERTER and the ESR (equivalent series resistance) of C1 and C2. A
good first order approximation for RO is:

Do’s and Don’ts R 0 ≅ 2 ( ( R SW1 + R SW3 + ESRC1 ) + 2 ( R SW2 + R SW4 + ESR C1 ) +

1. Do not exceed maximum supply voltages. 1
-------------------------------- + ESR C2
f PUMP × C 1
2. Do not connect LV terminal to GND for supply voltage
greater than 3.5V. f OSC
f PUMP = -------------- ( R SWX = MOSFET Switch Resistance )
3. Do not short circuit the output to V+ supply for supply 2
(EQ. 2)
voltages above 5.5V for extended periods, however,
transient conditions including start-up are okay. Combining the four RSWX terms as RSW, we see that:
4. When using polarized capacitors, the + terminal of C1 1
R 0 ≅ 2xR SW + -------------------------------- + 4xESR C1 + ESR C2 (EQ. 3)
must be connected to pin 2 of the ICL7660S and the + f PUMP × C 1
terminal of C2 must be connected to GND.
5. If the voltage supply driving the ICL7660S has a large RSW, the total switch resistance, is a function of supply
source impedance (25Ω to 30Ω), then a 2.2μF capacitor voltage and temperature (See the Output Source Resistance
from pin 8 to ground may be required to limit rate of rise graphs), typically 23Ω at +25°C and 5V. Careful selection of
of input voltage to less than 2V/µs. C1 and C2 will reduce the remaining terms, minimizing the
6. User should insure that the output (pin 5) does not go output impedance. High value capacitors will reduce the
more positive than GND (pin 3). Device latch up will occur 1/(fPUMP x C1) component, and low ESR capacitors will lower
under these conditions. A 1N914 or similar diode placed the ESR term. Increasing the oscillator frequency will reduce
in parallel with C2 will prevent the device from latching up the 1/(fPUMP x C1) term, but may have the side effect of a net
under these conditions. (Anode pin 5, Cathode pin 3). increase in output impedance when C1 > 10µF and is not long
enough to fully charge the capacitors every cycle. In a typical
application where fOSC = 10kHz and C = C1 = C2 = 10µF:

7 FN3179.5
March 6, 2008
 ICL7660S

1
Changing the ICL7660S Oscillator Frequency
R 0 ≅ 2x23 + --------------------------------------------------- + 4xESR C1 + ESR C2 (EQ. 4)
5 × 10 × 10 × 10
3 –6 It may be desirable in some applications, due to noise or other
considerations, to alter the oscillator frequency. This can be
R 0 ≅ 46 + 20 + 5 × ESR C achieved simply by one of several methods described in the
Since the ESRs of the capacitors are reflected in the output following.
impedance multiplied by a factor of 5, a high value could
By connecting the Boost Pin (Pin 1) to V+, the oscillator
potentially swamp out a low 1/fPUMP x C1) term, rendering
charge and discharge current is increased and, hence, the
an increase in switching frequency or filter capacitance
oscillator frequency is increased by approximately 31/2
ineffective. Typical electrolytic capacitors may have ESRs as
times. The result is a decrease in the output impedance and
high as 10Ω.
ripple. This is of major importance for surface mount
Output Ripple applications where capacitor size and cost are critical.
ESR also affects the ripple voltage seen at the output. The Smaller capacitors, e.g. 0.1µF, can be used in conjunction
total ripple is determined by 2 voltages, A and B, as shown in with the Boost Pin in order to achieve similar output currents
Figure 15. Segment A is the voltage drop across the ESR of compared to the device free running with C1 = C2 = 10µF or
C2 at the instant it goes from being charged by C1 (current 100µF. (Refer to graph of Output Source Resistance as a
flowing into C2) to being discharged through the load Function of Oscillator Frequency).
(current flowing out of C2). The magnitude of this current Increasing the oscillator frequency can also be achieved by
change is 2 x IOUT, hence the total drop is 2 x IOUT x overdriving the oscillator from an external clock, as shown in
ESRC2V. Segment B is the voltage change across C2 during Figure 18. In order to prevent device latchup, a 1kΩ resistor
time t2, the half of the cycle when C2 supplies current the must be used in series with the clock output. In a situation
load. The drop at B is IOUT x t2/C2V. The peak-to-peak ripple where the designer has generated the external clock
voltage is the sum of these voltage drops: frequency using TTL logic, the addition of a 10kΩ pull-up
V RIPPLE ≅ ⎛ ----------------------------------------- + 2ESR C2 × I OUT⎞
1 resistor to V+ supply is required. Note that the pump
⎝2 × f ⎠ (EQ. 5)
PUMP × C 2 frequency with external clocking, as with internal clocking,
will be 1/2 of the clock frequency. Output transitions occur on
Again, a low ESR capacitor will result in a higher
the positive going edge of the clock.
performance output.

Paralleling Devices V+ V+
Any number of ICL7660S voltage converters may be
paralleled to reduce output resistance. The reservoir 1 8
1kΩ
capacitor, C2, serves all devices while each device requires 2 7
CMOS
ICL7660S GATE
its own pump capacitor, C1. The resultant output resistance +
10µF 3 6
would be approximately: -
R OUT ( of ICL7660S ) 4 5 VOUT
R OUT = --------------------------------------------------------- (EQ. 6) -
n ( number of devices ) +
10µF

Cascading Devices
FIGURE 15. EXTERNAL CLOCKING
The ICL7660S may be cascaded as shown to produce larger
negative multiplication of the initial supply voltage. However,
It is also possible to increase the conversion efficiency of the
due to the finite efficiency of each device, the practical limit is
ICL7660S at low load levels by lowering the oscillator
10 devices for light loads. The output voltage is defined by:
frequency. This reduces the switching losses, and is shown
V OUT = – n ( V IN ) (EQ. 7) in Figure 19. However, lowering the oscillator frequency will
cause an undesirable increase in the impedance of the
pump (C1) and reservoir (C2) capacitors; this is overcome by
where n is an integer representing the number of devices
increasing the values of C1 and C2 by the same factor that
cascaded. The resulting output resistance would be
the frequency has been reduced. For example, the addition
approximately the weighted sum of the individual ICL7660S
of a 100pF capacitor between pin 7 (OSC and V+ will lower
ROUT values.
the oscillator frequency to 1kHz from its nominal frequency
of 10kHz (a multiple of 10), and thereby necessitate
corresponding increase in the value of C1 and C2 (from
10µF to 100µF).

8 FN3179.5
March 6, 2008
 ICL7660S

V+ V+

1 8 VOUT = -VIN
1 8
COSC 2 7 -
2 7 ICL7660S D1 C3
ICL7660S + +
+ C1 3 6
C1 3 6 -
-
4 5
4 5 VOUT
- D2
C2 - + VOUT = (2V+) -
+
(VFD1) - (VFD2)
C2 +
C
FIGURE 16. LOWERING OSCILLATOR FREQUENCY - 4

Positive Voltage Doubling

FIGURE 18. COMBINED NEGATIVE VOLTAGE CONVERTER
The ICL7660S may be employed to achieve positive voltage AND POSITIVE DOUBLER
doubling using the circuit shown in Figure 20. In this
application, the pump inverter switches of the ICL7660S are
Voltage Splitting
used to charge C1 to a voltage level of V+ -VF (where V+ is
The bidirectional characteristics can also be used to split a
the supply voltage and VF is the forward voltage on C1 plus
high supply in half, as shown in Figure 22. The combined
the supply voltage (V+) is applied through diode D2 to
load will be evenly shared between the two sides, and a high
capacitor C2. The voltage thus created on C2 becomes
value resistor to the LV pin ensures start-up. Because the
(2V+) - (2VF) or twice the supply voltage minus the
switches share the load in parallel, the output impedance is
combined forward voltage drops of diodes D1 and D2.
much lower than in the standard circuits, and higher currents
The source impedance of the output (VOUT) will depend on can be drawn from the device. By using this circuit, and then
the output current, but for V+ = 5V and an output current of the circuit of Figure 17, +15V can be converted (via +7.5,
10mA it will be approximately 60Ω. and -7.5 to a nominal -15V, although with rather high series
output resistance (∼250Ω).
V+

1 8 V+
+
2 7 D1 RL1 50µF
ICL7660S -
3 6 D2 VOUT = 1 8
(2V+) - (2VF) VOUT = V+ - V-
4 5 + 2 7
2 ICL7660S
C2 +
+
C1
- 50µF
-
3 6
- RL2 4 5
+
50µF
-
NOTE: D1 and D2 can be any suitable diode. V-
FIGURE 17. POSITIVE VOLTAGE DOUBLER
FIGURE 19. SPLITTING A SUPPLY IN HALF
Combined Negative Voltage Conversion and
Positive Supply Doubling Regulated Negative Voltage Supply
Figure 21 combines the functions shown in Figure 14 and
In some cases, the output impedance of the ICL7660S can
Figure 20 to provide negative voltage conversion and
be a problem, particularly if the load current varies
positive voltage doubling simultaneously. This approach
substantially. The circuit of Figure 23 can be used to
would be, for example, suitable for generating +9V and -5V
overcome this by controlling the input voltage, via an
from an existing +5V supply. In this instance capacitors C1
ICL7611 low-power CMOS op amp, in such a way as to
and C3 perform the pump and reservoir functions
maintain a nearly constant output voltage. Direct feedback is
respectively for the generation of the negative voltage, while
inadvisable, since the ICL7660S’s output does not respond
capacitors C2 and C4 are pump and reservoir respectively
instantaneously to change in input, but only after the
for the doubled positive voltage. There is a penalty in this
switching delay. The circuit shown supplies enough delay to
configuration which combines both functions, however, in
accommodate the ICL7660S, while maintaining adequate
that the source impedances of the generated supplies will be
feedback. An increase in pump and storage capacitors is
somewhat higher due to the finite impedance of the common
desirable, and the values shown provides an output
charge pump driver at pin 2 of the device.
impedance of less than 5Ω to a load of 10mA.

9 FN3179.5
March 6, 2008
 ICL7660S

+8V 50k

56k -
+8V 10µF
100Ω +
50k
-
100k ICL7611
+
1 8

2 7
ICL7660S
ICL8069 +
100µF 3 6
-
4 5 VOUT

800k -
250k 100µF
VOLTAGE +
ADJUST

FIGURE 20. REGULATING THE OUTPUT VOLTAGE

+5V LOGIC SUPPLY

12 11

TTL DATA 16 1
INPUT
4 3 RS232 +5V
DATA
15 OUTPUT -5V
1 8

2 7 IH5142
ICL7660S
+ 13
10µF 3 6 14
-
4 5

10µF
-
+

FIGURE 21. RS232 LEVELS FROM A SINGLE 5V SUPPLY

Other Applications
Further information on the operation and use of the
ICL7660S may be found in AN051 “Principles and
Applications of the ICL7660 CMOS Voltage Converter”.

10 FN3179.5
March 6, 2008
 ICL7660S

Dual-In-Line Plastic Packages (PDIP)

N
E8.3 (JEDEC MS-001-BA ISSUE D)
8 LEAD DUAL-IN-LINE PLASTIC PACKAGE
E1
INDEX INCHES MILLIMETERS
AREA 1 2 3 N/2
SYMBOL MIN MAX MIN MAX NOTES
-B-
A - 0.210 - 5.33 4
-A-
D E A1 0.015 - 0.39 - 4
BASE A2 0.115 0.195 2.93 4.95 -
PLANE A2
-C- A
SEATING
B 0.014 0.022 0.356 0.558 -
PLANE L C B1 0.045 0.070 1.15 1.77 8, 10
L
D1 A1 eA C 0.008 0.014 0.204 0.355 -
D1
B1 e D 0.355 0.400 9.01 10.16 5
eC C
B
eB D1 0.005 - 0.13 - 5
0.010 (0.25) M C A B S
E 0.300 0.325 7.62 8.25 6
NOTES: E1 0.240 0.280 6.10 7.11 5
1. Controlling Dimensions: INCH. In case of conflict between
e 0.100 BSC 2.54 BSC -
English and Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982. eA 0.300 BSC 7.62 BSC 6
3. Symbols are defined in the “MO Series Symbol List” in Section eB - 0.430 - 10.92 7
2.2 of Publication No. 95. L 0.115 0.150 2.93 3.81 4
4. Dimensions A, A1 and L are measured with the package seated
N 8 8 9
in JEDEC seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mold flash or protru- Rev. 0 12/93
sions. Mold flash or protrusions shall not exceed 0.010 inch
(0.25mm).
6. E and eA are measured with the leads constrained to be per-
pendicular to datum -C- .
7. eB and eC are measured at the lead tips with the leads uncon-
strained. eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions.
Dambar protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3,
E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch
(0.76 - 1.14mm).

11 FN3179.5
March 6, 2008
 ICL7660S

Small Outline Plastic Packages (SOIC)

N
M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
H 0.25(0.010) M B M
AREA INCHES MILLIMETERS
E
SYMBOL MIN MAX MIN MAX NOTES
-B-
A 0.0532 0.0688 1.35 1.75 -

1 2 3 A1 0.0040 0.0098 0.10 0.25 -

L
B 0.013 0.020 0.33 0.51 9
SEATING PLANE C 0.0075 0.0098 0.19 0.25 -
-A-
A h x 45°
D 0.1890 0.1968 4.80 5.00 3
D
E 0.1497 0.1574 3.80 4.00 4
-C- e 0.050 BSC 1.27 BSC -
α
H 0.2284 0.2440 5.80 6.20 -
e A1
C h 0.0099 0.0196 0.25 0.50 5
B 0.10(0.004)
L 0.016 0.050 0.40 1.27 6
0.25(0.010) M C A M B S
N 8 8 7
NOTES: α 0° 8° 0° 8° -
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Rev. 1 6/05
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.

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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
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12 FN3179.5
March 6, 2008