1. In your design you have dual port memories each working at a different frequency.

What is the clock

frequency you use for testing (MBIST)?
Ans: MBIST is frequency independent, I will used the max frequency allow/check by STA (Design team) at
which frequency they close timing.

2. When a failure is detected in parallel testing of memories, how do you know which memory is failing?
Ans: Load BIST_COLLAR_GO into waveform, check which GO went 0/X , Then Check *.etplan file to know
which memory is corresponding failing BIST_COLLAR_GO

3. What are the extra pins needed for BIRA (Built In Repair Analysis) implementation?

4. What could be the possible reasons for scan chain failures during GLS (Gate level Simulation)? Other
than setup issues.
Ans: Difference of model between verilog used by simulator and ATPG tool, seq_udp_delay switch has to
use to proper Q for some flops

5. Did you get any issues during timing simulation of MBIST patterns?
Ans: MBIST_RETIMING_CELL/RETIMG_CELL[0], *NTC*_reg has to be tcheck off during timing simulation

6. What are typical frequencies for scan shift, MBIST tests?

Ans: Scan shift -10 Mhz, MBIST will be design dependent

7. How is it different implementing MBIST logic for ROMs, SRAM, DRAMS, and register files? Can same
controller handle all these? What are the typical issues faced?
Ans: ROM need only to read all address, and accumulate in a CRC. For S/D RAM & R, that is IP-provider
dependent, whose will indicate the bist engine to apply.

8. What are the differences between IJTAG and JTAG standard?

9. What are the differences between Boundary scan and IEEE1500 standards? Other than Boundary scan
is used for board level testing and the IEEE1500 for core based testing.

10. What is the effect of LOS method for testing delay faults on the tester?
11. What are the typical issues you face during timing simulation of scan and MBIST patterns?
12. What are copy and shadow cell? How are they useful?
13. What are the typical clock skew issues you faced during post layout/ timing simulation?
14. How do you implement DFT for a design have lot of Analog blocks? How to improve coverage?
15. How do you test at-speed faults for inter clock domains?
16. Are multi-cycle paths tested in the design?
17. Why do you need multiple-load patterns? What are its advantages over basic scan patterns?
18. What are the typical steps to improve coverage when our coverage target is not achieved?
19. Steps to fix broken scan chain issues during ATPG? Step by step procedure to find the issue?
20. What is sequential depth?
21. How to specify clocks for at-speed testing in encounter test or any other tool? What is the syntax?
22. In SDF we have 3 values best, typical and worst case? Best is for good processor, less temp , high vol
and worst is reverse. What is typical?
23. What is split capture?
24. What Is the most challenging issue you faced? How you fixed it?

8- IJTAG is to manage multiple JTAG in a SOC.

9- ?
10- ?
11- see 4
12- ?
13- no issue with skew.
14- add feed-back, and need to control the analog input pins from digital core.
15- try to have only one clock domain during scan.
16- no.
17- to improve coverage.
18- analyze which sub-block has a low coverage, generaly add feed-back in scan mode, or test point.
19- check the scan mode is properly enable, the reset is stable state during shift, and the clock is visible
by all scan element during the shift.
20- 
21- no idea.
22- typical is power estimation.
23- transition fault capture.

 Probable Interview Questions for DFT Engineer position at Nvidia & Intel
1) What is the DFT process for an ASIC?

2) What factors that affect scan chains?

3) What is the purpose of DFT?

4) What are the major cost factors of DFT and what do you do to lower costs?

5) What are the errors/problems that occur during the DFT process and how do you resolve them?

6) What tests do people use for DFT and what are their purpose?

7) How do clock domains affect DFT and how to you handle them?

8) Given a small circuit (see diagram) how would you generate tests for it?

Chain test vectors are supposed to have vectors like 00110011. Why?
Well, 00110011 is useful for checking all the possible transition ensuring the flops are working fine but my question is,
why is it necessary to check the 0->0 transition or 1->1 transition? We can instead use the pattern 01010101 pattern
to see if the flops are toggling or not and that should be enough.
This is one question that I ask in my interviews :) Assume that you have just a flop. How will you test it? You will have to
apply 0011(0) or 0110(0) or 1100(1) or 1001(1), because only then it will cover 0->0, 1->1 (flop is able to retain the same
value), 0->1 and 1->0 (flop is able to toggle). This has got nothing to do with test power. You cant test a scan chain (or
shift register) in any other way.

Tell me somthing about your past project and work.

Explain DRC violation during scan insertion. 
Explain DRC violation during ATPG pattern generation.
What are steps we need to improve coverage of our design?
How you will debugge the chain simulation failure ?
How you debugge the EDT scan serial patterns failure ?
What the things we required before scan insertion.
Explain scan insertion DRC violation and step to fix it.
Explain EDT . Why we use it.
Why we use pipelining  logic ?
Explain SA and TFT fault.
what is SDF ? 
Explain LOC and LOS? Which one you used in your project and why?
Explain MBIST structure.
How we do memory grouping?
How many MBIST controller in your project and what logic you implemented to enable them.
Any problem you faced in MBIST generation and patterns simulation phase.
Bounday scan concept and issue face during bscan simulation.

If some black box present in your scan path OR inserted by tool, how you will debugge.

Can you explain some switches which you used in simulation run file like :
-novopt, +delay_mode_zero +nospecify
+notimingchecks +delay_mode_zero   etc...

force deposite and force freze.

1) How to test memory ?

2)How to take care memories during scan insertion?
3)How to test memories which are in IPs?
4) How to debug scan integrity patter failure?
5) If my 1st flop of scan chain is failing then how you will debug?
6) What is diagnostic  test for  scan integrity patter failure?
7)How to improve coverage? 
8) How to detect AU faults?
9)What is sequential depth?
10)If i have 2 blocks and i am doing stuck at in timing violation and that path is not timing closed then it will hit
violation ? which violation?
11)Which frequency you used to test memories , fast or slow(shift)?
12)What is the structure of EDT?
13)Why we use masking logic?
14)How we can come to know which chain we have to mask?
15)Which library you used for simulations?
16)How to decide algorithms in MBIST? 
17) How to decide numbers of controllers?
18)What types of faults will come on silicon?

1) Simulation

1. Have you done simulations? What and all you need to do a simulation?

2. what problems you faced (in non-timing & Timing)? How did you debug?
3. During simulation, why you need to constrain a port?
4. what is the correlation between the constraints that you give in simulation and the constraints those you give
during ATPG, Scan insertion?
5. In Timing simulation, what problems you faced?
6. During timing simulation,apart from setup & hold, did you get any 1/0 mismatch? did you get any x mismatch?
How did you debug?
7. What did you do to solve setup and hold time issues?

2) ATPG

1. What are all needed to do a ATPG?

2. Tell the flow, how will you generate patterns? (from loading netlist, loading libs, etc..)
3. What problems you faced during loading of design for ATPG (any build issues)
4. How did you solve scan chain not traced issue during building of ATPG?
5. what are all the DRC violations you got during ATPG? how you solved that?
6. what are all the constraints you added during ATPG and why you add those?
7. what was you initial coverage? (I said 92%)
8. what is the nominal coverage for SA and TFT?
9. what are all the steps you taken to reach 99% for SA?
10. Did you reduce the redundant faults?
11. what is fault coverage and test coverage?
3) Scan Insertion

1. What is the flow for scan insertion? (loading design, configuring clks., scan config, compressor configs etc.,)
2. How will you choose the scan chain length?
3. How did you manage multiple clock domains to stitch scan chain?
4. why you need to go for compression?
5. what was you compression ratio with DC compiler and with EDT? (I said 21x in DC compiler, and 48x using
edt)
6. why you didn't achive 100x or 200x? what is the problem in increasing compression ratio? Other than x-
propagation and routing issues, what will be the problem in achiving 100x, 200x compression?
7. Why you need lock up cell? Tell how it is connected?
8. Why you need IO wrapper cell? without IO wrapper cell, what will happen withoutIO cells?
9. Draw the IO wrapper cell structure
10. what are the extra ports that you will add from the raw design for scan insertion? 

4) MBIST

1. What is flow for inserting MBIST?

2. How will you select the controller for memories? (controller merging as per clk domain, per frequencies etc.,)
3. Will it be possible to to test different types of memories with same controller?
4. Did you work closely with PD team?
5. Assume, one controller is controlling 100 memories. What are all the problems in doing that?
6. What is called as at-speed memory testing? Explain how it is achieved?
7. How to make a path to propagate faster? (I said I don't know. Buffer will delay, but I don't know how to make it
faster)
8. Explain pipeline flop? (I said I didn't come across pipeline. Then he explained it with 5th & 6th question)

1) What will be the reason if create_patterns is not able to generate patterns ( It is hang) after few days of running 

Question:

During the run_atpg command process, TetraMAX ATPG appears to hang and fails to generate patterns. What causes this
problem?

Answer:

In most cases, this behavior does not occur because TetraMAX ATPG stopped. TetraMAX ATPG is actually still running, but the
ATPG process simply fails to produce any output. TetraMAX ATPG only writes to the log after completing a successful test
generation. If TetraMAX ATPG continues to fail to create a test, the ATPG run will appear to hang. This issue is most likely
caused by a problem with the ATPG run setup or the design, including the following conditons:

 Improper Constraints
 Contention
 Timing Exceptions
 Clocking Issues From OCC

Improper Constraints

If too many constraints are applied to a single ATPG run, TetraMAX ATPG might be unable to generate patterns that satisfy the
constraints. If too many constraints are placed on clocks, pattern generation might fail because the capture clocks cannot pulse.

You can use the following commands to report all of your constraints and make sure they are valid:

report_pi_constraints
report_cell_constraints
report_atpg_constraints
report_clocks -constraints
As a test, remove all constraints that aren't required to pass DRC checks, and try to generate patterns. If TetraMAX ATPG
successfully generates the patterns, investigate each constraint and investigate which one(s) are limiting ATPG.

Contention

If ATPG cannot avoid contention, it cannot generate patterns. If you see a significant number of Z rule violations, contention
issues could cause all your patterns to be rejected. A series of Z7 or Z8 DRC violations significantly impacts ATPG performance.
If Z7 or Z8 violations are not present, Z1, Z2, and Z3 violations also might indicate potential contention issues in the design.

To determine if contention is a problem, try a test ATPG run using minimal contention settings, as in the following example:

set_contention nobus nobidi

set_contention -nocapture -noatpg -verbose

If these contention settings allow pattern generation, investigate the Z rules (i.e., Z1, Z2, etc.) to determine the cause of the
contention. If you have a very large design with Z rule violations, ATPG sometimes requires significant resources in order
to avoid contention. In this case, ATPG might appear to hang. You can also use the set_contention -
noatpg command to disable the ATPG effort without disabling any contention checks. In this case, TetraMAX ATPG discards
all patterns that create contention.

Timing Exceptions

When performing transition delay testing, TetraMAX ATPG typically reads timing exceptions to specify paths that cannot run at
speed and must be masked during ATPG.

If the specified constraints are too broad, they can cause excessive masking and no patterns are generated -- or the test
coverage or pattern count is negatively impacted. To determine if timing exceptions are causing the issues, you should initiate
an ATPG run without using timing exceptions. If SDC exceptions are used, do not read the SDC file (using
the read_sdc command). Similarly, if exceptions from theadd_slow_paths command are used, do not read that exception
file.

If the problems are eliminated by avoiding timing exceptions, you need to investigate the exceptions. For example, SDC timing
exceptions do not support edge-specific exceptions (i.e., -rise_from or -fall_to). However, TetraMAX ATPG considers those
exceptions as -from or -to specifications, which could cause the exception to be applied too broadly. Take, for example, the
following timing exception:

set_false_path -rise_from [get_clocks {clk1}] -fall_to [get_clocks {clk1}]

This exception is interpreted by TetraMAX ATPG as follows:

set_false_path -from [get_clocks {clk1}] -to [get_clocks {clk1}]

Because of this interpretation, all intra-domain paths for the clk1 domain are covered by the timing exception, which might not be
the intention.

Clocking Issues From OCC

When using transition delay ATPG and OCC, you should investigate all internal clocks specified in the run and determine if any
PLL clocking rules are flagged.

The following SolvNet articles address how to debug these issues:

https://solvnet.synopsys.com/retrieve/1549038.html

https://solvnet.synopsys.com/retrieve/1834485.html
General Debug Guidelines:

 Use the set_atpg -merge off command so that TetraMAX ATPG will not merge ATPG runs
 Use the run_atpg command without the -auto option and determine if the results are consistent
 Use the set_atpg -verbose command
 If applicable, turn off multicore ATPG and use only a single core
 Use the analyze_faults command to debug a simple fault on a known scan flip-flop that should be detected

2) How Clock feeding to Data violation effects for pattern generation

3) Difference between parallel and serial pattern ?

   Is it possible to force values on Q pin instead of SI ? 

4) Waht will be the cause or How to debug if serial pattern passes and  parallel pattern fails and vice versa ? 
Parallel patterns stim and measure values on scan cells so they don’t apply masking logic. Failing serial chain test patterns
would mean identifying all the channels which are driving a scan out pin followed by mapping the failing cycle to a scan cell in
each of those channel. The number of scan cells to be monitored here for debug depends upon compression the ratio
5) What will be the pattern generated to test S@0 oat reset and S@1 at scan enable ?