AVR Architecture

and Assembly
Language
Programming
LECTURE# 02

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General Purpose Registers
(GPRs)
CPU registers store data temporarily
We must understand the registers and architecture of
the CPU to successfully program
32 GPRs in AVR (R0 to R31)
CPU directly perform operations on the GPRs
Each GPR is 8-bit wide
Located in the lowest location of memory addresses
(data bus)

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LDI and ADD instruction
In order to understand working of GPRs,
consider the two instructions
◦ LDI instruction
◦ Load 8-bit immediate data to GPR
LDI Rd, K LDI R16, 10 ;load decimal value 10
LDI R16, 0x25 ;load hex 25 in R16
◦ Cannot load value greater than 255 or 0xFF
◦ Value 0x5 is equal to 0x05
◦ Comment in assembly language using semicolon
◦ Cannot load R0 to R15 using LDI
◦ ADD instruction
◦ Add values of two GPRs and store the result in the first
GPR
ADD Rd, Rr ;Rd = Rd + Rr ADD R0, R1 ;R0 = R0 + R1

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The AVR Data Memory
8-bit
The Lowest 32 bytes of data space Data Address
Space R0
◦ is General Purpose Registers (GPRs) $0000 R1
General R2
$0001
. Purpose .
The I/O memory (Registers) are registers with .
.
Registers .
dedicated functions .
(GPRs) R31
◦ Like DDRA, PORTB, PINC etc. $001F I/O Address
$0020 TWBR $00
◦ Each register is 8-bit wide $0021 TWSR $01
. I/O Registers .
◦ ATmega16 has 64 I/O registers .
(SFRs)
.
.
.
◦ May be called Special Function Registers (SFRs) SPH $3E
$005F SREG $3F
◦ AVRs with more I/O ports have more $0060
◦ Called extended I/O memory .
.
. RAM (SRAM)
RAM
◦ Larger storage for data
$0460
◦ Each location is 8-bit wide
◦ Can be accessed with unique address
◦ Amount of RAM varies among AVRs $FFFF

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The AVR Data Memory
ATmega328p
8-bit
The Lowest 32 bytes of data space Data Address
Space R0
◦ is General Purpose Registers (GPRs) $0000 General R1
R2
$0001 Purpose
The I/O memory (Registers) are registers with Registers
dedicated functions $001F (GPRs) R31

◦ Like DDRA, PORTB, PINC etc. $0020 I/O Address

$0021 I/O Registers TWBR $00
◦ Each register is 8-bit wide (SFRs) TWSR $01
$005F
◦ May be called Special Function Registers (SFRs) $0060 SPH
Extended I/O $3E
◦ AVRs with more I/O ports have more Registers
SREG $3F
$00FF
◦ Called extended I/O memory $0100
.
RAM .
. RAM (SRAM)
◦ Larger storage for data Where is
◦ Each location is 8-bit wide EEPROM?
$08FF
◦ Can be accessed with unique address
◦ Amount of RAM varies among AVRs
$FFFF

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EEPROM and Data Space
Each EEPROM location does not have a unique address
◦ In data memory space

The EEPROM is accessed using four register in I/O memory

◦ Address (EEARH, EEARL)
◦ Data (EEDR), and,
◦ Control (EECR) registers

These interfaces are all that is needed to read/write a memory

◦ Although it will be slower, but we don’t frequently read/write EEPROM

EEPROM will be interfaced later in the Lab

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Using The Data Memory
LDS instruction
R0 R1 Loc. $300 Loc. $302
We know how to add and load values in
? ? α β
GPRs
LDS R0, 0x300 α ? α β
We can also copy data between Data LDS R1, 0x302 α β α β
Memory and GPRs ADD R1, R0 α+β β α β

LDS instruction
◦ LoaD direct from data Space
◦ Usage “LDS Rd, K”
◦ Copies one-byte from memory location ‘k’ to GPR
◦ Example, we want to add the numbers
◦ Stored at location 0x300 and 0x302
LDS R0, 0x300
LDS R1, 0x302
ADD R0, R1

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Using The Data Memory
STS instruction
STS instruction
◦ STore direct to data Space)
◦ Usage “STS K, Rr”
◦ Copies one-byte from GPR to memory location ‘k’
◦ Example, we want to store the sum back to RAM
◦ Copy the sum to location $303
LDS and STS can be used to access
LDS R0, 0x300 both I/O memory and RAM.
LDS R1, 0x302
ADD R0, R1 But there is a better way, using
STS 0x303, R0 • IN and OUT instructions

There is no direct way to store an immediate value to RAM

◦ First load in a GPR, then, move to RAM using STS
LDI R0, 36
◦ Do you know how, to store 36 at loc. 0x305? STS 0x302, R1

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Accessing I/O memory
IN and OUT Instruction
IN instruction, usage “IN Rd, A” Data I/O
◦ Copies data from I/O memory location ‘A’ to GPR Memory Memory
Address Address
◦ Where A = 0 to 63 (this is different from data space addresses)
$20 $00
OUT instruction, usage “OUT A, Rr” $21 $01
◦ Copies data from a GPR to I/O memory location ‘A’
. .
◦ Same address range as for IN instruction . .
. .
Why two different set of instructions for I/O memory?
$5F $3F
◦ IN and OUT are 2-byte instructions and executes in one cycle
◦ While, LDS and STS are 4-byte instructions and takes two cycles to execute
◦ IN and OUT can also use Register name as well as I/O memory address
◦ Names like PORTB (which has address $18 in I/O memory) Rewrite using LDS and STS
◦ Some AVRs may not have LDS and STS instruction IN R0, 0x01 LDS R0, 0x21
OUT 0x02, R1 STS 0x22, R1

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Accessing I/O Memory
Address Map

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MOV instruction
MOV instruction is used to copy data among GPRs
◦ Usage “MOV Rd, Rr” ; Rd = Rr (Rr will not change)
◦ Rd and Rr can be any registers
◦ Example MOV “R10, R20” or “MOV R31, R0”

How to load 42 in R0, when LDI only allows loading R16 – R31
LDI R16, 42
MOV R0, R16

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Some Arithmetic Instructions
INC instruction
◦ Increments value stored in a GPR
◦ Usage “INC Rd” ; Rd = Rd + 1
SUB instruction
◦ Subtracts value of one GPR from another
◦ Usage “SUB Rd, Rr” ; Rd = Rd – Rr
DEC instruction Please note
◦ Decrements value stored in a GPR The first register
◦ Usage “DEC Rd”; Rd = Rd – 1 is destination,
COM instruction whose contents
◦ Inverts all bits of a GPR (1’s complement) are changed
◦ Usage “COM Rd”

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Arithmetic Instructions
Summary
a

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The AVR Status Register (Flags)
This register has a specific function
◦ So it is in I/O memory
Unsigned arithmetic operation
◦ C – Set if carry is generated
◦ Z – set if result is 0
Signed arithmetic operation
◦ N – Set if result is negative (D7 bit for signed numbers)
◦ V – overflow occurred
◦ S – N flag may be corrupted due to overflow (give true sign of result)
Other
◦ H – When there is carry from first nibble to second during arithmetic operation
◦ T – Temporary one bit storage
◦ I – When using interrupt, if zero masks all interrupts or if set allows any interrupt

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Status Register and
ADD instruction
ADD 0x38 and 0x2F
◦ Sets H flag

Add 0x88 and 0x93

◦ Set C flag

Add 0x9C and 0x64

◦ Sets C, H and Z flags

Flag bits are used to act upon a result

◦ Conditional branching (like if or while in C)

Not all instructions effects flag

◦ Like MOV, LDS, STS, IN, OUT

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Status Flags
a

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