DEPARTMENT OF ELECTRONICS AND

COMMUNICATION ENGINEERING

Synthesis of Single Precision Floating Point ALU

Assignment (Experiential Learning) Report of

APPLICATION SPECIFIC INTEGRATED

Submitted by:

Nagendra P 1RV21LVS16
Arjumanth Farraj R 1RV21LVS24
ABSTRACT

Memory devices are becoming compact day by day. The computer calculations can be either floating
point or fixed point depending on performance and applications. In finance, remote sensing, Digital
Signal Processors etc needs fast performance. Floating point numbers representation has widespread
dominance over fixed point numbers. Compared to fixed point [1], the floating-point numbers support
a much wider range of values. It is also used in the recognition system of objects [2] with high speed
and in computers which need very high performances. To represent very large or small values, large
range is required as the integer representation is no longer appropriate. These values can be represented
using the IEEE-754 standard based floating point representation. A high speed ASIC implementation
of a floating point arithmetic unit which can perform addition, subtraction, multiplication, division
functions on 32-bit operands that use the IEEE 754-2008 standard. The algorithms are modeled in
Verilog HDL and the RTL code for adder, subtractor, multiplier, are synthesized using Cadence Genus
RTL complier where the design is targeted for 180nm TSMC technology with proper constraints.

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OBJECTIVES OF THE WORK

1. Developing a behavioral Verilog code for a single precision floating point Arithmethic
unit.
2. Understanding the approach required to be taken while designing a floating point unit.
3. To understand the model of a IEE754 single precision floating point unit and how to
go about developing a Verilogcode for its implementation.

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LITERATURE SURVEY

1. The procedure for a floating point multiplier unit for 32-bit single precision proposes the result of
significant multiplication. The drawback is that the multiplier gave less precision because the
implementation did not include rounding operations.The delay and power consumption are reduced
using a floating point unit. A pipelined ALU for floating point numbers was designed and
simulated. It performed the basic arithmetic operations, but couldn’t achieve a high speed.
2. The implementation of double precision floating point numbers [9]. The drawbacks were with
respect to speed. The advantage is the coverage of a large range of values in implementation. A 32
bit unit for floating point and area and speed is calculated for advanced processors [10]. The delay
got reduced by using less hardware. A high speed single precision for floating point numbers and
achieved a 59% optimization in the delay. The implementation of both single and double precision
is done. The paper objective is a comparison between the single and double precision floating point
values with respect to its area and the timings.

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 INTRODUCTION

An arithmetic circuit which performs digital arithmetic operations has many applications in digital
coprocessors, application specific circuits, etc. Because of the advancements in the VLSI
technology, many complex algorithms that appeared impractical to put into practice, have become
easily realizable today with desired performance parameters so that new designs can be incorporated
[2]. The standardized methods to represent floating point numbers have been instituted by the IEEE
754 standard through which the floating point operations can be carried out efficiently with modest
storage requirements,. The three basic components in IEEE 754 standard floating point numbers
are the sign, the exponent, and the mantissa [3]. The sign bit is of 1 bit where 0 refers to positive
number and 1 refers to negative number [3]. The mantissa, also called significand which is of
23bits composes of the fraction and a leading digit which represents the precision bits of the
number
[3] [2]. The exponent with 8 bits represents both positive and negative exponents. A bias of 127 is
added to the exponent to get the stored exponent [2]. Table 1 show the bit ranges for single (32-
bit) and double (64-bit) precision floating-point values [2]. A floating point number representation
is shown in table 2 The value of binary floating point representation is as follows where S is sign
bit, F is fraction bit and E is exponent field.

Value of a floating point number= (-1)S x val (F) x 2val(E)

TABLE 1 BIT RANGE FOR SINGLE (32-BIT) AND DOUBLE (64-BIT) PRECISION
FLOATING-POINT VALUES

Sign Exponent Fraction Bias

TABLE 2 FLOATING POINT NUMBER REPRESENTATION

32 bits
sign exponent mantissa
1 bit 8 bits 23 bits

There are four types of exceptions that arise during floating point operations. The Overflow
exception is raised whenever the result cannot be represented as a finite value in the precision
format of the destination [13]. The Underflow exception occurs when an intermediate result is too
small to be calculated accurately, or if the operation's result rounded to the destination precision
is too small to be normalized [13] The Division by zero exception arises when a finite nonzero
number is divided by zero [13]. The Invalid operation exception is raised if the given operands
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are invalid for the operation to be performed [13]. In this paper, ASIC implementation of a high
speed FPU has been carried out using efficient addition, subtraction, multiplication algorithms.

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Methodology

This section discusses about the architecture and different considerations for the Floating Point Unit
design.
The FPU of a single precision floating point unit that performs add, subtract, multiply, divide
functions is shown in figure 1 [1]. Two pre-normalization units for addition/subtraction and
multiplication/division operations has been given [1]. Post normalization unit also has been given
that normalizes the mantissa part [2]. The final result can be obtained after post- normalization. To
carry out the arithmetic operations, two IEEE- 754 format single precision operands are considered.
Pre- normalization of the operands is done. Then the selected operation is performed followed by
post-normalizing the output obtained. Finally the exceptions occurred are detected and handled
using exceptional handling.

Figure 1 : Flowchart for Addition/ Subtraction

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 Figure 2 : Flowchart for multiplication

Addition / Subtraction:
There are two possibilities that may occur while computing two 32bit floating-point numbers.
1. If both the operands are having the same sign, their MSB bit could be either ‘1’ or ‘0’ (positive
or negative).
2. When both operands are of different signs, that is MSB of one operand is ‘1’ is positive and
the MSB of the other is ‘0’ which is negative.
3. We have to check the sign of two numbers. If the sign of both numbers are different, then
perform two’s complement for the MSB having ‘1’. Later addition operation to be performed
on both numbers. Algorithm is shown in figure 1.

Multiplication:
1. First step is to normalize the two operands using IEEE 754 standard. Multiply the
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 significant(mantissa). The next step is to add two exponents and subtract the bias 127 and sign
bit is determined by performing an ex-or operation on both MSB bits. Check for exception
flags occurred and determine if there is an underflow or overflow. The final result is obtained
by normalizing the mantissa. The algorithm used for the multiplication is shown above in
figure 2.

RTL Schematic

Simulation Results:

Addition unit:

The single precision addition operation has been implementation in Modelsim. Here for the inputs,
input1=32.33 and input2=48.52 the result has been obtained as 80.85 and is shown in figure 9.

Fig – 1.1 – Addition

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Subtraction Unit:

The single precision Subtraction operation has been implementation in Modelsim. Here for the inputs,
input1=6 (32'h40C00000) and input2 = 5 (32'h40A00000) the result has been obtained as 32'h3F800000
and is shown in figure 9.

Fig – 1.2 – Subtraction

The single precision multiplication operation has been implementation in Modelsim. Here for the inputs,
input1=-13.15 (32'hC152_6666) and input2 = -48.16 (32'hC240_A3D7) the result has been obtained as
633.304 (32'h441E_5375) and is shown in figure 9.

Fig – 1.3 – Multiplication

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Synthesized Gate Level Netlist:

Fig – 1.4 – Gate level netlist for the Addition – Subtraction Module

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 Fig – 1.5 – Gate level netlist for the Multiplication Module

Synthesis Reports:

Addition-Subtraction Module:

Fig – 1.6 – The area report for synthesized design

Report_gates – Addition - Subtraction module

Fig – 1.7 – Represents the gate utilization for the synthesized design of the addition-subtraction unit.

Report_Power – Addition - Subtraction module

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Fig – 1.8 represents the power utilization for the synthesized design.

Report_Area – Multiplication module

Fig – 1.9 – Represents the area utilization for the synthesized design – multiplication unit

Report_power – Multiplication Module

Fig 2.0 – Represents the power utilization of the synthesized design – multiplication module.

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Report_gates – Multiplication Module

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Fig 2.1 – Represents the gate utilization of the synthesized design – multiplication unit.

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CONCLUSION

The implementation of a high-speed single precision FPU has been presented. The design has been synthesized
with TSMC 18 1.0 Logic process technology. Strategies have been employed to realize optimal hardware and
power efficient architecture. Hence it can be concluded that this FPU can be effectively used for ASIC
implementations which can show comparable efficiency and speed and if pipelined then higher throughput may
be obtained.

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OUTCOME OF THE WORK

The Verilog behavioral code for the single precision floating point unit is written compiled using
Modelsim and the synthesis process was done using Cadence Tools - Genus. The various operations like
the multiplication, addition & subtraction are verified using the testbench. The reports of the Synthesis
process were also captured each for power, area and gates.
The simulation results are compared with the expected results and the functionality is found to be correct.

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REFERENCE

[1] Rudolf Usselmann, “Open Floating Point Unit, The Free IP Cores Projects”.
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[3] Prof. Indranil Sengupta,IIT Kharagpur, “ Hardware modelling using Verilog” , NPTEL online
course noc20_cs63
[4] A. Karatsuba and Y. Ofman. Multiplication of Multidigit Numbers on Automata. Soviet Physics-
Doklady, 7 (1963), 595-596.
[5] D. E. Knuth. The Art of Computer Programming. Volume 2: Seminumerical Algorithms.Addison-
Wesley, Reading, Massachusetts, 3rd edition, 1997.
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[12]. Konstantinos Vitoroulis, Asim J. Al-Khalili “Performance of Parallel prefix adders” Proceedings on
workshop on Circuits and Systems ,pp.498-501,Aug.2007
[13]. Giorgos Dimitrakopoulos, Dimitris Nikolos, “High-Speed ParallelPrefix VLSI Ling Adders”, IEEE
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