Digital System Design

Sep. 2014

Professor : Ying-Shieh Kung

Southern Taiwan University
of Science and Technology
 Syllabus
1. Introduction to FPGA (Field Programmable Gate Array)
2. Introduction to VHDL
3. Fundamental digital system design
-> Design of combinational system
-> Standard combinational modules
-> Specification of sequential network
-> Design of sequential network
-> Standard sequential network
4. Introduction to co-simulation of ModelSim/Simulink
5. Advanced digital system design
-> Register transfer level (RTL) systems
-> Data and control subsystems
-> Design of a microcomputer

VHDL: Very High Speed Integrated Circuit Hardware

Description Language 2
 Reference Book
A. Main Reference Book
Book name: Introduction to Digital System
Authors: Milos Ercegovac, Tomas Lang, Jaime H. Moreno
Publisher: John wiley&Sons, Inc.
Publishing Year: 1999
B. Others Reference Books
1. Robert K. Dueck, Digital Design with CPLD Application and VHDL,
2nd THOMOS, 2004. (for undergraduate)
2. Sunggu Lee, Advanced Digital Logic Design: Using VHDL, State
Machines and Synthesis for FPGAs, Nelson, a division of Thomson
Canada Limited. 2006.
3. Mark Zwolinsk, Digital System Design with VHDL, Prentice Hall,
Second edition, 2004.
4. Volnei A. Pedroni, Circuit Design and Simulation with VHDL, Second
Edition, The MIT Press, 2010.

Note: Some teaching materials are arranged from my past research work. 3
 Evaluation

 Homework (3 cases) : 70%

(It needs to make a presentation.)
 Practice : 30%

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 Combinational and Sequential
Systems
Combinational system Sequential system

The output at time t depends on the

The output at time t depends only
input at time t and possibly also
on the input at time t.
depend on the input at time prior to t.
Z(t) = F(x(t)) 5
Z(t) = F(0,x(t))
Example of the sequential system
r 1.

The
put

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Specification and implementation,
analysis and design
Specification
(function and other
characteristics)

Analysis Design

Implementation 7
Hierarchical implementation

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Top-down approach Bottom-up approach
 Levels of an implementation:
Module, Logical, Physical
Logical (gate and For example: Compute
t
flip-flop) level
Modules level Z( t ) = ∑ X ( i )
i =0

At Modules level:
The system consists of
two registers and an adder.
At Logical level:
These modules are
Implemented with gates and
Flip-flops.
At Physical level:
These component are
transistors and power supplies.

Physical level
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VHDL-based description of a
system
Use work.ALL;
Entity sample_system IS
PORT (xin: IN BIT_VECTOR;
z : OUT BIT_VECTOR;
clk : IN BIT);
END sample_system;

Architecture structure1 of sample_system IS

SIGNAL xreg, yreg, addout: BIT_VECTOR(7 DOWNTO 0);
BEGIN
RX: ENTITY BitReg8 PORT MAP (xin, xreg, clk);
RY: ENTITY BitReg8 PORT MAP (addout, yreg, clk);
ADD: ENTITY adder PORT MAP (xreg, yreg, addout);
Z <= addout;
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END structural;
SoPC Technology based on FPGA
A SoPC (System-on-a-Programmable- Nios II UART
CPU
Chip) technologies enables to integrate
PIO

Avalon™ Bus
an embedded processor IP (Intellectual
On-Chip
Property) and an application IP into a ROM Timer

Field Programmable Gate Array SPI

Cyclon EP1C20
(FPGA). On-Chip
20,060 LEs RAM SDRAM
Controller
Nios processor:
Min. 1,000~1,500 LEs

Your Design
Application
IP Here
FPGA
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Hardware/Software co-design
 The requirement for high sampling
frequency control (~10kHz, or ~MHz) but
fixed computation is designed by hardware.
 The requirement for flexible processing and
low computation power (under 1kHz) is
designed by software.

Therefore, all functionalities, which are based on software/hardware co-

design, required to build a fully digital system will be integrated in one
FPGA chip.

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 ModelSim/Simulink Co-simulation using
EDA Simulator Link
• A co-simulation work by Electronic Design Automation (EDA) Simulator
Link has been gradually applied to verify the effectiveness of the Verilog
and VHDL code in the digital system.

• The EDA Simulator Link provides a co-simulation interface between

MALTAB or Simulink and HDL simulators-ModelSim . Using it you can
verify a VHDL, Verilog, or mixed-language implementation against your
Simulink model or MATLAB algorithm.

• EDA Simulator Link lets you use MATLAB code and Simulink models as a
test bench that generates stimulus for an HDL simulation and analyzes the
simulation’s response.

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ModelSim/Simulink co-simulation
for cosine

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 Hardware implementation of Sin/Cos
function
GEN : block
begin FSM for computing the cosine function
process (CLK)
begin
if CLK'event and CLK='1' then θ (15..7)
step<=step+1; LUT
mult_r1(46..23)
if step=0 then (cos)
sin_addr <= sita(15 downto 7); x
cos_addr <= sita(15 downto 7); ∆θ (6..0) LUT
Cos_16=
addr1(23..8)
dsin_addr <= sita(6 downto 0); (dcos)
dcos_addr <= sita(6 downto 0);
+
elsif step=2 then LUT
(sin)
-
mult_a1 <= cos_sita;
mult_b1 <= dcos_sita;
x
LUT mult_r2(46..23)
mult_a2 <= sin_sita;
(dsin)
mult_b2 <= dsin_sita;
elsif step=3 then
adda1 <= mult_r1(46 downto 23); s0 s1 s2 s3 s4
addb1 <= -mult_r2(46 downto 23);
elsif step=4 then
cos_16 <= addr1(23 downto 8);
step <= x"00"; cos(θ + ∆θ ) = cos(θ ) cos(∆θ ) − sin(θ ) sin( ∆θ )
end IF;
end IF;
end process; Four LUTs are built.
end block GEN;

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