CSC 232 Computer Organization

and Architecture

Dr. Charles Nche

Structure of von Neumann machine
 5.0 Processing Unit Design

• On completing this chapter, the students should be

able to;
• Explain the main component of any computer
system
• Discuss the primary function of the central
processing unit (CPU).
• Explain the organization and main operations of the
CPU.
• Explains the different types of registers and their
functions.
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 5.1 CPU Basic

• A typical CPU has three major components:

– Register Set,
– Arithmetic Logic Unit, and
– Control Unit (CU).
– The register set is usually a combination of
general-purpose and special-purpose registers.
• General-purpose registers are used for any purpose.
• Special-purpose registers have specific functions
within the CPU.

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 5.1 CPU Basic

CPU Main Components and Interactions with the Memory and

I/O
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 5.1 CPU Basic

• The ALU provides the circuitry needed to perform

the arithmetic, logical and shift operations
demanded of the instruction set.
• The control unit is responsible for fetching the
instruction to be executed from the main memory
and decoding and then executing it.
• The CPU fetches instructions from memory, reads
and writes data from and to memory, and transfers
data from and to input/output devices.

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 5.1 CPU Basic

• A typical and simple execution cycle in a CPU is as

follows:
– The next instruction to be executed, whose
address is obtained from the PC, is fetched from
the memory and stored in the IR.
– Instruction is decoded.
– Operands are fetched from the memory and stored
in CPU registers, if needed.
– Instruction is executed.
– Results are transferred from CPU registers to the
1.12 memory, if needed.
 5.1 CPU Basic

• The execution cycle is repeated as long as there are

more instructions to execute.
• A check for pending interrupts is usually included
in the cycle.
• Examples of interrupts include I/O device request,
arithmetic overflow, or a page fault
• Interrupt handling routines are programs that are
invoked to collect the state of the currently
executing program, correct the cause of the
interrupt, and restore the state of the program.
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 5.1 CPU Basic

• Actions of the CPU during an execution cycle are defined

by micro-orders issued by the control unit.
• These micro-orders are individual control signals sent over
dedicated control lines.
• For example, to moves the contents of register X to register
Y. Both registers are connected to the data bus, D.
• The control unit will issue a control signal to tell register X
to place its contents on the data bus D.
• After some delay, another control signal will be sent to tell
register Y to read from data bus D.
• The activation of the control signals is determined using
either hardwired control or microprogramming.
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 5.2 Register Set

• Registers are essentially extremely fast memory

locations within the CPU that are used to create and
store the results of CPU operations and other
calculations.
• Different computers have different register sets.
• Memory Access Registers
– Two registers are essential in memory write and read
operations: memory data register (MDR) and
memory address register (MAR).
– The MDR and MAR are used exclusively by the CPU
1.15and are not directly accessible to programmers.
 5.2 Register Set

• In order to perform a write operation into a

specified memory location, the MDR and MAR are
used as follows:
• The word to be stored into the memory location is
first loaded by the CPU into MDR
• The address of the location into which the word is
to be stored is loaded by the CPU into a MAR.
• The number of registers in a particular architecture
affects the instruction set design

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 5.2 Register Set

• Memory Access Registers

– Similarly, to perform a memory read operation, the
MDR and MAR are used as follows:
• The address of the location from which the word is
to be read is loaded into the MAR.
• The required word will be loaded by the memory
into the MDR ready for use by the CPU.
• Instruction Fetching Registers
– Two main registers are involved in fetching an
instruction for execution: the program counter (PC)
1.17and the instruction register (IR).
 5.2 Register Set

• Instruction Fetching Registers

– The PC is the register that contains the address
of the next instruction to be fetched.
– The fetched instruction is loaded in the IR for
execution.
– After a successful instruction fetch, the PC is
updated to point to the next instruction to be
executed.
– In the case of a branch operation, the PC is
updated to point to the branch target instruction
1.18after the branch is resolved.
 5.2 Register Set

• Condition Registers
– Condition registers, or flags, are used to
maintain status information.
– Some architectures contain a special Program
Status Word (PSW) register.
– The PSW contains bits that are set by the CPU
to indicate the current status of an executing
program.
– These indicators are typically for arithmetic
operations, interrupts, memory protection
1.19information, or processor status.
 5.2 Register Set

• Special Purpose Address Registers

– Index register
• The index register holds an address displacement.
• Index addressing is indicated in the instruction by including
the name of the index register in parentheses and using the
symbol X to indicate the constant to be added.
– Segment pointers
• The address issued by the processor should consist of a
Segment Number (Base) and a Displacement (or an offset)
within the segment.
• A segment register holds the address of the base of the
segment.
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 5.2 Register Set

– Stack Pointer:
• A stack is a data organization mechanism in which the last
data item stored is the first data item retrieved.
• Two specific operations can be performed on a stack. These
are the Push and the Pop operations.
• A specific register, called the stack pointer (SP), is used to
indicate the stack location that can be addressed.
• In the stack push operation, the SP value is used to indicate
the location (called the top of the stack).
• After storing (pushing) this value, the SP is incremented (In
some architectures a SP is decremented (i.e. x86) as the
stack grows low in memory).
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 5.2 Register Set

80x86 Registers
– the Intel basic programming model of the 386, 486 and
the Pentium consists of three register groups:
• General-purpose registers,
• Segment registers, and
• The instruction pointer (program counter) & the flag
register.

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 5.3 Datapath

The CPU can be divided into:

– Data section
• The data section, also called the datapath, contains
the registers and the ALU.
• The datapath is capable of performing certain
operations on data items.
– Control section is basically the control unit, which
issues control signals to the datapath.
• Internal to the CPU, data move from one register to
another and between ALU and registers.
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 5.3 Datapath

– Internal data movements are performed via local

buses, which may carry data, instructions, and
addresses.
• Internal data movement among registers and
between the ALU and registers may be carried out
using different organizations including one-bus,
two-bus or three-bus organizations.
• Externally, data move from registers to memory and
I/O devices, often by means of a system bus.

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 5.3 Datapath

– One-Bus Organization
– Using one bus, the CPU registers and the ALU
use a single bus to move outgoing and
incoming data.
– Since a bus can handle only a single data
movement within one clock cycle, two-operand
operations will need two cycles to fetch the
operands for the ALU.
– Additional registers may also be needed to
buffer data for the ALU.
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 5.3 Datapath

– This bus organization is the simplest and least

expensive but it limits the amount of data
transfer that can be done in the same clock
cycle, which will slow down the overall
performance.

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 5.3 Datapath

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 5.3 Datapath

– Two-Bus Organization
– Using two buses is a faster solution than the one bus.
– General-purpose registers are connected to both
busses.
• Data can be transferred from two different registers
to the input point of the ALU at the same time.
– A two-operand operation can fetch both operands at
the same clock cycle.
– Additional buffer register may hold the output of the
ALU when the two busses are busy carrying the
1.28two operands.
 5.3 Datapath

– In some cases, one of the busses may be dedicated

for moving data into registers (in-bus), while the
other is dedicated for transferring data out of the
registers (out-bus).
• In this case, the additional buffer register may be
used, as one of the ALU inputs, to hold one of the
operands.
• The ALU output can be connected directly to the in-
bus, which will transfer the result into one of the
registers.
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 5.3 Datapath

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 5.3 Datapath

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 5.3 Datapath

• Three-Bus Organization
– Two buses may be used as source busses while the third is
used as destination.
– The source busses move data out of registers (out-bus), and
the destination bus may move data into a register (in-bus).
– Each of the two out-busses is connected to an ALU input
point.
– The output of the ALU is connected directly to the in-bus.
– The more busses we have, the more data we can move
within a single clock cycle.
– However, increasing the number of busses will also increase
the complexity of the hardware.
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 5.3 Datapath

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 5.4 CPU Instruction Cycle

• As long as there are instructions to execute, the next

instruction is fetched from main memory.
• The instruction is executed based on the operation
specified in the opcode field of the instruction.
• At the completion of the instruction execution, a test
is made to determine whether an interrupt has
occurred.

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 5.4 CPU Instruction Cycle

• An interrupt handling routine needs to be invoked in

case of an interrupt.
• The basic actions during fetching an instruction,
executing an instruction, or handling an interrupt
are defined by a sequence of micro-operations.
• A group of control signals must be enabled in a
prescribed sequence to trigger the execution of a
micro-operation.

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 5.4 CPU Instruction Cycle

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 5.4 CPU Instruction Cycle

• Fetch Instructions
– The sequence of events in fetching an instruction can
be summarized as follows:
• The contents of the PC are loaded into the MAR.
• The value in the PC is incremented. (This operation
can be done in parallel with a memory access).
• As a result of a memory read operation, the
instruction is loaded into the MDR.
• The contents of the MDR are loaded into the IR.

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 5.4 CPU Instruction Cycle

In one-bus datapath organization shown below the

fetch operation can be accomplished in three steps.

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 5.4 CPU Instruction Cycle

• Using the three-bus datapath, the following table

shows the steps needed.

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 5.4 CPU Instruction Cycle

• Execute Simple Arithmetic Operation

– Add R1, R2, R0
• This instruction adds the contents of source
registers R1 and R2, and stores the results in
destination register R0.
• This addition can be executed as follows:
– The registers R0, R1, R2, are extracted from the IR.
– The contents of R1 and R2 are passed to the ALU for
addition.
– The output of the ALU is transferred to R0.
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 5.4 CPU Instruction Cycle

• Using the one-bus datapath, this addition will take

three steps as shown in the following table, where
t0 < t1 < t2 .

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 5.3 Datapath

1.42
 5.4 CPU Instruction Cycle

• Using the two-bus datapath, this addition will take

two steps as shown in the following table, where t0
< t1.

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 5.3 Datapath

1.44
 5.4 CPU Instruction Cycle

• Using the two-bus datapath with in-bus and out-

bus, this addition will take two steps as shown
below, where t0 < t1.

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 5.3 Datapath

1.46
 5.4 CPU Instruction Cycle

• Using the three-bus datapath, this addition will take

only one step as shown in the following table.

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 5.3 Datapath

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 5.4 CPU Instruction Cycle

Execute Simple Arithmetic Operation – Add X, R0

• This instruction adds the contents of memory
location X to register R0 and stores the result in R0.
• This addition can be executed as follows:
• The memory location X is extracted from IR and
loaded into MAR.
• As a result of memory read operation, the contents
of X are loaded into MDR.
• The contents of MDR are added to the contents of
R0.
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 5.4 CPU Instruction Cycle

• Using the one-bus datapath, this addition will take

five steps as shown below, where t0 < t1 <t2<t3<t4.

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 5.4 CPU Instruction Cycle

• Using the two-bus datapath, this addition will take

four steps as shown below, where t0 < t1 < t2 < t3.

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 5.4 CPU Instruction Cycle

• Using the two-bus datapath with in-bus and out-bus

shown, this addition will take four steps as shown
below,, where t0 < t1 < t2 < t3.

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 5.4 CPU Instruction Cycle

• Using the three-bus datapath, this addition will take

three steps as shown below, where t0 < t1 < t2.

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 5.4 CPU Instruction Cycle

• Interrupt Handling
• After the execution of an instruction, a test is performed to
check for pending interrupts.
• If there is an interrupt request waiting, the following steps
take place:
• The contents of PC are loaded into MDR (to be saved).
• The MAR is loaded with address at which the PC contents
to be saved.
• The PC is loaded with the address of the first instruction of
the interrupt handling routine.
• The contents of MDR (old value of the PC) are stored in
memory.
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 5.4 CPU Instruction Cycle

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 5.5 Control Unit

• The control unit is the main component that directs

the system operations by sending control signals to
the datapath.
• These signals control the flow of data within the
CPU and between the CPU and external units such
as memory and I/O.
• Control busses generally carry signals between the
control unit and other computer components in a
clockdriven manner.
• The system clock produces a continuous sequence
1.56of pulses in a specified duration and frequency.
 5.5 Control Unit

• The Functions of Control Unit

• Responsible for controlling the transfer of data and
instructions among other units of a computer
• Manages and coordinates all the units of the
computer
• Obtains instructions from memory, interprets them,
and directs the operation of the computer
• Communicates with Input/Output devices for
transfer of data or results from storage
• It does not process or store data.
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 5.5 Control Unit

• A sequence of steps t0, t1, t2, … (t0 < t1 < t2 <…)

are used to execute a certain instruction.
• The op-code field of a fetched instruction is
decoded to provide the control signal generator with
information about the instruction to be executed.
• Step information generated by a logic circuit
module is used with other inputs to generate control
signals.
• The signal generator can be specified simply by a
set of Boolean equations for its output in terms of
1.58its inputs..
 5.5 Control Unit

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 5.5 Control Unit

• Mainly two different types of control units:

– Microprogrammed
• The control signals associated with operations are
stored in special memory units inaccessible by the
programmer as control words.
• A control word is a microinstruction that specifies
one or more microoperations.
• A sequence of microinstructions is called a
microprogram, which is stored in a ROM or RAM
called a control memory CM.
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 5.5 Control Unit

– Hardwired
• Fixed logic circuits that correspond directly to the
Boolean expressions are used to generate the
control signals.
• Hardwired control is more economical for small
control units.
• It should also be noted that microprogrammed
control could adapt easily to changes in the
system design.
• We can easily add new instructions without
1.61changing hardware.
 5.5 Control Unit

Example, Let us revisit the add operation in which we add the

contents of source registers R1 , R2 , and store the results in
destination register R0 .
We have shown earlier that this operation can be done in one
step using the three-bus datapath.
Let us try to examine the control sequence needed to
accomplish this addition at step t0 . Suppose that the op-code
field of the current instruction was decoded to Inst-x type.
First we need to select the source registers and the destination
register, then we select Add as the ALU function to be
performed. The following table shows the needed step and the
control sequence..
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 5.5 Control Unit

1.63
 5.5 Control Unit

• The fig shows the signals generated to execute Inst-

x during time period t0 .
• The AND gate ensures that these signals will be
issued when the op-code is decoded into Inst-x and
during time period t0 . The signals (R1 out-bus 1),
(R2 out-bus2),
• (R0 in-bus), and (Add) will select R1 as a source on
out-bus1, R2 as a source on outbus2,
• R0 as destination on in-bus, and select the ALUs
add function, respectively.
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 5.5 Control Unit

1.65
 5.5 Control Unit

Example 2 Let us repeat the operation in the previous

example using the one-bus datapath. We have shown
earlier that this operation can be carried out in three
steps using the one-bus datapath. Suppose that the op-
code field of the current instruction was decoded to
Inst-x type. The following table shows the needed
steps and the control sequence.

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 5.5 Control Unit

1.67
 5.5 Control Unit

• The fig shows the signals generated to execute Inst-x

during time periods t0, t1, and t2. The AND gates ensure
that the appropriate signals will be issued when the op-code
is decoded into Inst-x and during the appropriate time
period.
• During t0, the signals (R1 out) and (A in) will be issued to
move the contents of R1 into A. Similarly during t1, the
signals (R2 out) and (B in) will be issued to move the
contents of R2 into B.
• Finally, the signals (R0 in) and (Add) will be issued during
t2 to add the contents of A and B and move the results into
R0.
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 5.5 Control Unit

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 5.5 Control Unit

• Hardwired Implementation
• In hardwired control, a direct implementation is
accomplished using logic circuits.
• For each control line, one must find the Boolean expression
in terms of the input to the control signal generator.
• Assume that the instruction set of a machine has three
instructions: Inst-x, Inst-y, and Inst-z; and A, B, C, D, E, F,
G, and H are control lines. The following table shows the
control lines that should be activated for the three
instructions at the three steps t0 , t1 , and t2 .

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 5.5 Control Unit

1.71
 5.5 Control Unit

1.72
 5.5 Control Unit

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 5.5 Control Unit

• Microprogrammed Control Unit

• Microprogramming was motivated by the desire to
reduce the complexities involved with hardwired
control.
• Associated with each micro-operation is a set of
control lines that must be activated to carry out the
corresponding micro-operation.
• After fetching each microinstruction, the
appropriate control lines will be enabled.

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 5.5 Control Unit

• The idea of microprogrammed control is to store the

control signals associated with the implementation of a
certain instruction as a microprogram in a special memory
called a control memory (CM).
• A microprogram consists of a sequence of
microinstructions.
• A microinstruction is a vector of bits, where each bit is a
control signal, condition code, or the address of the next
microinstruction.
• Microinstructions are fetched from CM the same way
program instructions are fetched from main memory.

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 5.5 Control Unit

• Every control line that corresponds to a “1” bit should be

turned on. Every control line that corresponds to a “0” bit
should be left off.
• After completing the execution of one microinstruction, a
new microinstruction will be fetched and executed.
• The length of a microinstruction is determined based on the
number of microoperations specified in the
microinstructions.
• The length of a microinstruction could be reduced if
control lines are coded in specific fields in the
microinstruction.

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 5.5 Control Unit

• Decoders will be needed to map each field into the

individual control lines.
• Using decoders will reduce the number of control
lines that can be activated simultaneously.
• Tradeoff between the length of microinstructions
and the amount of parallelism. It is important we
reduce the length of microinstructions to reduce the
cost and access time of the control memory.
• It may also be desirable that more micro-operations
be performed in parallel and more control lines can
1.77be activated simultaneously.
 5.5 Control Unit

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 5.5 Control Unit

Microprogrammed Control Unit

– Horizontal versus Vertical Microinstructions
• Individual bits in horizontal microinstructions
correspond to individual control lines.
• Horizontal microinstructions are long and allow
maximum parallelism since each bit controls a
single control line.
• In vertical microinstructions, control lines are coded
into specific fields within a microinstruction.

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 5.5 Control Unit

• Decoders are needed to map a field of k bits to 2k

possible combinations of control lines.
• Because of the encoding, vertical microinstructions
are much shorter than horizontal ones.
• Control lines encoded in the same field cannot be
activated simultaneously. Therefore, vertical
microinstructions allow only limited parallelism.

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 5.5 Control Unit

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 5.5 Control Unit

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 5.5 Control Unit

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 5.5 Control Unit

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 5.5 Control Unit

Microinstruction for Add R1, R2, R0

Microinstruction for MAR PC

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 5.5 Control Unit

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 5.6 Summary

• The central processing unit (CPU) is the part of a computer

that interprets and carries out the instructions contained in
the programs we write.
• The CPU’s main components are the register file, ALU,
and the control unit.
• The register file contains general-prupose and special
registers.
– General-purpose registers may be used to hold operands
and intermediate results.
• The special registers may be used for memory access,
sequencing, status information, or to hold the fetched
instruction during decoding and execution.
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 5.6 Summary

• Arithmetic and logical operations are performed in the

ALU.
• Internal to the CPU, data may move from one register
to another or between registers and ALU.
• Data may also move between the CPU and external
components such as memory and I/O.
• The control unit is the compnent that controls the
state of the instruction cycle.
• As long as there are instructions to execute, the next
instruction is fetched from main memory.

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 5.6 Summary

• The instruction is executed based on the operation

specified in the opcode field of the instruction.
• The control unit generates signals that control the
flow of data within the CPU and between the CPU
and external units such as memory and I/O.
• Control unit can be implemented using hardwired or
microprogramming techniques..

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