B.E.

ELECTRONICS AND COMMUNICATION ENGINEERING

Choice Based Credit System (CBCS)
SEMESTER - VI
VLSI LAB (0:0:3) 1.5
(Effective from the academic year 2020-21)
Course Code 20ECL609 CIE Marks 50
Teaching Hours/Week (L:T:P) 0:0:3 SEE Marks 50
Total Number of Contact Hours 26 Exam Hours 3
Course Objectives: This course will enable students to:
1. Design, model, simulate and verify CMOS digital circuits
2. Design layouts and perform physical verification of CMOS digital circuits
3. Perform ASIC design flow and understand the process of synthesis, synthesis
constraints and evaluating the synthesis reports to obtain optimum gate
level net list
4. Perform RTL-GDSII flow and understand the stages in ASIC design
Laboratory Experiments
Part – A
1a). Capture the schematic of CMOS inverter with load capacitance of 0.1pF and set
the widths of inverter with Wn = Wp, Wn = 2Wp, Wn = Wp/2 and length at
selected technology. Carry out the following:
I. Set the input signal to a pulse with rise time, fall time of 1ns and pulse width
of 10ns and time period of 20ns and plot the input voltage and output
voltage of designed inverter?
II. From the simulation results compute tpHL, tpLH and td for all three
III. Geometrical settings of width?
IV. Tabulate the results of delay and find the best geometry for minimum delay
for CMOS inverter?
1 b) Draw layout of inverter with Wp/Wn = 40/20, use optimum layout methods.
Verify for DRC and LVS, extract parasitic and perform post layout simulations,
compare the results with pre-layout simulations. Record the observations.
2. a) Capture the schematic of 2-input CMOS NAND gate having similar delay as that
of CMOS inverter computed in experiment 1. Verify the functionality of NAND
gate and also find out the delay td for all four possible combinations of input
vectors. Table the results. Increase the drive strength to 2X and 4X and tabulate
the results.
2. b) Draw layout of NAND with Wp/Wn = 40/20, use optimum layout methods.
Verify for DRC and LVS, extract parasitic and perform post layout simulations,
compare the results with pre-layout simulations. Record the observations.
1. a) Capture schematic of Common Source Amplifier with PMOS Current Mirror
Load and find its transient response and AC response? Measures the Unity Gain
Bandwidth (UGB), amplification factor by varying transistor geometries, study
the impact of variation in width to UGB.
3. b) Draw layout of common source amplifier, use optimum layout methods. Verify
for DRC and LVS, extract parasitic and perform post layout simulations,
compare the results with pre-layout simulations. Record the observations.
Part - B
Digital Design
 1. Write Verilog code for 4-bit up/down asynchronous reset counter and carry out
the following:
I. Verify the functionality using test bench
b. Synthesize the design by setting area and timing constraint. Obtain the
gate
level netlist, find the critical path and maximum frequency of operation.
Record the area requirement in terms of number of cells required and
properties of each cell in terms of driving strength, power and area
requirement.
c. Perform the above for 32-bit up/down counter and identify the critical
path, delay of critical path, and maximum frequency of operation, total
number of cells required and total area.
2. Write Verilog code for 4-bit adder and verify its functionality using test bench.
Synthesize the design by setting proper constraints and obtain the net list. From
the report generated identify critical path, maximum delay, total number of cells,
power requirement and total area required. Change the constraints and obtain
optimum synthesis results.
1. Write Verilog code for 32-bit ALU supporting four logical and four arithmetic
operations, use case statement and if statement for ALU behavioural modelling.
a. Perform functional verification using test bench
b. Synthesize the design targeting suitable library by setting area and timing
constraints
c. For various constrains set, tabulate the area, power and delay for the
synthesized netlist
d. Identify the critical path and set the constraints to obtain optimum gate level
netlist with suitable constraints
Compare the synthesis results of ALU modelled using IF and CASE statements
2. Write Verilog code for Latch and Flip-flop, Synthesize the design and compare the
synthesis report (D, SR, JK).
3. For the synthesized netlist carry out the following for any two above
experiments:
a. Floor planning (automatic), identify the placement of pads
b. Placement and Routing, record the parameters such as no. of layers used
for routing, flip method for placement of standard cells, placement of
c. standard cells, routes of power and ground, and routing of standard cells
d. Physical verification and record the LVS and DRC reports
e. Perform Back annotation and verify the functionality of the design
f. Generate GDSII and record the number of masks and its color
composition.
Course outcomes: The students will be able to:
CO1: Design and simulate combinational and sequential digital circuits using Verilog
HDL.
CO2: Understand the Synthesis process of digital circuits and perform RTL-GDSII
flow and understand the stages in ASIC design using EDA tool.
CO3: Perform ASIC design flow and understand the process of synthesis, synthesis
constraints and evaluating the synthesis reports to obtain optimum gate level
net list.
CO4: Design and simulate basic CMOS circuits like inverter, common source
 amplifier and differential amplifiers.
Textbooks
1. Sung Mo Kang & Yosuf Leblebici “CMOS Digital Integrated Circuits: Analysis and
Design” Tata McGraw-Hill, Third Edition, 2002.
Neil H. E. Weste, and David Money Harris “CMOS VLSI Design- A Circuits and
Systems Perspective” Pearson Education, 4 Edition, 2011.
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