HARDWARE DESCRIPTION

LANGUAGE

Digital Design: With an Introduction to the Verilog HDL, 5e

M. Morris Mano • Michael D. Ciletti
Copyright ©2013 by Pearson Education, Inc., All rights reserved.
• Manual methods for designing logic circuits are feasible only when
the circuit is small.
• For anything else designers use computer-based design tools.
• A hardware description language (HDL) is a computer-based language
that describes the hardware of digital systems in a textual form.
• It resembles an ordinary computer programming language, such as C,
but is specifically oriented to describing hardware structures and the
behavior of logic circuits.
Module Declaration
• The language reference manual for the Verilog HDL presents a syntax
that describes precisely the constructs that can be used in the
language.
• Keywords are predefined lowercase identifiers that define the
language constructs. Examples of keywords are module, endmodule,
input, output, wire, and, or, and not.
• For clarity, keywords will be displayed in boldface in the text in all
examples of code and wherever it is appropriate to call attention to
their use.
Module Declaration
• Any text between two forward slashes ( // ) and the end of the line is
interpreted as a comment and will have no effect on a simulation
using the model. Multiline comments begin with /*and terminate
with */.
• Verilog is case sensitive, which means that uppercase and lowercase
letters are distinguishable.
• The term module refers to the text enclosed by the keyword pair
module
...
endmodule.
Module Declaration
• A module is the fundamental descriptive unit in the Verilog language.
• It is declared by the keyword module and must always be terminated
by the keyword endmodule.
• The keyword module starts the declaration (description) of the
module; the last line completes the declaration with the keyword
endmodule.
• The keyword module is followed by a name and a list of ports. In
general, we choose meaningful names for modules.
Module Declaration
• The port list of a module is the interface between the module and its
environment.
• The logic values of the inputs to a circuit are determined by the
environment; the logic values of the outputs are determined within
the circuit.
• The port list is enclosed in parentheses, and commas are used to
separate elements of the list.
• The statement is terminated with a semicolon (;).
• The keywords input and output specify which of the ports are inputs
and which are outputs. Internal connections are declared as wires.
Module Declaration
• The structure of circuit is specified by a list of (predefined) primitive
gates, each identified by a descriptive keyword (and, not, or).
• The elements of the list are referred to as instantiations of a gate,
each of which is referred to as a gate instance.
• Each gate instantiation consists of an optional name (such as G1, G2,
etc.).
• The output of a primitive gate is always listed first, followed by the
inputs. But the inputs and outputs of a module may be listed in any
order.
Gate Delays
• All physical circuits exhibit a propagation delay between the transition
of an input and a resulting transition of an output.
• When an HDL model of a circuit is simulated, it is sometimes
necessary to specify the amount of delay from the input to output.
• In Verilog, the propagation delay of a gate is specified in terms of
time units and by the symbol #.
• The association of a time unit with physical time is made with
the `timescale compiler directive.
• Such a directive is specified before the declaration of a module and
applies to all numerical values of time in the code that follows.
`timescale 1ns/100ps
Gate Delays
• The first number specifies the unit of measurement for time delays.
The second number specifies the precision for which the delays are
rounded off, in this case to 0.1 ns.
Gate Delays
Test Bench
• In order to simulate a circuit with an HDL, it is necessary to apply
inputs to the circuit so that the simulator will generate an output
response.
• An HDL description that provides the stimulus to a design is called a
test bench.
• In its simplest form, a test bench is a module containing a signal
generator and an instantiation of the model that is to be verified.
• Note that the test bench has no input or output ports, because it
does not interact with its environment.
Test Bench
Test Bench
• Within the test bench, the inputs to the circuit are declared with
keyword reg and the outputs are declared with the keyword wire.
• Every instantiation of a module must include a unique instance name.
• Note that using a test bench is similar to testing actual hardware by
attaching signal generators to the inputs of a circuit and attaching
probes (wires) to the outputs of the circuit.
 Test Bench
• Hardware signal generators are not used to verify an HDL model: The
entire simulation exercise is done with software models executing on
a digital computer under the direction of an HDL simulator.
• The waveforms of the input signals are abstractly modeled by Verilog
statements specifying waveform values and transitions.
• The initial keyword is used with a set of statements that begin
executing when the simulation is initialized; the signal activity
associated with initial terminates execution when the last statement
has finished executing.
• The initial statements are commonly used to describe waveforms in a
test bench.
Test Bench
• The set of statements to be executed is called a block statement and
consists of several statements enclosed by the keywords begin and
end.
• A second initial statement uses the $finish system task to specify
termination of the simulation. If a statement is preceded by a delay
value (e.g., #100), the simulator postpones executing the statement
until the specified time delay has elapsed.