UNIT III I/O INTERFACING

PART A

1. With neat block diagram explain the 8255 Programmable Peripheral Interface
and its operating modes. [Marks 16]

The 8255 chip is also called as Programmable Peripheral Interface. The Intel 8255A is a
general purpose programmable I/O device which is designed for use with all Intel and most
other microprocessors. It has 3 I/O ports, Port A , Port B and Port C each of 8 bits. The eight
bits of Port C is divided into two 4 bit ports. Cupper (C U) and C lower(CL).

8255 contains two modes of operation Bit Set/Reset Mode(BSR) and I/O

Mode

BSR Mode is used to set or reset the bits in port C which is used for hand shake signals.

I/O mode is divided into three modes

Mode 0 (Simple input/output)

Mode 1 (Handshake mode)
Mode 2 (Bidirectional Data Transfer)

Port A

Port C
8255

Port B

Mode 0 Operation (Simple input/output) It does not use any handshake signals. All
the ports are used for simple data transfer.
Mode 1 Operation (Handshake mode) Port A and B are used for data transfer and
Port C is used for hand shake signals.
Mode 2 (Bidirectional Data Transfer)Port A is used for Bidirectional data transfer.
Port B in either in mode 0 or 1. Port C is used for Handshake signals
MODES OF 8255 BIT SET/RESET(BSR) MODE-
Set/Reset bits in Port C

BLOCK DIAGRAM OF 8255

The block diagram contains

1. Data bus buffer

2. Read/Write control logic
3. Group A and Group B controls
4. Port A, B and C

DATA BUS BUFFER

This three-state bi-directional 8-bit buffer is used to interface the 8255 to the system
data bus. Data is transmitted or received by the buffer upon execution of input or
output instructions by the CPU. Control words and status information are also
transferred through the data bus buffer.

READ/WRITE AND CONTROL LOGIC

The function of this block is to manage all of the internal and external transfers of
both Data and Control or Status words. It accepts inputs from the CPU Address and
Control busses and in turn, issues commands to both of the Control Groups.

CS Chip Select. A "low" on this input pin enables the communication between the
8255 and the CPU.
RD Read: This control signal enables the read operation. A "low" on this input pin
enables 8255 to read data from the selected I/O.
WR Write: This control signal enables the write operation. A "low" on this input pin
enables 8255 to write a data into the selected I/O or control register.
A0 and A1: These input signals, in conjunction with the RD and WR inputs, control
the selection of one of the three ports or the control word register. They are normally
connected to the least significant bits of the address bus (A0 and A1).

A1 A0 SELECTION
0 0 PORT A
0 1 PORT B
1 0 PORT C
1 1 CONTROL

RESET : A "high" on this input clears the control register and all ports (A, B, C) are
set to the input mode.

GROUP A AND GROUP B CONTROLS

These block receive control from the CPU and issues commands to their respective ports. The
two groups of I/O pins are named as Group A and Group B. Group A contains eight I/O lines
of Port A (PA0 – PA 7) and another four lines of Port Cupper (PC0 – PC 3). Group B contains
eight I/O lines of Port B(PB0 – PB 7) and another four lines of Port C lower(PC4 – PC 7). The
functional configuration of each port is programmed by the systems software. In essence,
the CPU "outputs" a control word to the 8255. The control word contains information such as
"mode", "bit set", "bit reset", etc., that initializes the functional configuration of the 8255.
Each of the Control blocks (Group A and Group B) accepts "commands" from the
Read/Write Control logic, receives "control words" from the internal data bus and
issues the proper commands to its associated ports.

PORTS A, B, AND C
The 8255 contains three 8-bit ports (A, B, and C).
Port A: This has an 8 bit latched/buffered O/P and 8 bit input latch. It can be
programmed in 3 modes – mode 0, mode 1, mode 2
Port B: This has an 8 bit latched / buffered O/P and 8 bit input latch. It can be
programmed in mode 0, mode1.
Port C: This has an 8 bit latched input buffer and 8 bit output latched/buffer. This
port can be divided into two 4 bit ports and can be used as control signals for port A
and port B. it can be programmed in mode 0.

Control Word Register

The content of the control register specify an I/O function for each port. This register can be
accessed to write word when A0 and A1 are at logic 1. This register is not accessible for read
operation. Bit D7 specifies either the I/O function or the BSR functions. If bit D 7 = 1, bits D6 –D 0
determine I/O functions in various modes. If Bit D7 = 0 port C operates in BSR mode.

Modes of Operation

These are two basic modes of operation of 8255. Bit Set/Reset Mode(BSR) and I/O Mode
In I/O mode, the 8255 ports work as programmable I/O ports, while in BSR mode only port
C can be used to set or reset its individual port bits. It is used to set or reset the bits in
port C which is used for hand shake signals.
The I/O mode is divided into three modes : Mode 0 (Simple input/output) , Mode 1
(Handshake mode) , Mode 2 (Bidirectional Data Transfer)

Mode 0 Operation (Simple input/output) It does not use any handshake signals. All
the ports are used for simple data transfer. It is used for interfacing an i/p device or
an o/p device. It is used when timing characteristics of I/O devices is well known.

Mode 1 Operation (Handshake mode) Port A and B are used for data transfer and
Port C is used for hand shake signals. 3 lines are used for handshaking. It is used for
interfacing an input device or an output device. Handshake signals of the port inform
the processor that the data is available, data transfer complete etc.

INTEA PA7 – PA0

PORTA I/P Mode 1 Input Control

Signals STB :
PC4 STBA
The strobe input loads data into the
IBFA port latch on a 0-to-1 transition.
PC5
IBF :

Input buffer full is an output signal

indicating that the input latch
INTRA contains information.
PC3

INTR :
INTEB
STBB Interrupt request is an output
PC2
signal that requests an interrupts.

INTE :
PC1 IBFB
The interrupt enable signal is an
internal flip flop used to enable or
disable the generation of INTR
PC3
INTRB signal.

PC7,PC6 :
PORT B I/P PB7 – PB0
The port C pins 7 and 6 are general
purpose I/O pins that are available for
PC 6,7 I/O
 INTEA PORTA O/P PA7 – PA0 Mode 1 Output Control Signals

OBFA OBF :
PC7
Output buffer full is an output
signal
that goes low when data is latched
in
PC6 ACKA either port A or port B. Goes low
on
ACK.

PC ACK :
3 that must output a low when the peripheral receives a data.
INTEB
INTR :
PC2 OBFB
Interrupt request is an output
signal that can be used to
ACKB interrupt the MPU to request the
PC1 next data byte for output.

INTE :
INTRB The interrupt enable signal is an
PC3
internal flip flop used to enable or
disable the generation of INTR
PORT B O/P PB7 – PB0 signal.

PC 4,5 I/O PC5, PC4 :

The port C pins 5 and 4 are
general-purpose I/O pins that are
Mode 2 (Bidirectional Data Transfer) available for any purpose.

Port A is used for Bidirectional data transfer. Port B in either in mode 0 or 1. Port C is used
for Handshake signals .This functional configuration provides a means for communicating
with a peripheral device or structure on a single 8-bit bus for both transmitting and receiving
data (bidirectional bus I/O). “Handshaking” signals are provided to maintain proper bus flow.

 INTR : Interrupt request is an output signal that can be used to interrupt the MPU to
request the next data byte for output.
 OBF : Output Buffer Full is an output indicating that that output buffer contains data for
the bi-directional bus.
 ACK : An input from a peripheral device that must output a low when the peripheral
receives a data.
 STB : The strobe input loads data into the port A latch.
 PA0-PA7 PORT A

STB
PC4
PC5 IBF
INTR
PC3
OBF
PC7
PC6 ACK
I/O
PC0 – PC2

PORT B

 IBF : Input buffer full is an output signal indicating that the input latch contains
information for the external bi-directional bus.
 INTE : The interrupt enable signal is an internal flip flop used to enable or disable the
generation of INTR signal.
 PC2,PC1,PC0 : These port C pins are general-purpose I/O pins that are available for any

purpose.

2. Explain the 8251 USART with neat block diagram. Also explain its
mode word, command word and status word. (16) [Nov/Dec 2011]

A serial communications interface (SCI) is a device that enables the serial (one bit at
a time) exchange of data between a microprocessor and peripherals such as printers,
external drives, scanners. 8251 is a Universal Synchronous and Asynchronous Receiver
and Transmitter compatible with Intel’s processors. This chip converts the parallel data into
a serial stream of bits suitable for serial transmission. It is also able to receive a serial
stream of bits and convert it into parallel data bytes to be read by a microprocessor.
Basic Modes of data transmission

a) Simplex Mode: Data is transmitted only in one direction from the

transmitter to the receiver over a single communication channel.

b) Half Duplex Mode: Data transmission may take place in either direction, but
at a time data may be transmitted only in one direction.

c) Full Duplex Mode: Data transmission may take place in both directions

simultaneously. Serial Communication takes place in two methods,

Asynchronous data Transfer and Synchronous data Transfer.

Asynchronous Data Transfer

It allows data to be transmitted without the sender having to send a clock signal
to the receiver. Instead, special bits will be added to each word in order to synchronize
the sending and receiving of the data. When a word is given for Asynchronous
transmissions, a bit called the "Start Bit" is added to the beginning of each word that is to
be transmitted. The Start Bit is used to alert the receiver that a word of data is about to
be sent, and to force the clock in the receiver into synchronization with the clock in the
transmitter. The stop bit will be added at the end of the data.

Synchronous Data Transfer

The receiver knows when to “read” the next bit comi ng from the sender. This is
achieved by sharing a clock between sender and receiver. It is suitable for long
distance since exchange of data is done through one cable. Once the SYNC
character is detected 8251 starts receiving the data.

SYNC1 SYNC2 Data

Transmission Rate:
Bits per second: Number of bits transmitted per second.
Baud rate: It is a measurement of transmission speed in asynchronous communication,
it represents the number of bits/sec that are actually being sent over the serial link.

ARCHITECTURE OF 8251A

Data Bus Buffer: This tri-state, bi-directional, 8-bit buffer is used to interface 8251 to
the system data bus. Along with the data, control word, command words and status
information are also transferred through the Data Bus Buffer.
Read/Write Control Logic: This functional block accepts inputs from the system
control bus and generates control signals for overall device operation. It decodes
control signals on the control bus into signals which controls the internal and external
I/O bus. It contains the control word register and command word register that stores
the various controls formats for the device functional definition.

Transmit Buffer: The transmit buffer accepts parallel data from the CPU, adds the
appropriate framing information, serializes it, and transmits it on the TxD pin on the
falling edge of TxC. It has two registers: A buffer register to hold eight bits and an
output register to convert eight bits into a stream of serial bits. The CPU writes a
byte in the buffer register, which is transferred to the output register when it is empty.
The output register then transmits serial data on the TxD pin.
In the asynchronous mode the transmitter always adds START bit; depending
on how the unit is programmed, it also adds an optional even or odd parity bit, and
either 1,11/2, or 2 STOP bits. In synchronous mode no extra bits (other than parity, if
enable) are generated by the transmitter.

Transmit Control

It manages all activities associated with the transmission of serial data. It

accepts and issues signals both externally and internally to accomplish this function.

TxRDY (Transmit Ready) :This output signal indicates CPU that buffer register is empty
and the USART is ready to accept a data character. It can be used as an interrupt to the
system or, for polled operation, the CPU can check TxRDY using the status read
operation. This signal is reset when a data byte is loaded into the buffer register.

TxE (Transmitter Empty):This is an output signal. A high on this line indicates that
the output buffer is empty. In the synchronous mode, if the CPU has failed to load a
new character in time, TxE will go high momentarily as SYN characters are loaded
into the transmitter to fill the gap in transmission.

TxC (Transmitter Clock): This clock controls the rate at which characters are
transmitted by USART. In the synchronous mode TxC is equivalent to the baud rate,
and is supplied by the modem. In asynchronous mode TxC is 1, 16, or 64 times the
baud rate. The clock division is programmable. It can be programmed by writing
proper mode word in the mode set register.

Receive Buffer: The receiver accepts serial data on the RxD line converts this serial
data to parallel format, checks for bits or characters that are unique to the
communication technique and sends an “assembled” character to the CPU.
When 8251A is in the asynchronous mode and it is ready to accept a character, it
looks for a low level on the RxD line. When it receives the low level, it assumes that it is a
START bit and enables an internal counter. At a count equivalent to one-half of a bit time,
the RxD line is sampled again. If the line is still low, a valid START bit is detected and the
8251A proceeds to assemble the character. After successful reception of a START bit the
8251A receives data, parity and STOP bits, and then transfers the data on the
receiver input register. The data is then transferred into the receiver buffer register.
In the synchronous mode the receiver simply receives the specified number of data
bits and transfers them to the receiver input register and then to the receiver buffer register.

Receive Control
It manages all receiver-related activities. Along with data reception, it does
false start bit detection, parity error detection, framing error detection, sync detection
and break detection.

RxRDY (Receiver Ready):This is an output signal. It goes high (active), when the
USART has a character in the buffer register and is ready to transfer it to the CPU. This
line can be used either to indicate the status in the status register or to interrupt the
CPU. This signal is reset when a data byte from receiver buffer is read by the CPU.

RxC (Receiver Clock):This clock controls the rate at which the character is to be
received by USART in the synchronous mode. RxC is equivalent to the baud rate,
and is supplied by the modem. In asynchronous mod RxC is 1, 16, or 64 times the
baud rate. The clock division is programmable. It can be programmed by writing
proper mode word in the mode set register.

Modem Control
The 8251 has a set of control inputs and outputs that can be used to simplify the interface to
almost any modem. It provides control circuitry for the generation of RTS and DTR and the
reception of CTS and DSR. In addition, a general purpose inverted output and a general
purpose input are provided. The output is labelled DTR and the input is labelled DSR.
DTR can be asserted by setting bit 2 of the command instruction; DSR can be sensed as
bit 7 of the status register. When used as a modem control signal DTR indicates that the
terminal is ready to communicate and DSR indicates that it is ready for communication.
The receive control unit decides the receiver frequency as controlled by
theRXC input frequency. The receive control unit generates a receiver ready
(RXRDY) signal that may be used by the CPU for handshaking. This unit also
detects a break in the data string while the 8251 is in asynchronous mode. In
synchronous mode, the 8251 detects SYNC characters using SYNDET/BD pin.

Programming 8251
Prior to starting data transmission or reception the 8251 must be sent a set of control
words. This must be done after an external or internal reset. The control words are
split into two formats.

Mode Instruction Format and Command Word Format

Mode Instruction Format

The mode instruction format fixes up the baud rate, number of characters and stop
bits for transmission.
D1-D0 determines whether the USART is to operate in the synchronous (00) or
asynchronous mode. In the asynchronous mode, this field determines the division
factor for clock to decide the baud rate.
D3-D2 determines number of data bits in one character. With this 2 bit field we can
set character length from 5 bits to 8 bits.
D5-D4 controls the parity generation. The parity bit is added to the data bits only if
parity is enabled.
D7-D6 has two meanings depending on whether operation is to be in synchronous mode
or asynchronous mode. In asynchronous mode it controls the number of STOP bits to be
transmitted. In synchronous mode it decides whether to operate with external
synchronization or internal synchronization.

Command Instruction Format

It controls the operation of the USART. The command instruction controls the actual
operations of the selected format like enable transmit/receive, error reset and
modem control. A reset operation returns 8251 back to mode instruction format.

EH IR RTS ER SBRK RxE DTR TxE

EH : Enter Hunt Mode SBPRK : Send Break

Character IR : Internal Reset RxE : Receiver Enable
RTS : Request to Send DTR : Data Terminal Ready
ER: Error Reset TxE : Transmitter Empty

Status Word

The status word enables us to read the status of the device during its operation.

SYNDET
DSR BRKDET FE OE PE TxE RxRDY TxRDY

DSR : Data Set Ready FE: Framing Error

TxE : Transmitter Empty OE: Overrun Error
RxRDY : Receiver Ready PE: Parity Error
TxRDY: Transmitter Ready SYNDET/BRKDET: Sync Detect/Break Error

TxRDY Transmitter Ready : This output signal indicates to the CPU that the internal circuit
of the transmitter is ready to accept a new character for transmission from the CPU.

RxRDY Receiver Ready Output : This output indicates that the 8251A contains a
character to be read by the CPU.

TXE Transmitter Empty : The TXE signal can be used to indicate the end of a
transmission mode.

PE - Parity Error : At the time of transmission of data an even parity or odd parity is
inserted in the data stream. At the receiver end, if parity of the character does not
match with the predefined parity, parity error occurs.

OE - Overrun Error : In the receiver section received character is stored in the

receive buffer. The CPU is supposed to read this character before reception of the
next character. But if CPU fails in reading the character loaded in the receiver buffer
the next received character replaces the previous one and the overrun error occurs.
FE - Framing Error: If valid stop bit is not detected at the end of each character
framing error occurs.

SYNDET/BRKDET – Synchronous Detect / Break Detect :In synchronou s modes it is

Synchronous Detect and it outputs a High to indicate the chip has detected the SYCN.
Characters In "asynchronous mode," this is an output terminal which generates "high
level" output upon the detection of a "break" character if receiver data contains a "low-
level" space between the stop bits of two continuous characters. The terminal will be
reset, if RXD is at high level. After Reset is active, the terminal will be output at low level.

DSR - Data Set Ready : This is normally used to check if data set is ready when
communicating with a modem.

SIGNAL DESCRIPTION OF 8251

D0 – D7 : This is an 8-bit data bus used to read or write status, command word or
data from or to the 8251A.

C / D : (Control Word/Data): This input pin, together with RD and WR inputs, informs the
8251A that the word on the data bus is either a data or control word/status information. If
this pin is 1, control / status is on the bus, otherwise data is on the bus.

RD : This active-low input to 8251A is used to inform it that the CPU is reading either
data or status information from its internal registers.

WR :This is the "active low" input terminal which receives a signal for writing transmit
data and control words from the CPU into the 8251.

CLK : This input is used to generate internal device timings and is normally
connected to clock generator output. This input frequency should be at least 30
times greater than the receiver or transmitter data bit transfer rate.

RESET : A high on this input forces the 8251A into an idle state. The device will remain
idle till this input signal again goes low and a new set of control word is written into it.

TXC (Transmitter Clock Input) : This transmitter clock input controls the rate at which
the character is to be transmitted.

TXD (Transmitted Data Output) : This output pin carries serial stream of the transmitted
data bits along with other information like start bit, stop bits and parity bit, etc.

RXC (Receiver Clock Input) : This receiver clock input pin controls the rate at which
the character is to be received.

RXD (Receive Data Input) : This input pin of 8251A receives a composite stream of
the data to be received by 8251 A.

RxRDY (Receiver Ready Output) : This output indicates that the 8251A contains a
character to be read by the CPU.
TxRDY - Transmitter Ready : This output signal indicates to the CPU that the internal circuit
of the transmitter is ready to accept a new character for transmission from the CPU.

DSR - Data Set Ready : This is normally used to check if data set is ready when
communicating with a modem.

DTR - Data Terminal Ready : This is used to indicate that the device is ready to
accept data when the 8251 is communicating with a modem.

RTS - Request to Send Data : This signal is used to communicate with a modem.

TXE- Transmitter Empty : The TXE signal can be used to indicate the end of a
transmission mode.

SYNDET/BRKDET – Synchronous Detect / Break Detect :In synchronou s modes it is

Synchronous Detect and it outputs a High to indicate the chip has detected the SYCN.
Characters. In "asynchronous mode," this is an output terminal which generates "high
level" output upon the detection of a "break" character if receiver data contains a "low-
level" space between the stop bits of two continuous characters. The terminal will be
reset, if RXD is at high level. After Reset is active, the terminal will be output at low level.
 3. Explain how D/A and A/D interfacing done with 8086 with an application.(10)
[Apr/May 2015]

A DAC inputs a binary number and outputs an analog voltage or current signal. The
digital to analog converters converts binary numbers into their analog equivalent
voltages or currents. Several techniques are employed for digital to analog conversion.

Binary Analog
input DAC Output

Basic Concepts
For a 3 bit D/A Converter it has 3 digital input D2, D1 and Do and one output analog signal.
3
The three input lines can assume eight (2 = 8) input combinations from 000 to 111. D2 is
MSB and D0 is LSB. If the input ranges from 0 to 1V it can be divided into eight
equal parts(1/8 V) each successive input is 1/8 V higher than the previous
combinations as shown in the graph below.

The 3 bit D/A converter has eight possible combinations. If a converter has n input
n
lines it can have 2 input combinations.
Characteristics:
Resolution: It is a change in analog output for one LSB change in digital input.
n
It is given by(1/2 )*Vref. If n=8 (i.e.8-bit DAC)1/256*5V=39.06mV

Settling Time: It is the time required for the DAC to settle for a full scale code change.
If the full scale analog voltage is 1 V, the smallest unit or the LSB 001 is equivalent
n
to 1/2 of 1V. This is defined as resolution.
The DAC find applications in areas like digitally controlled gains, motor speed
control, programmable gain amplifiers, digital voltmeters, panel meters, etc. D/A
converter have many applications besides those where they are used with a
microcomputer. In a compact disk audio player for example a 14or16bit D/A
converter is used to convert the binary data read off the disk by a laser to an analog
audio signal. Most speech synthesizer integrated circuits contain a D/A converter to
convert stored binary data words into analog audio signals.

D/A Converter can be constructed by the following methods.

 Binary Weighted Resistor Network

 R-2R Ladder Network

Binary Weighted Resistor Network

The Binary Weighted DAC, which contains one resistor or current source for each bit of the
DAC connected to a summing point. These precise voltages or currents sum to the correct
output value. This is one of the fastest conversion methods but suffers from poor accuracy
because of the high precision required for each individual voltage or current. Such high-
precision resistors and current-sources are expensive, so this type of converter is usually
limited to 8-bit resolution or less.The output of the DAC is current which is converted to a
voltage by the operational amplifier at the output. If operational amplifier is used in a
difference configuration, both positive and negative values may be obtained. The input
resistors R1, R2 and R3 are selected in binary weighted proportion; each has double
the value of the previous resistor.
Rf = 1K

IT
R1 = 2K IT
D2
I1
R = 4K Io
2
D1
I2
R3 = 8K
D0
I3

If all three inputs are 1 V the output current is

Io = IT =I1 + I2 + I3
= Vin /R1 +Vin /R2 + Vin /R3
= Vin /1 K(½ + ¼ + 1/8)
= 0.875 mA.
The voltage output

Vo = - R f I T
= - (1 K ) (0.875)
= - 0.875 V
= |7/8 V|

It shows that for the input 111, the output is equal to either 7/8 mA or 7/7 V representing the
D/A conversion process. The diagram is redrawn as shown below, where the input voltage
Vin is replaced by Vref, which can be turned On or OFF by the switches.

Rf
2K 4k8k

The output Current Io can be generalized for any number of bits as

I o  Vref A 1
A A A A A A
2 3 4 5 6 7
A 8

R 2 4 8 16 32 64 128 256
where A1 to A8 can be 0 or 1

R-2R Ladder Network

The R-2R ladder DAC, which is a binary weighted DAC that uses a repeating cascaded
structure of resistor values R and 2R. This improves the precision due to the relative ease of
producing equal valued matched resistors (or current sources). However, wide converters
perform slowly due to increasingly large RC-constants for each added R-2R link.
DAC 0800 8-bit Digital to Analog converter
Pin Diagram of DAC 0800:

 DAC0800 is a monolithic 8-bit DAC manufactured by National semiconductor.

 It has settling time around 100ms
 It can operate on a range of power supply voltage i.e. from 4.5V to +18V.
Usually
+ -
the supply V is 5V or +12V. The V pin can be kept at a minimum of -12V.
 Resolution of the DAC is 39.06mV

DAC0800
The digital inputs are converted to current Iout, and by connecting a resistor to the Iout pin,
the output is converted to voltage. The total current I out is a function of the binary
numbers at the B0-B7

inputs of the DAC0808 and the reference current I ref , and it is given by:
D D D
I 
D 7D 6 D 5  4
3 D2 D1 0
   
ref 2 4 8 16 32 64 128 256

Usually reference current is 2mA. Ideally we connect the output pin to a resistor, convert this
current to voltage, and monitor the output on the scope. But this can cause inaccuracy;
hence an operational amplifier is used to convert the output current to voltage.

92
When chip select of DAC is enabled then DAC will convert digital input value given through
portliness PA0-PA7 to analog value. The analog output from DAC is a current quantity. This
current is converted to voltage using OPAMP based current-to-voltage converter. The
Output of DAC-0800 is fed to the operational amplifier to get the final output.

4. Draw and explain the block diagram of A to D converter. [Nov /Dec 2013]
Vin=2.25v, Vref=5v Number of data lines are 5. Convert the given analog quantity into its
equivalent output digital quantity.(8) [May/Jun 2014]
Explain how D/A and A/D interfacing done with 8086 with an application.(10)
[Apr/May 2015]
Vin=2.78v, Vref=5v Number of data lines are 6. Convert the given analog quantity
into its equivalent output digital quantity.(8) [Apr/May 2015]

Analog
Input ADC Binary
Output

An ADC inputs an analog electrical signal such as voltage or current and outputs a
binary number. The function of an A/D converter is to produce a digital word which
represents the magnitude of some analog voltage or current. The specifications for
an A/D converter are very similar to those for D/A converter. The resolution of an A/D
converter refers to the number of bits in the output binary word. An 8-bit converter for
example has a resolution of 1 part in 256. Accuracy and linearity specifications have
the same meaning for an A/D converter as they do for a D/A converter. Another
important specification for an ADC is its conversion time. This is defined as total
time required to convert analog signal into its digital output and is determined by the
conversion technique used and by the propagation delay in various circuits.

Algorithm for ADC interfacing contains the following steps.

 Ensure the stability of analog input, applied to the ADC.

 Issue start of conversion (SOC) pulse to ADC.
 Read end of conversion (EOC) signal to mark the end of conversion
process.
 Read digital data output of the ADC as equivalent digital output.

Many different types of analog-to-digital converters are available. Differing ADC types offer
varying resolution, accuracy and speed specifications. The most popular techniques used for
Analog-to-Digital conversion are
 Successive Approximation Method

 Dual Slope Method

SUCCESSIVE APPROXIMATION METHOD (ADC 0808/0809)

The method of generating input to the DAC is similar to weighing an unknown

material on a chemical balance with a set of such fractional weights as ½ g, 1/4g, 1/8
g etc. The weighing procedure with a heaviest weight (1/2 g) and subsequent weights
in decreasing order until the balance is tipped. The weight that tips the balance is
removed and the process is continued until the smallest weight is used.
In the case of 4 bit A/D/ converter bit D3bit is turned ON first and the output of the
DAC is compared with an analog signal. If the comparator changes the state indicating that
the output generated by d3 is larger than the analog signal bit D3 is turned OFF in the SAR
and the bit D2 is turned ON. The process continues until the input reaches bit D0.When bit
D3 is turned ON, the output exceeds the analog signal and therefore bit D 3 is turned
OFF. When the next three successive bits are turned ON, the output becomes
approximately equal to the analog signal.

0 1 1 1

Te O Te O Te O Te O
st FF st N st N st N

D3 D2 D1 D0
The analog to digital converter chips 0808 and 0809 are 8-bit CMOS,
successive approximation converters. Successive approximation technique isone of
the fast techniques for analog to digital conversion.
A successive approximation ADC employs a digital-to-analog converter (DAC) and a
single comparator. A special shift register called a Successive Approximation Register
(SAR) is used to control the DAC. It provisionally sets each bit of the DAC, beginning with
the most significant bit. The search compares the output of the DAC to the voltage being
measured. If setting a bit to one causes the DAC output to rise above the input voltage, that
bit is set to zero. Otherwise, that bit is left unaltered. This process is continued for all the bits
of the SAR. A Start Conversion (SOC) signal is provided, which when pulsed, initiates the
conversion cycle. An N-bit ADC requires N clock cycles for the conversion of an analog
input. When the conversion is complete, the binary result is placed on the parallel outputs of
the SAR, and the SAR sends out an End-Of Conversion (EOC) signal. For continuous
conversion, the EOC signal may be connected to the SOC signal.
 Comparator
Start
Vin
Control

Data
CLK Ready

4 Bit D/A Successive

Converter Approximation
Register

Output
Register
Analog
Reference

D3 D2 D1 D0
The time taken by the converter to calculate the equivalent digital data output
from the instant of the start of conversion is called conversion delay. It may be
noted that analog input voltage must be constant at the input of the ADC right from
the start of conversion till the end of conversion to get correct results.

Interfacing ADC 0808 with 8086 using 8255 ports.

Use port A of 8255 for transferring digital data output of ADC to the CPU and port
C for control signals. Analog input is present at I/P 2 of the ADC and a clock input
of suitable frequency is available for ADC. The analog input I/P 2 is used and
therefore address pins A,B,C should be 0,1,0 respectively to select I/P 2. The OE
and ALE pins are already kept at +5V to select the ADC and enable the outputs.
Port C upper acts as the input port to receive the EOC signal while port C lower
acts as the output port to send SOC to the ADC.
 Analog I/P

Address lines
selected C B A
I/P 0 0 0 0
I/P 1 0 0 1
I/P 2 0 1 0
I/P 3 0 1 1
I/P 4 1 0 0
I/P 5 1 0 1
I/P 6 1 1 0
I/P 7 1 1 1

Address lines for selecting analog inputs

IN7 - IN0 Digital 8-bit output with O7 MSB and O0
SC LSB Start of conversion signal pin
EOC End of conversion signal pin
OE Output latch enable pin, if high enables
CLK output Clock input for ADC
Vcc, GND Supply pins +5V and GND
Vref+ and Vref- Reference voltage positive (+5 Volts max.) and
Reference voltage negative (OV minimum).

DUAL SLOPE A/D CONVERTER

A dual-slope ADC (DS-ADC) integrates an unknown input voltage (VIN) for a fixed amount
of time (TINT), then "de-integrates" (TDE- INT) using a known reference voltage
(VREF) for a variable amount of time.
 At t<0, S1 is set to ground, S2 is closed, and counter=0.
At t=0 a conversion begins and S2is open, and S1is set so the input to the integrator is
Vin.
S1is held for TINT which is a constant predetermined time interval.
When S1is set the counter begins to count clock pulses, the counter resets to zero after
TINT
Vout of integrator at t = TINT is VIN TINT/RC is linearly proportional to VIN
At t = TINT S1is set so Vref is the input to the integrator which has the voltage V IN
TINT /RC stored in it.
The integrator voltage then drops linearly with a slope -V ref/RC.
A comparator is used to determine when the output voltage of the integrator
crosses zero When it is zero the digitized output value is the state of the counter.

5. Explain the different modes of operation of a timer.(8) [Apr/May 2015] [May/Jun 2014]

INTEL 8254 programmable Timer/ counter is a specially designed chip for µC

applications which require timing and counting operation. Each counter has two
inputs, clock and gate and one output. The clock is signal that helps in counting by
decrementing a preloaded value in the respective counter register. The gate serves
as an enable input. If the gate is maintained low the counting is disabled.

Data Bus Buffer:

The data bus buffer is bidirectional, 8-bit buffer and is used to interface the 8253 to the
system data bus. Data is transmitted or received by the buffer. The data bus buffer has three
basic functions, (i) Programming the modes of 8253. (ii) Loading the count value in times
(iii) Reading the count value from timers. The data bus buffer is connected to µ Ρ
which are also bidirectional. The data transfer is through these pins.
Read/ Write Control Logic:

It accepts inputs for the system control bus and in turn generate the control signals
for overall device operation.

CS : The chip select input is used to enable the communication between 8253 and
the microprocessor by means of data bus. A low on CS enables the data bus buffers,
while a high disables the buffer

RD &WR : The read (RD ) and write (WR) pins control the direction of data transfer on
the 8-bit bus. When the RD input pin is low. The CPU is inputting data from 8253 in the
form of counter value. When WR pins is low, then CPU is sending data to 8253 in the
form of mode information or loading counters. The RD &WR should not both be low
simultaneously. When RD & WR pins are HIGH, the data bus buffer is disabled.

A0 & A1: These two input lines are used for counter selection along with the CS pin.

A0 A1 Selected
0 0 Counter 0
0 1 Counter 1
1 0 Counter 2
1 1 Control Register
Counters: Each counter has three pins associated with it. They are CLK (CLK)
the gate (GATE) and the output (OUT).

CLK: Counters operate at the negative edge (1 to 0) of this clock input. If the signal
on this pin is generated by a fixed frequency oscillator then the user has
implemented a standard timer. If the input signal is a string of randomly occurring
pulses, then it is an implementation of a counter.

GATE: The gate input pin is used to initiate or enable counting. The exact effect of
the gate signal depends on which of the six modes of operation is chosen.

OUTPUT: The output pin provides an output from the timer. It actual use
depends on the mode of operation of the timer. The counter can be read “in the
fly” without inhibiting gate pulse or clock input.

Programming the Chip

All operations are decided by the control word loaded into the control register. For each
counters, there is a count register which is 16 bits in size. A number is written into this
register and stored in counter block. The maximum size of the number is FFFF H. The
operation of the counter occurs by creating a delay by decrementing this number down
to 0, the rate at which this occurs depends on the input clock frequency.
 Status Register

OUT NULL RW1 RW0 M2 M1 M0 BCD

OUT: The level of the OUT Pin M2,M1,M0 : Counter Mode

NULL = 1 if counter is 0 BCD : Logic 1 for BCD
counter RW1.RW0: Read/write Operation

Control Word Register:

It accepts information from the data bus buffer and stores it in a register. The
information stored in the register controls the operation mode, selection of binary or
BCD counting, Selection of counter and loading the values in the count register.

SCI SCO RL1 RL0 M2 M1 M0 BCD

BCD SCI SCO RL1 RL0

0 Binary 0 0 Select Counter 0 0 Counter Latching
0
1 BCD 0 1 Select Counter 0 1 Read LSB
1
1 0 Select Counter 1 0 Read MSB
2
1 1 Select Counter 1 1 Read LSb,MSB
3

M2 M1 M0
0 0 0 Mode 0
0 0 1 Mode 1
x 1 0 Mode 2
x 1 1 Mode 3
1 0 0 Mode 4
1 0 1 Mode 5

8253 OPERATING MODES

Mode 0 Interrupt on Terminal Count
Mode 1 Programmable One Shot
Mode 2 Rate Generator
Mode 3 Square Wave Generator
Mode 4 Software Triggered Strobe
Mode 5 Hardware Triggered Strobe

Mode 0 Interrupt on Terminal Count

The output goes high after the terminal count is reached. The counter stops if the Gate
is low. The timer count register is loaded with a count (say 6) when the WR line is made
low by the processor. The counter unit starts counting down with each clock pulse. The
output goes high when the register value reaches zero. In the meantime if the GATE is
made low the count is suspended at the value(3) till the GATE is enabled again.
Mode 1 Programmable One Shot
The output goes low with the Gate pulse for a predetermined period depending on the counter.
The counter is disabled if the GATE pulse goes momentarily low. The counter register is loaded
with a count value as in the previous case (say 5) The output responds to the GATE input and
goes low for period that equals the countdown period of the register (5 clock pulses in this
period). By changing the value of this count the duration of the output pulse can be changed. If
the GATE becomes low before the countdown is completed then the counter will be suspended
at that state as long as GATE is low. Thus it works as a mono-shot.

Mode 2 Rate Generator

In this mode it operates as a rate generator. The output goes high for a period that
equals the time of countdown of the count register (3 in this case). The output goes low
exactly for one clock period before it becomes high again. This is a periodic operation.
Mode 3 Square Wave Generator

It is similar to Mode 2 but the output high and low period is symmetrical. The output goes
high after the count is loaded and it remains high for period which equals the countdown
period of the counter register. The output subsequently goes low for an equal period and
hence generates a symmetrical square wave unlike Mode 2. The GATE has no role here.

Mode 4 Software Triggered Strobe

In this mode after the count is loaded by the processor the countdown starts. The
output goes low for one clock period after the countdown is complete. The
countdown can be suspended by making the GATE low This is also called a
software triggered strobe as the countdown is initiated by a program.
Mode 5 Hardware Triggered Strobe

The count is loaded by the processor but the countdown is initiated by the GATE
pulse. The transition from low to high of the GATE pulse enables count down. The
output goes low for one clock period after the countdown is complete

Watchdog timer

A Watchdog Timer is a circuit that automatically invokes a reset unless the system
being watched sends regular hold-off signals to the Watchdog.

5. Draw the block diagram of 8279 keyboard/ Display controller and explain hoe
to interface the Hex Key pad and 7- segment LEDs using 8279. (16 Marks)
[April/May 2010, April/May2017]
Intel’s 8279 is a general purpose keyboard display controller that simultaneously drives the
display of a system and interfaces a keyboard with the CPU, leaving it free for its routine task

Basics of Keyboard Interfacing:

Matrix keyboards are connected in a series of rows and columns. The important
tasks in interfacing a keyboard are 1) detecting a key press, 2) debounce the key
press and 3) encode the key to some standard code. Three tasks can be done with
hardware, software, or a combination of two, depending on the application.
Keyboards are organized in a matrix of rows and columns. The CPU accesses both
rows and columns through ports. Therefore, with two 8-bit ports, an 8 x 8 matrix of
keys can be connected to a microprocessor.
 When a key is pressed, a row and a column make a contact. Otherwise, there is no
connection between rows and columns. A 4x4 matrix connected to two ports. The
rows are connected to an output port and the columns are connected to an input
port.

Scanning and Identifying the Key:

It is the function of the microprocessor to scan the keyboard continuously to detect
and identify the key pressed

 To detect a pressed key, grounds all rows by providing 0 to the output

latch, then it reads the columns
 If the data read from columns is D3 – D 0 =1111, no key has been pressed and the
process continues till key press is detected
 If one of the column bits has a zero, this means that a key press has occurred For
example, if D3 – D 0 = 1101, this means that a key in the D1 column has been pressed
After detecting a key press, microprocessor will go through the process of identifying
the key
 Starting with the top row, the microprocessor grounds it by providing a low to row D0
only. It reads the columns, if the data read is all 1s, no key in that row is activated and
the process is moved to the next row
 It grounds the next row, reads the columns, and checks for any zero. This process
continues until the row is identified.
 After the key press detection, it waits 20ms for the key debounce and then scans the
 columns again
(a) It ensures that the first key press detection was not an erroneous one
due a spike noise
(b) The key press. If after the 20-ms delay the key is still pressed, it goes back
into the loop to detect a real key press
 Upon finding the zero, it pulls out the ASCII code for that key from the look-up table
otherwise, it increments the pointer to point to the next element of the look-up table
With the interrupt method the microcomputer doesn’t have to pay any
attention to the keyboard until it receives an interrupt signal.

Modes of Operation
 Two-Key Rollover. This means that if two keys are pressed at nearly the same time,
each key will be detected, debounced and converted to ASCII. The ASCII code for
the first key and a strobe signal for it will be sent out then the ASCII code for the
second key and a strobe signal for it will be sent out and compare this with two-key
lockout.
 2-Key Lockout Mechanism, one key must be released before the other key is
detected.
 N-Key Rollover Mode, if two keys are pressed almost simultaneously,
both key presses are detected and are placed in a queue

ARCHITECTURE OF 8279

The keyboard display controller 8279 provides:

a) A set of four scan lines and eight return lines for interfacing keyboards
b) A set of eight output lines for interfacing display.

I/O Control and Data Buffers :

The I/O control section controls the flow of data to/from the 8279. The data buffers
interface the external bus of the system with internal bus of 8279.The I/O section is
enabled only if CS is low. The pins A0, RD and WR select the command, status or
data read/write operations carried out by the CPU with 8279.

Control and Timing Register and Timing Control :

These registers store the keyboard and display modes and other operating conditions
programmed by CPU. The registers are written with A 0=1 and WR=0. The Timing and control
unit controls the basic timings for the operation of the circuit. Scan counter divide down the
operating frequency of 8279 to derive scan keyboard and scan display frequencies.

Scan Counter :
The scan counter has two modes to scan the key matrix and refresh the display. In the encoded
mode, the counter provides binary count that is to be externally decoded to provide the scan
lines for keyboard and display (Four externally decoded scan lines may drive upto 16 displays).
In the decode scan mode, the counter internally decodes the least significant 2
bits and provides a decoded 1 out of 4 scan on SL 0-SL 3( Four internally decoded scan lines
may drive upto 4 displays). The keyboard and display both are in the same mode at a time.

Return Buffers and Keyboard Debounce and Control:

If a key closer is detected, the keyboard debounce unit debounces the key entry (i.e. wait for
10 ms). After the debounce period, if the key continues to be detected. The code of key is
directly transferred to the sensor RAM along with SHIFT and CONTROL key status.

FIFO/Sensor RAM and Status Logic:

In keyboard or strobed input mode, this block acts as 8-byte first-in-first out (FIFO)
RAM. Each key code of the pressed key is entered in the order of the entry and in
the meantime read by the CPU, till the RAM become empty. The status logic
generates an interrupt after each FIFO read operation till the FIFO is empty. In
scanned sensor matrix mode, this unit acts as sensor RAM. Each row of the sensor
RAM is loaded with the status of the corresponding row of sensors in the matrix. If a
sensor changes its state, the IRQ line goes high to interrupt the CPU.
Display Address Registers and Display RAM :
The display address register holds the address of the word currently being written or
read by the CPU to or from the display RAM. The contents of the registers are
automatically updated by 8279 to accept the next data entry by CPU.

MODES OF OPERATION OF 8279

Input ( Keyboard ) Modes and Output (Display

)Modes Input ( Keyboard ) Modes

1. Scanned Keyboard Mode :

This mode allows a key matrix to be interfaced using either encoded or decoded scans. In the
encoded scan, an 8 x 8 keyboard or in decoded scan , a 4 x 8 Keyboard can be interfaced. The
code of key pressed with SHIFT and CONTROL status is stored into the FIFO RAM.

2. Scanned Sensor Matrix:

In this mode, a sensor array can be interfaced with 8279 using either encoder or decoder
scans. With encoder scan 8 x 8 sensor matrix or with decoder scan 4 x 8 sensor matrix can
be interfaced. The sensor codes are stored in the CPU addressable sensor RAM.

3. Strobed Input :
In this mode, if the control line goes low, the data on return lines, is stored in the
FIFO byte by byte.

Output (Display) Modes

Provides two output modes for selecting the display option.

Display Scan : 8279 provides 8 or 16 character multiplexed displays.

Display Scan : Options for data entry on the displays. The display data is entered
for display either from right side or from the left side.

DETAILS OF MODE OF OPERATION

1. Scanned Keyboard Mode with 2 Key Lockout

In this mode of operation, when a key is pressed, a debounce logic comes into
operation. The Key code of the identified key is entered into the FIFO with SHIFT
and CNTL status, provided the FIFO is not full.

2. Scanned Keyboard with N-key Rollover

In this mode, each key depression is treated independently. When a key is pressed, the
debounce circuit waits for 2 keyboard scans and then checks whether the key is still
depressed. If it is still depressed, the code is entered in FIFO RAM. Any number of keys can be
pressed simultaneously and recognized in the order, the Keyboard scan and record them.

3. Scanned Keyboard Special Error Mode

This mode is valid only under the N-Key rollover mode. This mode is programmed
using end interrupt/error mode set command. If during a single debounce period (two
Keyboard scan) two keys are found pressed, this is considered a simultaneous
depression and an error flag is set. This flag, if set, prevents further writing in FIFO
but allows generation of further interrupts to the CPU for FIFO read.

4. Sensor Matrix Mode

In the Sensor Matrix mode, the debounce logic is inhibited the 8-byte memory matrix. The
status of the sensor switch matrix is fed directly to sensor RAM matrix Thus the sensor RAM
bits contains the row-wise and column-wise status of the sensors in the sensor matrix.

DISPLAY MODES

There are various options of data display The first one is known as left entry mode or
type writer mode. Since in a type writer the first character typed appears at the left-most
position, while the subsequent characters appears successively to the right of the first
one. The other display format is known as right entry mode, or calculator mode, since
the calculator the first character entered appears at the right-most position and this
character is shifted one position left when the next character is entered.

1. Left Entry Mode

In the Left entry mode, the data is entered from the left side of the display unit.
Address0 of the display RAM contains the leftmost display character and address 15
of the RAM contains the rightmost display character.

2. Right Entry Mode

In the right entry mode, the first entry to be displayed is entered on the rightmost
display. The next entry is also placed in the right most display but after the previous
display is shifted left by one display position.

Command Words of 8279

All the command words or status words are written or read with A0 = 1 and CS = 0 to
or from 8279. This section describes the various command available in 8279.

a) Keyboard Display Mode Set – The format of the command word to select differe
nt modes of operation of 8279 is given below with its bit definitions.
 D7 D6 D5 D4 D3 D2 D1 D0

0 0 0 D D K K K
D
K K K Keyboard Modes
0 0 0 Encoded Scan 2 Key
Lockout
0 1 0 Decoded Scan 2 Key
Lockout
Encoded Scan N Key Roll
D Display Modes 0 1 0 Over
0 0 Eight 8 bit Character Left Entry Decoded Scan N Key Roll
0 1 1 Over
0 1 Sixteen 8 bit Character Left
1 0 0 Encoded Scan Sensor Matrix
Entry
1 1 0 Decoded Scan Sensor Matrix
1 0 Eight 8 bit Character Right Entry
Sixteen 8 bit Character Right 1 1 0 Strobed input Encoded Scan
1 1
Entry 1 1 1 Strobed input Decoded Scan
b) Read FIFO / Sensor RAM :
The format of this command is given below. This word is written to set up 8279 for reading
FIFO/ sensor RAM. In scanned keyboard mode, AI and AAA bits are of no use. The 8279
will automatically drive data bus for each subsequent read, in the same sequence, in which
the data was entered. In sensor matrix mode, the bits AAA select one of the 8 rows of RAM.
If AI flag is set, each successive read will be from the subsequent RAM location.

D7 D6 D5 D4 D3 D2 D1 D0
0 1 0 AI X A A A
AI – Auto increment
AAA – Address pointer to 8 bit FIFO RAM

c) Read Display RAM :

This command enables a programmer to read the display RAM data. The CPU writes
this command word to 8279 to prepare it for display RAM read operation. AI is auto
increment flag and AAAA, the 4-bit address points to the 16-byte display RAM that is to
be read. If AI=1, the address will be automatically, incremented after each read or write
to the Display RAM. The same address counter is used for reading and writing.

D7 D6 D5 D4 D3 D2 D1 D0
0 1 1 AI A A A A

d) Write Display RAM :

AI – Auto increment Flag. AAAA – 4 bit address for 16-bit display RAM to be written.
 D7 D6 D5 D4 D3 D2 D1 D0
1 0 0 AI A A A A

SIGNALS OF 8279

DB0-DB7 : These are bidirectional data bus lines. The data and command words to
and from the CPU are transferred on these lines.

CLK : This is a clock input used to generate internal timing required by 8279.

RESET : This pin is used to reset 8279. A high on this line reset 8279. After resetting
8279, its in sixteen 8-bit display, left entry encoded scan, 2-key lock out mode. The
clock prescaler is set to 31.

CS : Chip Select – A low on this line enables 8279 for normal read or write operations.

A0 : A high on this line indicates the transfer of a command or status information. A

low on this line indicates the transfer of data. This is used to select one of the
internal registers of 8279.

RD, WR(Input/Output ) READ/WRITE – These input pins enabl e the data buffers to
receive or send data over the data bus.

IRQ : This interrupt output lines goes high when there is a data in the FIFO sensor RAM.
The interrupt lines goes low with each FIFO RAM read operation but if the FIFO RAM
further contains any key-code entry to be read by the CPU, this pin again goes high
to generate an interrupt to the CPU.

Vss, Vcc : These are the ground and power supply lines for the circuit.

SL0-SL3-Scan Lines : These lines are used to scan the key board matrix and display digits.
These lines can be programmed as encoded or decoded, using the mode control register.

RL0 - RL7 - Return Lines : These are the input lines which are connected to one
terminal of keys, while the other terminal of the keys are connected to the decoded
scan lines. These are normally high, but pulled low when a key is pressed.

SHIFT : The status of the shift input lines is stored along with each key code in FIFO,
in scanned keyboard mode. It is pulled up internally to keep it high, till it is pulled low
with a key closure.

BD – Blank Display : This output pin is used to blank the display during digit
switching or by a blanking closure.

OUT A0 – OUT A3 and OUT B0 – OUT B3 – These are the output ports for two 16*4 or
16*8 internal display refresh registers. The data from these lines is synchronized with the
scan lines to scan the display and keyboard. The two 4-bit ports may also as one 8-bit port.

CNTL/STB- CONTROL/STROBED I/P Mode : In keyboard mode, this lines is used

as a control input and stored in FIFO on a key closure. The line is a strobed lines that
enters the data into FIFO RAM, in strobed input mode. It has an interrupt pull up. The
lines is pulled down with a key closer.

6. Describe the block diagram of 8259 Programmable Interrupt Controller

and its priority modes. (16) [Nov/Dec 2011]

Programmable interrupt controller 8259A which is able to handle a number of

interrupts at a time. This controller takes care of a number of simultaneously
appearing interrupt requests along with their types and priorities. This will reduce the
processor burden of handling interrupts. The 8259 A interrupt controller can

1) Handle eight interrupt inputs. This is equivalent to providing eight interrupt

pins on the processor in place of one INTR/INT pin.
2) All the eight interrupt are spaced at the interval of either four or eight location.
3) Resolve eight levels of interrupt priorities in a variety of modes.
 4) Mask each interrupt request individually.
5) Read the status of pending interrupts, in service interrupts, and masked interrupts.
6) Be set up to accept either the level triggered or edge triggered interrupt request.
7) Nine 8259 as can be cascaded in a master slave configuration to handle 64
interrupt inputs.

ARCHITECTURE OF 8259

Data Bus Buffer

This tristate bidirectional buffer interfaces internal 8259A bus to the microprocessor
system data bus. Control words, status and vector information pass through buffer
during read or write operations.

Read /Write Control Logic

This circuit accepts and decodes commands from the CPU. This also allows the
status of the 8259A to be transferred on to the data bus.
Interrupt Request Register (IRR)
The interrupts at IRQ input lines are handled by Interrupt Request Register internally. IRR
stores all the interrupt requests in it in order to serve them one by one on the priority basis.
In-Service Register (ISR)
This stores all the interrupt requests those are being served, i.e ISR keeps a track of
the requests being served.

Priority Resolver
This unit determines the priorities of the interrupt requests appearing simultaneously.
The highest priority is selected and stored into the corresponding bit of ISR during
INTA pulse. The IR0 has the highest priority while the IR7 has the lowest one

Interrupt Mask Register (IMR)

This register stores the bits required to mask the interrupt puts. IMR operates on IRR
at the direction of the Priority Resolver.

Control Logic
This block manages the interrupt and interrupt acknowledge signals to be sent to the CPU
for serving one of the eight interrupt requests. This also accepts interrupt acknowledge
(INTA) signal from CPU that causes the 8259A to release vector address on to the data bus.

Cascade Buffer/Comparator
This block stores and compares the ID's of all the 8259As used in the system. The
three I/O pins CAS0-2 are outputs when the 8259A is used as a master. The same
pins acts as input when 8259 is in slave mode.

The Interrupt sequence in an 8086-8259A system is described as follows:

1. One or more IR lines are raised high that set corresponding IRR bits.
2. 8259A resolves priority and sends an INT signal to CPU.
3. The CPU acknowledge with INTA pulse.
4. Upon receiving an INTA signal from the CPU, the highest priority ISR bit is set and the
corresponding IRR bit is reset. The 8259A does not drive data during this period.
5. The 8086 will initiate a second INTA pulse. During this period 8259A
releases an 8-bit pointer on to a data bus from where it is read by the CPU.
6. This completes the interrupt cycle. The ISR bit is reset at the end of the
second INTA pulse if automatic end of interrupt (AEOI) mode is programmed.
Otherwise ISR bit remains set until an appropriate EOI command is issued at
the end of interrupt subroutine.

PIN DIAGRAM DESCRIPTION

CS: This is an active low chip select signal for enabling RD and WR operations of 8259A.

WR: This pin is an active low write enable input to 8259A. This enables it to
accept command words from CPU.
RD: This is an active low read enable input to 8259A. A low on this line enables
8259A to release status onto the data bus of CPU.

D7-D0: These pins form a bidirectional data bus that carries 8-bit data either to control
word or from status word registers. This also carries interrupt vector information.

CAS0-CAS2 :Cascade Lines A single 8259A provides eight vectored interrupts. If

more interrupts are required, the 8259A is used in cascade mode.

PS*/EN*: This pin is a dual purpose pin. When the chip is used in buffered mode, it
can be used as buffer enable to control buffer transceivers. If this is not used in
buffered mode then the pin is used as input.

INT This pin goes high whenever a valid interrupt request is asserted. This is used to
interrupt the CPU and is connected to the interrupt input of CPU.

IR0-IR7(1nterrupt Requests)These pins act as inputs to accept interrupt requests to

the CPU. In edge triggered mode, an interrupt service is requested by raising an IR
pin from a low to a high state and holding it high until it is acknowledged

INTA* (Interrupt Acknowledge) This pin is an input used to strobe-in 8259A

interrupt vector data on to the data bus

Command Words of 8259A

The command words of 8259A are classified in two groups,

 Initialization Command Words (ICWs)

 Operation command words (OCWs)

Initialization Command Words (ICWs)

8259A must be initialized by writing two to four command words into the respective
command word registers. These are called as initialization command words (ICWs).

ICW1, ICW2, ICW3 ,ICW4 (Status Register)

ICW1 Initialization Command Word1

A0 D7 D6 D5 D4 D3 D2 D1 D0
0 A7 A6 A5 1 LTIM ADI SNGL IC4
 LTIM 1: Level triggered A7 – A5 : Interrupt Vector
Address
0 : Edge Triggered IC4 1: ICW4 Needed
ADI: Call address interval 0: Not Needed
1: Interval of 4 bytes SNGL 1: Single
0: Interval of 8 bytes 0 : Cascaded

The SNGL bit in ICW1 indicates whether the 8259A in the cascade mode or not. ADI refers
the interval of call address. LTIM refers whether it is edge triggered or level triggered.

ICW2 Initialization Command Word2

A0 D7 D6 D5 D4 D3 D2 D1 D0
1 T7 T6 T5 T4 T3 A10 A9 A8

In 8086 based system A15-A11 of the interrupt vector address are inserted in place of
T7 – T 3 respectively and the remaining three bits A 8, A9, A10 are selected
depending upon the interrupt level, i.e. from 000 to 111 for IR0 to IR7.

ICW3 Initialization Command Word3

The ICW 3 loads an 8-bit slave register. It detailed functions are as follows. In master
mode [ SP = 1 or in buffer mode M/S = 1 in ICW 4], the 8-bit slave register will be set
bit-wise to 1 for each slave in the system. The requesting slave will then release the
second byte of a CALL sequence. In slave mode [ SP=0 or if BUF =1 and M/S = 0 in
ICW4] bits D2 to D0 identify the slave, i.e. 000 to 111 for slave 1 to slave 8. The
slave compares the cascade inputs with these bits and if they are equal, the second
byte of the CALL sequence is released by it on the data bus.

Master Mode of ICW3

A0 D7 D6 D5 D4 D3 D2 D1 D0

1 S7 S6 S5 S4 S3 S2 S1 S0

Sn :1 has a slave : 0 Does not have a slave

 A0 D7 D6 D5 D4 D3 D2 D1 D0

1 0 0 0 0 0 ID2 ID1 ID0

ID2, ID1, ID0 : 000 to 111 for IR0 to IR7

ICW4 Initialization Command Word4

A0 D7 D6 D5 D4 D3 D2 D1 D0
1 0 0 0 SFNM BUF M/S AEOI µPM

The bit functions of ICW4 are described as follow:

SFNM: If BUF = 1, the buffered mode is selected. In the buffered mode, SP/EN acts
as enable output and the master/slave is determined using the M/S bit of ICW 4.
M/S: If M/S = 1, 8259A is a master. If M/S =0, 8259A is slave. If BUF = 0, M/S is to
be neglected.
AEOI: If AEOI = 1, the automatic end of interrupt mode is selected.
µPM : If the µPM bit is 0, the Mcs-85 system operation is selected and if µPM=1,
8086/88 operation is selected.

Operation command words (OCWs)

Once 8259A is initialized it is ready for its normal function. 8259A has its own ways of handling
the received interrupts called as modes of operation. These modes of operations can be selected
by programming, i.e. writing three internal registers called as operation command word registers.
The data written into them (bit pattern) is called as operation command words. In the three
operation command words OCW1, OCW2, OCW3 every bit corresponds to some operational
feature of the mode selected, except for a few bits those are either 1 or 0.

Operation Command Word 1 (OCW1)

OCW1 is used to mask the unwanted interrupt request and if it is 0 the request is enabled.

A0D7 D6 D5 D4 D3 D2 D1 D0

1 M7 M6 M5 M4 M3 M2 M1 M0

1: Mask Set 0: Mask Reset

Operation Command Word2 (OCW2)

In OCW2 the three bits, R, SL and EOI control the end of interrupt, the rotate mode and their
combinations as shown in fig below. The three bits L 2, L1 and L0 in OCW2
determine the interrupt level to be selected for operation, if SL bit is active i.e. 1.
 A0 D7 D6 D5 D4 D3 D2 D1 D0
1 R SL EOI 0 0 L2 L1 L0

R SL EOI
End of 0 0 1 Non Specific EOI Command
Interrupt 0 1 1 Specific EOI Command
1 0 1 Rotate on Non Specific EOI Command
Automatic
1 0 0 Rotate in Automatic EOI mode(Set)
Rotation
0 0 0 Rotate in Automatic EOI
mode(Clear)
1 1 1 Rotate on Specific EOI Command
Specific
1 1 0 Set priority Command
Rotation
0 1 0 No operation

L2 L1 L0 : 000 to 111 refers the Interrupt Request Numbers

Operation Command Word3 (OCW3)

A0 D7 D6 D5 D4 D3 D2 D1 D0
0 0 ESMM SMM 0 1 P RR RIS

P : 1 – Poll Command 0 – No Poll Command

ESMM SMM RR RIS

0 0 0 0
No Action No Action
0 1 0 1
1 0 Reset Special Mask 1 0Read IRR on Next RD Pulse
1 1 Set Special Mask 1 1Read ISR on Next RD Pulse

In operation command word 3 (OCW 3), if the ESMM bit, i.e. enable special mask
mode bit is set to 1, the SMM bit is enabled to select or mask the special mask
mode. When ESMM bit is 0 the SMM bit is neglected. If the SMM bit .i.e. special
mask mode bit is 1, the 8259A will enter special mask mode provided ESMM=1. If
ESMM=1 and SMM=0, the 8259A will return to the normal mask mode.

OPERATING MODES OF 8259

Fully Nested Mode : This is the default mode of operation of 8259A. IR0 has the highest
priority and IR7 has the lowest one. When interrupt request are noticed, the highest
priority request among them is determined and the vector is placed on the data bus. The
corresponding bit of ISR is set and remains set till the microprocessor issues an EOI
command just before returning from the service routine or the AEOI bit is set. If the
ISR ( in service ) bit is set, all the same or lower priority interrupts are inhibited but
higher levels will generate an interrupt, that will be acknowledge only if the
microprocessor interrupt enable flag IF is set. The priorities can afterwards be
changed by programming the rotating priority modes.

End of Interrupt (EOI) : The ISR bit can be reset either with AEOI bit of ICW1 or by
EOI command, issued before returning from the interrupt service routine. There are
two types of EOI commands specific and non-specific. When 8259A is operated in
the modes that preserve fully nested structure, it can determine which ISR bit is to be
reset on EOI. When non-specific EOI command is issued to 8259A it will be
automatically reset the highest ISR bit out of those already set.

Automatic Rotation : This is used in the applications where all the interrupting devices
are of equal priority. In this mode, an interrupt request IR level receives priority after it is
served while the next device to be served gets the highest priority in sequence. Once all
the devices are served like this, the first device again receives highest priority.

Automatic EOI Mode : Till AEOI=1 in ICW 4, the 8259A operates in AEOI mode. In
this mode, the 8259A performs a non-specific EOI operation at the trailing edge of
the last INTA pulse automatically. This mode should be used only when a nested
multilevel interrupt structure is not required with a single 8259A.

Specific Rotation : In this mode a bottom priority level can be selected, using L 2, L1 and L0
in OCW 2 and R=1, SL=1, EOI=0. The selected bottom priority fixes other priorities. If IR 5 is
selected as a bottom priority, then IR 5 will have least priority and IR4 will have a next higher
priority. Thus IR 6 will have the highest priority. These priorities can be changed during an
EOI command by programming the rotate on specific EOI command in OCW2.

Specific Mask Mode: In specific mask mode, when a mask bit is set in OCW1, it inhibits
further interrupts at that level and enables interrupt from other levels, which are not masked.

Edge and Level Triggered Mode : This mode decides whether the interrupt should
be edge triggered or level triggered. If bit LTIM of ICW1 =0 they are edge triggered,
otherwise the interrupts are level triggered.

READING 8259 STATUS

The status of the internal registers of 8259A can be read using this mode. The OCW
3 is used to read IRR and ISR while OCW1 is used to read IMR. Reading is possible
only in no polled mode.

Poll Command : In polled mode of operation, the INT output of 8259A is neglected,
though it functions normally, by not connecting INT output or by masking INT input of the
microprocessor. The poll mode is entered by setting P=1 in OCW3. The 8259A is polled by
using software execution by microprocessor instead of the requests on INT input. The
8259A treats the next RD pulse to the 8259A as an interrupt acknowledge. An appropriate
ISR bit is set, if there is a request. The priority level is read and a data word is placed on to
data bus, after RD is activated. A poll command may give more than 64 priority levels.

Special Fully Nested Mode : This mode is used in more complicated system, where
cascading is used and the priority has to be programmed in the master using ICW 4. this is
somewhat similar to the normal nested mode. • In th is mode, when an interrupt request
from a certain slave is in service, this slave can further send request to the master, if the
requesting device connected to the slave has higher priority than the one being currently
served. In this mode, the master interrupt the CPU only when the interrupting device has a
higher or the same priority than the one current being served. In normal mode, other
requests than the one being served are masked out. When entering the interrupt service
routine the software has to check whether this is the only request from the slave. This is
done by sending a non-specific EOI can be sent to the master, otherwise no EOI should be
sent. This mode is important, since in the absence of this mode, the slave would interrupt
the master only once and hence the priorities of the slave inputs would have been disturbed.

Buffered Mode: When the 83259A is used in the systems where bus driving buffers
are used on data buses. The problem of enabling the buffers exists. The 8259A
sends buffer enable signal on SP/ EN pin, whenever data is placed on the bus.

Cascade Mode : The 8259A can be connected in a system containing one master
and eight slaves (maximum) to handle upto 64 priority levels. The master controls
the slaves using CAS 0-CAS 2 which act as chip select inputs (encoded) for slaves.
In this mode, the slave INT outputs are connected with master IR inputs. When a
slave request line is activated and acknowledged, the master will enable the slave to
release the vector address during second pulse of INTA sequence.

7. How to interface a DMA controller with a microprocessor? Explain how

DMA controller transfers large amount of data from one memory locations to
another memory locations? [Nov/Dec 2014].

The Direct Memory Access or DMA mode of data transfer is the fastest among all the modes
of data transfer. In this mode, the device may transfer data directly to/from memory without
any interference from the CPU. The device requests the CPU (through a DMA controller) to
hold its data, address and control bus, so that the device may transfer data directly to/from
memory. The DMA data transfer is initiated only after receiving HLDA signal from the CPU.

Intel’s 8257 is a four channel DMA controller designed to be interfaced with their family of
microprocessors. The 8257, on behalf of the devices, requests the CPU for bus access
using local bus request input i.e. HOLD in minimum mode. In maximum mode of the
microprocessor RQ/GT pin is used as bus request input. On receiving the HLDA signal (in
minimum mode) or RQ/GT signal (in maximum mode) from the CPU, the requesting devices
gets the access of the bus, and it completes the required number of DMA cycles for the data
transfer and then hands over the control of the bus back to the CPU.
INTERNAL ARCHITECTURE OF 8257

The chip support four DMA channels, i.e. four peripheral devices can independently
request for DMA data transfer through these channels at a time. The DMA controller
has 8-bit internal data buffer, a read/write unit, a control unit, a priority resolving unit
along with a set of registers. The chip support four DMA channels, i.e. four peripheral
devices can independently request for DMA data transfer through these channels at
a time. The DMA controller has 8-bit internal data buffer, a read/write unit, a control
unit, a priority resolving unit along with a set of registers.

Register Organization of 8257

The 8257 performs the DMA operation over four independent DMA channels. Each
of four channels of 8257 has a pair of two 16-bit registers, viz. DMA address register
and terminal count register. There are two common registers for all the channels,
namely, mode set register and status register. Thus there are a total of ten registers.
The CPU selects one of these ten registers using address lines Ao-A3.

DMA Address Register

Each DMA channel has one DMA address register. The starting address of the memory
block which will be accessed by the device is first loaded in the DMA address register.
The device that wants to transfer data over a DMA channel, will access the block of the
memory with the starting address stored in the DMA Address Register.

Terminal Count Register

Each of the four DMA channels of 8257 has one terminal count register (TC). This
16-bit register is used for ascertaining that the data transfer through a DMA channel
ceases or stops after the required number of DMA cycles. The low order 14-bits of
the terminal count register are initialized with the binary equivalent of the number of
required DMA cycles minus one. After each DMA cycle, the terminal count register
content will be decremented by one and finally it becomes zero after the required
number of DMA cycles are over.
 The bits 14 and 15 of this register indicate the type of the DMA operation (transfer).
If the device wants to write data into the memory, the DMA operation is called DMA
write operation. Bit14 of the register in this case will be set to one and bit 15 will be
set to zero. Table gives detail of DMA operation selection and corresponding bit
configuration of bits 14 and 15 of the TC register.

Mode Set Register

The mode set register is used for programming the 8257. The function of the mode set
register is to enable the DMA channels individually and also to set the various modes of
operation. The DMA channel should not be enabled till the DMA address register and the
terminal count register contain valid information, otherwise, an unwanted DMA request may
initiate a DMA cycle, probably destroying the valid memory data. The bits B 0- B3 enable
one of the four DMA channels of 8257. for example, if B 0 is ‘1’, channel 0 is enabled.
 Bit 15 Bit 14 Types of DMA Operation
0 0 Verify DMA Cycle
0 1 Write DMA Cycle
1 0 Read DMA Cycle
1 1 Illegal

If B4 is set, rotating priority is enabled, otherwise, the normal, i.e. fixed priority is enabled If
the TC STOP bit is set, the selected channel is disabled after the terminal count condition is
reached, and it further prevents any DMA cycle on the channel. To enable the channel
again, this bit must be reprogrammed. If the TC STOP bit is programmed to be zero, the
channel is not disabled, even after the count reaches zero and further request are allowed
on the same channel. The auto load bit, if set, enables channel 2 for the repeat block
chaining operations, without immediate software intervention between the two successive
blocks. The channel 2 registers are used as usual, while the channel 3 registers are used to
store the block reinitialisation parameters, i.e. the DMA starting address and terminal count.
After the first block is transferred using DMA, the channel 2 registers are reloaded with the
corresponding channel 3 registers for the next block transfer, if the update flag is set. The
extended write bit, if set to ‘1’, extends the duration of MEMW and IOW signals by activating
them earlier, this is useful in interfacing the peripherals with

AL TCS EW RP EN3 EN2 EN1 EN0

AL : 1 = Enable Auto Reload EN0 : Channel 0

0 = Disable Auto Reload EN1 : Channel
1 TCS : 1 = Stop DMA on terminal Count EN2 :
Channel 2 EW : 1 = Extended Write selection EN3 :
Channel 0
0 = Normal write selection 1 = Enable
RP : 1 = Rotating Priority 0= Disable
0 = Fixed Priority
different access times. If the peripheral is not accessed within the stipulated time, it
is expected to give the ‘NOT READY’ indication to 8257 , to request it to add one or
more wait states in the DMA CYCLE. The mode set register can only be written into.
Status Register
The status register of 8257 is shown in figure. The lower order 4-bits of this register contain the
terminal count status for the four individual channels. If any of these bits is set, it indicates that
the specific channel has reached the terminal count condition. If the update flag is set, the
contents of the channel 3 registers are reloaded to the corresponding registers of channel 2
whenever the channel 2 reaches a terminal count condition, after transferring one block and the
next block is to be transferred using the autoload feature of 8257.

D7 D6 D5 D4 D3 D2 D1 D0

D0 TC Status Channel D2 TC Status Channel 2

0 D3 TC Status Channel 3
D1 TC Status Channel
1
Data Bus Buffer, Read/Write Logic, Control Unit and Priority Resolver

The 8-bit. Tristate, bidirectional buffer interfaces the internal bus of 8257 with the external system
bus under the control of various control signals. In the slave mode, the read/write logic accepts
the I/O Read or I/O Write signals, decodes the Ao-A3 lines and either writes the contents of the
data bus to the addressed internal register or reads the contents of the selected register
depending upon whether IOW or IOR signal is activated. In master mode, the read/write logic
generates the IOR and IOW signals to control the data flow to or from the selected peripheral.
The control logic controls the sequences of operations and generates the required control signals
like AEN, ADSTB, MEMR, MEMW, TC and MARK along with the address lines A4-A7, in master
mode. The priority resolver resolves the priority of the four DMA channels depending upon
whether normal priority or rotating priority is programmed.

MODES OF OPERATION

Single mode
In single mode only one byte is transferred per request. For every transfer, the
counting register is decremented and address is incremented or decremented
depending on programming.

Block transfer mode

The transfer is activated by DREQ which can be deactivated once acknowledged by
DACK. The transfer continues until end of process EOP (either internal or external)
is activated which will trigger terminal count TC to the card. Auto-initialization may be
programmed in this mode.

Demand transfer mode

The transfer is activated by DREQ and acknowledged by DACK and continues until
either TC, external EOP or DREQ goes inactive. Only TC or external EOP may
activate auto-initialization if this is programmed.
SIGNAL DESCRIPTION OF 8257

DRQo-DRQ3 : These are the four individual channel DMA request inputs, used by the
peripheral devices for requesting the DMA services. The DRQ o has the highest
priority while DRQ3 has the lowest one, if the fixed priority mode is selected.

DACKo-DACK3 : These are the active-low DMA acknowledge output lines which inform
the requesting peripheral that the request has been honoured and the bus is
relinquished by the CPU. These lines may act as strobe lines for the requesting devices.

Do-D7: These are bidirectional, data lines used to interface the system bus with the
internal data bus of 8257. These lines carry command words to 8257 and status
word from 8257, in slave mode, i.e. under the control of CPU. The data over these
lines may be transferred in both the directions. When the 8257 is the bus master
(master mode, i.e. not under CPU control), it uses Do-D7 lines to send higher byte of
the generated address to the latch. This address is further latched using ADSTB
signal. the address is transferred over Do-D7 during the first clock cycle of the DMA
cycle. During the rest of the period, data is available on the data bus.

IOR: This is an active-low bidirectional tristate input line that acts as an input in the
slave mode. In slave mode, this input signal is used by the CPU to read internal
registers of 8257.this line acts output in master mode. In master mode, this signal is
used to read data from a peripheral during a memory write cycle.

IOW : This is an active low bidirection tristate line that acts as input in slave mode to load the
contents of the data bus to the 8-bit mode register or upper/lower byte of a 16-bitDMA
address register or terminal count register. In the master mode, it is a control output that
loads the data to a peripheral during DMA memory read cycle (write to peripheral).
CLK: This is a clock frequency input required to derive basic system timings for the
internal operation of 8257.

RESET : This active-high asynchronous input disables all the DMA channels by
clearing the mode register and tristates all the control lines.

Ao-A3: These are the four least significant address lines. In slave mode, they act as
input which select one of the registers to be read or written. In the master mode,
they are the four least significant memory address output lines generated by 8257.

CS: This is an active-low chip select line that enables the read/write operations
from/to 8257, in slave mode. In the master mode, it is automatically disabled to
prevent the chip from getting selected (by CPU) while performing the DMA operation.

A4-A7 : This is the higher nibble of the lower byte address generated by 8257 during
the master mode of DMA operation.

READY: This is an active-high asynchronous input used to stretch memory read and write
cycles of 8257 by inserting wait states. This is used while interfacing slower peripherals..

HRQ: The hold request output requests the access of the system bus. In the
noncascaded 8257 systems, this is connected with HOLD pin of CPU. In the
cascade mode, this pin of a slave is connected with a DRQ input line of the master
8257, while that of the master is connected with HOLD input of the CPU.

HLDA : The CPU drives this input to the DMA controller high, while granting the bus to the
device. This pin is connected to the HLDA output of the CPU. This input, if high, indicates to
the DMA controller that the bus has been granted to the requesting peripheral by the CPU.

MEMR: This active –low memory read output is used to re ad data from the
addressed memory locations during DMA read cycles.

MEMW : This active-low three state output is used to write data This active-low three
state output is used to write data to the addressed memory location during DMA
write operation. ADST : This output from 8257 strobes the higher byte of the memory
address generated by the DMA controller into the latches.

AEN: This output is used to disable the system data bus and the control the bus driven
by the CPU, this may be used to disable the system address and data bus by using the
enable input of the bus drivers to inhibit the non-DMA devices from responding during
DMA operations. If the 8257 is I/O mapped, this should be used to disable the other I/O
devices, when the DMA controller addresses is on the address bus.

TC: Terminal count output indicates to the currently selected peripherals that the present
DMA cycle is the last for the previously programmed data block. If the TC STOP bit in the
mode set register is set, the selected channel will be disabled at the end of the DMA cycle.
The TC pin is activated when the 14-bit content of the terminal count register of the selected
channel becomes equal to zero. The lower order 14 bits of the terminal count register are to
be programmed with a 14-bit equivalent of (n-1), if n is the desired number of DMA cycles.

MARK : The modulo 128 mark output indicates to the selected peripheral that the
current DMA cycle is the 128th cycle since the previous MARK output. The mark will
be activated after each 128 cycles or integral multiples of it from the beginning if the
data block (the first DMA cycle), if the total number of the required DMA cycles (n) is
completely divisible by 128.

Vcc : This is a +5v supply pin required for operation of the circuit. GND : This is a
return line for the supply (ground pin of the IC).

8. Draw the block diagram of traffic light control system using 8086. [Apr/May
2015]

Vehicular traffic at intersecting streets is typically controlled by traffic control lights.

The function of traffic lights requires sophisticated control and coordination to ensure
that traffic moves as smoothly and safely as possible. Microprocessor is programmed in
such a way to adjust their timing and phasing to meet changing traffic conditions. Traffic
congestion is a severe problem in many modern cities around the world. Traffic
congestion has been causing many critical problems and challenges in the major and
most populated cities. To travel to different places within the city is becoming more
difficult for the travellers in traffic. Due to these congestion problems, people lose time,
miss opportunities, and get frustrated. Traffic congestion directly impacts the companies.
Due to traffic congestions there is a loss in productivity from workers, trade opportunities
are lost, delivery gets delayed, and thereby the costs goes on increasing.
Traffic lights, which may also be known as stoplights, traffic lamps, traffic signals, signal
lights, robots or semaphore, are signalling devices positioned at road intersections,
pedestrian crossings and other locations to control competing flows of traffic.

ABOUT THE COLORS OF TRAFFIC LIGHT CONTROL

Traffic lights alternate the right of way of road users by displaying lights of a standard color
red, yellow/amber, and green. Illumination of the red signal prohibits any traffic from
proceeding. Usually, the red light contains some orange in its hue, and the green light
contains some blue, for the benefit of people with red-green color blindness, and "green"
lights in many areas are in fact blue lenses on a yellow light (which together appear green).

INTERFACING TRAFFIC LIGHT WITH 8086

The Traffic light controller section consists of 12 Nos. of LED’s arranged by 4Lanes
in Traffic light interface card. Each lane has Go(Green), Listen(Yellow) and
Stop(Red) LED is being placed.
PIN ASSIGNMENT WITH 8086

LAN 8086
MODULES
Direction LINES
PA.0 GO
SOUTH PA.1 LISTEN
PA.2 STOP
PA.3 GO
EAST PA.4 LISTEN
PA.5 STOP
PA.6 GO
NORTH PA.7 LISTEN
PB.0 STOP
PB.1 GO
WEST PB.2 LISTEN
PB.3 STOP
13-16 NC
PWR 17,19 Vcc

18,20 Gnd

Circuit Diagram To Interface Traffic Light With 8086

Assembly Program To Interface Traffic Light With 8086

START: MOV BX, 1200H

MOV CX, 0008H
MOV AL,[BX]
MOV DX, CONTROL PORT
OUT DX, AL
INC BX
NEXT: MOV AL,[BX]
MOV DX, PORT A
OUT DX,AL
INC BX
MOV AL,[BX]
MOV DX,PORT B
OUT DX,AL
CALL DELAY
INC BX
LOOP NEXT
JMP START

DELAY: PUSH CX
MOV CX,0005H
REPEAT: MOV DX,0FFFFH
LOOP2: DEC DX
JNZ LOOP2
LOOP REPEAT
POP CX
RET

LOOKUP TABLE

1200 80H

1201 21H,09H,10H,00H (SOUTH WAY)

1205 0CH,09H,80H,00H (EAST WAY)

1209 64H,08H,00H,04H (NORTH WAY)

120D 24H,03H,02H,00H (WEST WAY)