ECE - (4 Year B.

Tech Programme) - COURSE CURRICULUM R-19

III Year Course structure
Semester - I
Course Title of the course CAT Periods Sessionals Semester Total Credits
Code L T P E O Total Marks end Exam Marks
marks
ECE311 Open Elective- I OE 3 0 0 1 2 6 40 60 100 3
Professional
ECE312 PE 3 0 0 1 2 6 40 60 100 3
Elective-1
Digital
ECE313 PC 3 0 0 1 5 9 40 60 100 3
communications
Embedded systems
ECE314 PC 3 0 0 1 5 9 40 60 100 3
and IOT
Integrated circuits
ECE315 PC 3 0 0 1 5 9 40 60 100 3
and Applications
Antennas and
ECE316 PC 3 0 0 1 5 9 40 60 100 3
Wave Propagation
Quantitative
ECE317 Aptitude & Verbal HS 0 0 3 1 3 7 100 0 100 1.5
Aptitude-I
Embedded systems
ECE318 PC 0 0 3 0 1 4 50 50 100 1.5
and IOT lab
AC& DC
ECE319 PC 0 0 3 0 1 4 50 50 100 1.5
Laboratory
Total 18 0 9 7 29 63 440 460 900 22.5
Semester – II
Course Title of the course Cate Periods Sessionals Semester Total Credits
Code gory L T P E O Total Marks end Exam Marks
marks
ECE321 Open Elective- II OE 3 0 0 1 2 6 40 60 100 3

Professional
ECE322 PE 3 0 0 1 4 8 40 60 100 3
Elective-2
Professional
ECE323 PE 3 0 0 1 4 8 40 60 100 3
Elective-3

ECE324 Data structures ES 3 0 0 1 5 9 40 60 100 3

Digital signal
ECE325 PC 3 0 0 1 5 9 40 60 100 3
processing

ECE326 VLSI Design PC 3 0 0 1 5 9 40 60 100 3

Quantitative
ECE327 Aptitude-II & HS 0 0 2 2 3 7 100 0 100 1.5
Softskills

ECE328 ICA Laboratory PC 0 0 3 0 1 4 50 50 100 1.5

ECE329 DS lab ES 0 0 3 0 1 4 50 50 100 1.5

Total 18 0 8 8 30 64 440 460 900 22.5

 DIGITAL IC DESIGN USING HDL
ECE 322(a) Credits:3
Instruction : 3 periods & 1 E/Week Sessional Marks:40
End Exam : 3 Hours End Exam Marks:60
Pre -requisites: Digital Electronics, Computer Architecture & Organization, Integrated Circuits and
Applications
Course Outcomes:
By the end of the course, the student will be able to:
1. Interpret the importance of EDA tools and its flow for VLSI designs

2. Model logic gates ,half adder, full adder ,various digital blocks by using modern tools with HDL

3. Construct verilog HDL models for combinational and sequential circuits using gate level,
behavioral level and dataflow level
4. Build CMOS circuits using Verilog switch level programming

5. Apply design rule checks and timing parameters to digital circuits and model the state machines

SYLLABUS
UNIT – I [10 Periods]
INTRODUCTION TO ELECTRONIC DESIGN AUTOMATION
Introduction, FPGA Design flow, ASIC Design flow, architectural design, logic design, Physical design
of IC. Simulation, verification and testing. EDA Tools: FPGA Design, ASIC Design.
FPGA Based Front End Design-Implementation, FPGA configuration, User constraints Xilinx 3000
Series FPGA architecture, ALTERA FLEX 10K Series CPLD architecture

UNIT – II [10 Periods]

VERILOG LANGUAGE CONSTRUCTS
Verilog as HDL, Levels of Design Description, Concurrency, Simulation and Synthesis, Functional
Verification, System Tasks, Programming Language Interface (PLI), Module, Simulation and Synthesis
Tools, Test Benches. Keywords, Identifiers, White Space Characters, Comments, Numbers, Strings,
Logic Values, Strengths, Data Types, Scalars and Vectors, Parameters, Memory, Operators, System
Tasks, Exercises

UNIT – III [10 Periods]

GATE LEVEL MODELING AND DATAFLOW MODELING
AND Gate Primitive, Module Structure, Other Gate Primitives, Tri-State Gates, Array of Instances of
Primitives, Additional Examples, Design of Flip-flops with Gate Primitives, Delays, Strengths and
Contention Resolution, Net Types, Design of Basic Circuits, Exercises. Continuous Assignment
Structures, Delays and Continuous Assignments, Assignment to Vectors, Operators.

UNIT – IV [10 Periods]

BEHAVIORALAND SWITCH LEVEL MODELING
Introduction, Operations and Assignments, Functional Bifurcation, Initial Construct, Always Construct,
Examples, Assignments with Delays, Wait construct, Multiple Always Blocks, Designs at Behavioral
Level, Blocking and Non blocking Assignments, The case statement, Simulation Flow. If and if-else
constructs, repeat construct, for loop, , while loop, forever loop, parallel blocks, force-release construct,
Event. Basic Transistor Switches, CMOS Switch, Bi-directional Gates, Time Delays with Switch
Primitives, Instantiations with Strengths and Delays, Strength Contention with Tri-reg Nets, Exercises
UNIT – V [10 Periods]
SYSTEM TASKS, FUNCTIONS, UDP AND SM CHARTS
Introduction, Parameters, Path Delays, Module Parameters, System Tasks and Functions. File Based
Tasks and Functions, Compiler Directives, Hierarchical Access, General observations, Exercises.
User-Defined Functions, Tasks and Primitives-Introduction, Function, Tasks, User- Defined Primitives
(UDP), FSM Design (Moore and Mealy Machines), State Machine Charts, Derivation of SM Charts,
Realization of SM Charts, Examples based on SM charts

TEXT BOOKS:
1. T.R. Padmanabhan and B. Bala Tripura Sundari,” Design through Verilog HDL” WSE, IEEE
Press, 2004(UNIT-I,II,III,IV &V)
2. J. Bhaskar” A Verilog Primier” ,First edition ,BSP, 2003(UNIT-I,II,III,IV &V)

REFERENCE BOOKS:
1. Brown and ZvonkoVranesic Stephen” Fundamentals of Logic Design with Verilog ”TMH,
2005.
2. Michael D. Ciletti “Advanced Digital Design with Verilog HDL “,Second edition, PHI, 2005.
 INFORMATION THEORY AND CODING
ECE 323(a) Credits:3
Instruction: 3 Periods & 1 E/week Sessional Marks:40
End Exam: 3 Hours End Exam Marks:60

Prerequisites: Digital Electronics, Digital Communications.

Course Outcomes:
At the end of the course, students will be able to
1. Evaluate the parameters of Digital data over discrete channels / Calculate information
entropy and mutual information for discrete channel.
2. Compare efficiency of Source coding techniques / Decide an efficient source coding for a
given information source.
3. Implement linear block coding-decoding and comprehend error detection and correction.
4. Implement Cyclic coding-decoding and comprehend error detection and correction.
5. Design convolution encoder and perform Convolution coding-decoding.

SYLLABUS
UNIT I [10 Periods]
INFORMATION THEORY
Measure of Information and its Properties, Entropy and its Properties, Joint Entropy, Marginal
Entropy, Conditional Entropy, Information rate, Mutual Information and its Properties, Discrete
Memory less Channels, Rate of Information over Discrete Channels, Capacity of Binary
Symmetric Channel.

UNIT II [10Periods]
SOURCE CODING
Shannon Fano Algorithm, Huffman Binary Coding, Huffman Ternary Coding, Huffman
Quaternary Coding, Shannan Hartley Theorem, Trade-off Between S/N Ratio and Bandwidth,
Ideal Communication system.

UNIT III [10 Periods]

LINEAR BLOCK CODES
Introduction to Linear Block Codes, Matrix Description of Generator Matrix & Parity Check
Matrix, Linear Block codes Generation, Minimum Distance of a Block code, Error-Detecting and
Error-correcting Capabilities of a Block code, Syndrome Decoding, Standard array and Hamming
Codes.

UNIT IV [10Periods]
CYCLIC CODES
Encoding of Convolutional Codes- Structural and Distance Properties, state, tree, trellis diagrams,
maximum likelihood decoding, Sequential decoding, Majority- logic decoding of Convolution
codes. Application of Viterbi Decoding and Sequential Decoding, Applications of Convolutional
codes in ARQ system.

UNIT V [10 Periods]

CONVOLUTION CODES
Convolution Encoder, Generation in Time Domain and Frequency domain ,Code Tree, Code
Trellis, State Diagram, Viterbi Decoding and Sequential Decoding.
TEXT BOOKS:
1. Communication Systems, by A.B. Carlson, Mc. Graw Hill Publishers
2. Digital Communications by Simon Haykin , John Wiley & Sons

REFERENCE BOOKS:
1.Digital Communications- John G. Proakis, 5th ed., , TMH.
2.Information Theory, Coding and Cryptography, Ranjan Bose.
 DATA STRUCTURES
ECE 324 Credits:3
Instruction: 3 Periods & 1 E/week Sessional Marks:40
End Exam: 3 Hours End Exam Marks:60
Pre -requisites: Mathematics, Signals and Systems

Course Outcomes:
By the end of the course, the student will be able to:
1. Analyze and apply linear data structures -arrays and their applications.

2. Interpret linear data structures -stacks and queues and their applications.

3. Implement linear data structures -Linked List and their operations.

4. Implement tree traversal techniques and operations on binary search tree.

5. Apply Non-linear data structures-graph algorithms to implement graph applications and graph
traversals.

SYLLABUS
UNIT – I [12 Periods]
ARRAYS AND STACKS
Introduction: Basic Terminology, Elementary Data Organization, Data Structure operations, Algorithm
Complexity and Time-Space trade-off.
Arrays: Array Definition, Representation and Analysis, Single and Multidimensional Arrays, address
calculation, application of arrays, Array as Parameters, Sparse Matrices.
Searching: Sequential search, binary search, Interpolation Search, comparison and analysis, Hash
Table, Hash Functions, collision resolution techniques-linear probing, quadratic probing, separate
chaining, Double hashing.
Sorting: Insertion Sort, Bubble Sort, Selection sort, Merge Sort, Quick Sort.

UNIT – II [15 Periods]

STACKS
Array Representation and Implementation of stack, Operations on Stacks: Push & Pop, Application of
stack: Conversion of Infix to Prefix and Postfix Expressions, Evaluation of Postfix expressions using
stack, Recursion, Towers of Hanoi Problem.
QUEUES AND LINKED LIST
Queues: Array representation and implementation of queues, Operations on Queue: Insert, Delete,
Display, Full and Empty. Operations on-Circular queue, De-queue, and Priority Queue, Applications of
Queues.

UNIT – III [12 Periods]

LINKED LIST
Representation and Implementation of Singly Linked Lists, Traversing and Searching of Linked List,
Insertion and deletion to/from Linked Lists, operations on-Doubly linked list, Circular Doubly linked
list, implementing priority queue using Linked List, Polynomial representation using Linked list &
addition of polynomials.

UNIT – IV [12 Periods]

TREES
Basic terminology, Binary Trees, Binary tree representation- Array and Linked list Representation of
Binary trees, Full Binary Tree, Complete Binary Tree, Traversing Binary trees- in-order, pre-order, post-
order, introduction to Threaded Binary trees
BINARY SEARCH TREES
Binary Search Tree (BST), Insertion and Deletion in BST, Complexity of Search Algorithm, AVL Trees-
Rotations, Balance factor, operations-insert, delete, display

UNIT – V [12 Periods]

GRAPHS
Terminology & Representations- Graphs, Directed Graphs, Adjacency Matrices, Adjacency List, Path
OR Transitive Closure of a Graph, Warshall‟s Algorithm, Shortest path Algorithm- Dijkstra‟s
Algorithm, Connected Component and Spanning Trees, Minimum Cost Spanning Trees- Kruskal’s,
prims algorithms, Graph Traversals.

TEXT BOOKS:
1. Y. Langsam, M. Augenstin and A. Tannenbaum, “Data Structures using C and C++”, Pearson
Education, 2nd Edition, 1995.
2. Mark Allen Weiss, "Data Structures and Algorithm Analysis in C", Second Edition, Pearson
Education.

REFERENCE BOOKS:
1. E.Horowitz and Sahani, "Fundamentals of Data Structures"
2. P. Padmanabham, C Programming and Data structures, 3rd Edition, BS publications..
3. S. Lipschutz, “Data Structures”, McGraw Hill, 1986.
4. P. Dey & M. Ghosh, Programming in C, Oxford Univ. Press.
5. ISRD Group, “Data Structures through C++”, McGraw Hill, 2011.
 DIGITAL SIGNAL PROCESSING
ECE 325 Credits:3
Instruction: 3 Periods & 1 E/week Sessional Marks:40
End Exam: 3 Hours End Exam Marks:60
Pre -requisites: Mathematics, Signals and Systems

Course Outcomes:
By the end of the course, the student will be able to:
1. Transform a DTS into frequency domain using DFT and FFT and compare these two methods with
respect to their computation complexity.
2. Design IIR digital filters for a arbitrary frequencies and attenuation values .

3. Design FIR digital filters for a arbitrary frequencies and attenuation values

4. Realize the IIR and FIR digital filters in different structure forms and understand the application of
sampling rate conversion
5. Understand the architecture of DSP processors which can be used for practical applications.

SYLLABUS
UNIT – I [10 Periods]
FOURIER TRANSFORMS AND FFTS
Discrete Fourier transforms, Properties of DFT, Circular Convolution, linear convolution of sequences
using DFT, Filtering Long duration sequences-Overlap Add and Overlap Save Method, Fast Fourier
transforms (FFT) - Radix-2 decimation in time and decimation in frequency FFT Algorithms, Inverse
FFT.

UNIT – II [10 Periods]

IIR DIGITAL FILTER DESIGN TECHNIQUES
Introduction, Analog low pass Filter design: Butterworth and Chebyshev approximations, Frequency
transformations, Design of HPF, Design of IIR Digital filters from analog filters: Bilinear
Transformations method, Impulse invariance method.

UNIT – III [10 Periods]

FIR DIGITAL FILTER DESIGN TECHNIQUES
Introduction, Fourier Series method to design digital FIR filter, Design of FIR Digital Filters using
Window Techniques- Rectangular, Triangular, Hanning, Hamming and Kaiser windows, Comparison of
IIR & FIR filters.

UNIT – IV [8 Periods]
REALIZATION OF DIGITAL FILTERS
Direct form –I &II , cascade form and parallel form structures of IIR and FIR digital filters.
MULTIRATE DIGITAL SIGNAL PROCESSING
Decimation, Interpolation, sampling rate conversion

UNIT – V [8 Periods]
INTRODUCTION TO DSP PROCESSORS
Introduction to programmable DSPs - Multiplier and Multiplier Accumulator (MAC), Modified Bus
Structures and Memory Access schemes in DSPs, Special addressing modes , Architecture of TMS
320C5X - Introduction, Bus Structure - Central Arithmetic Logic Unit - Auxiliary Register - Index
Register - Block Move Address Register - Parallel Logic Unit - Memory mapped registers - program
controller - Some flags in the status registers - On-chip memory, On-chip peripherals, Applications of
DSP in Speech Processing and Bio-Medical Engineering.

TEXT BOOKS:
1. John G. Proakis, Dimitris G.Manolakis, Digital Signal Processing, Principles, Algorithms, and
Applications: Pearson Education / PHI, 2007.
2. B.Venkataramani, M.Bhaskar, Digital Signal Processors – Architecture, Programming and
Applications,TATA McGraw Hill, 2002.

REFERENCE BOOKS:
1. Alan V. Oppenheim and Ronald W. Schafer, Digital Signal Processing, PHI.
2. Sanjit K. Mitra, Digital Signal Processing, Tata Mc Graw Hill Third edition,.
 VLSI DESIGN
ECE 326 Credits:3
Instruction: 3 Periods & 1 E/week Sessional Marks:40
End Exam: 3 Hours End Exam Marks:60
Pre -requisites: Digital Electronics and Logic Design, ECA-I, ECA-II, IC analysis.
Course Outcomes:
By the end of the course, the student will be able to:
1. Delineate IC Production process, fabrication processes for NMOS, PMOS, Bi-CMOS
Technologies.
2. Analyze CMOS electrical properties with circuit concepts.

3. Draw stick diagrams, layouts for CMOS circuits and compute delays of CMOS circuits using
modern tools.
4. Design and test the CMOS digital Circuits at different levels of abstraction using modern tools.
5. Apply testing methods on the digital designs for DFT.

SYLLABUS
UNIT – I [10 Periods]
IC TECHNOLOGY
MOS, PMOS, NMOS, CMOS &BiCMOS technologies- Oxidation, Lithography, Diffusion, Ion
implantation, Metallization, Encapsulation, Integrated Resistors and Capacitors

UNIT – II [10 Periods]

CMOS ELECTRICAL PROPERTIES
Basic Electrical Properties of MOS and BiCMOS Circuits: Ids-Vds relationships, MOS transistor
threshold Voltage, gm, gds, figure of merit, Pass transistor, NMOS Inverter, Various pull ups, CMOS
Inverter analysis and design, Bi-CMOS Inverters.
BASIC CIRCUIT CONCEPTS
Sheet Resistance RS and its concept to MOS, Area Capacitance Units, Calculations - Delays, driving
large Capacitive Loads, Wiring Capacitances, Fan-in and fan-out, Choice of layers

UNIT – III [10 Periods]

VLSI Design Flow, MOS Layers, Stick Diagrams, Design Rules and Layout, 2 micron CMOS Design
rules, Contacts and Transistors Layout Diagrams for NMOS and CMOS Inverters and Gates, Scaling of
MOS circuits, Limitations of Scaling.

UNIT – IV [10 Periods]

GATE LEVEL DESIGN
Logic Gates and Other complex gates, Switch logic, Alternate gate circuits. Different CMOS logic
Circuits-Pseudo, Dynamic, Domino, C2MOS.
SUBSYSTEM DESIGN
Subsystem Design, Shifters, Adders, ALUs, Multipliers, Parity generators, Comparators.

UNIT – V [10 Periods]

VLSI TESTING
CMOS Testing, Need for testing, Test Principles, Design Strategies for test, Chip level Test Techniques,
System-level Test Techniques, Design for testability, Practical design for test guidelines, Buil-In-Self-
Test
 TEXT BOOKS:
1. Douglas A, Pucknell, Kamran Eshraghian,“Basic VLSI Design”,3rd Edition,Prentice Hall,
l996.(UNITS I, II, III, IV & V)
2. Weste and Eshraghian, “Principles of CMOS VLSI Design”, Pearson Education, 1999

REFERENCE BOOKS:
1. 1. John .P. Uyemura,“Introduction to VLSI Circuits and Systems”,JohnWiley, 2003.
2. 2. Wayne Wolf, “Modern VLSI Design”, 3rd Edition, Pearson Education, 1997
 INTEGRATED CIRCUITS LABORATORY
ECE 328 Credits:1.5
Instruction: 3 Practical’s & 1 O/week Sessional Marks:50
End Exam: 3 Hours End Exam Marks:50
Pre -requisites: Digital Electronics, Integrated Circuits and Applications, VHDL/Verilog Language
Course Outcomes:
By the end of the course, the student will be able to:
1. Design the circuits using op-amps for various applications like Schmitt Trigger, Precision Rectifier,
Comparators and three terminal IC 78XX regulator.
2. Design active filters for the given specifications and obtain their frequency response characteristics.

3. Design and analyze multivibrator circuits using Op-amp and 555Timer

4. Design and Verify various combinational circuits like multiplexers, and de-multiplexers, encoder,
decoder, ALU, code converters etc using FPGA
5. Design and Verify various sequential circuits like flip-flops, counters using FPGA

LIST OF EXPERIMENTS
CYCLE-I: Analog Circuits
1. Frequency response of Op-amp in Inverting and Non-inverting modes.

2. Design an amplifier using Op-amp for the given specifications

3. Measurement of Op-amp parameters

4. Design and verification of Op-amp adder, subtractor, Integrator, Differentiator.

5. Design of Schmitt Trigger using op-amp

6. Design and verification of Active LPF & HPF using op-amp

7. Comparison of functionality of Astable multivibrator using a) Op-amp b) IC 555

8. Verification of functionality of R-2R ladder DAC

CYCLE-II: Experiments Using FPGA

1. Verify the functionality of parallel adder using FPGA

2. Verify the functionality of 4x1 Multiplexer using FPGA

3. Verify the functionality of 1x4 Demultiplexer using FPGA

4. Verify the functionality of 4:2 encoder using FPGA.

5. Verify the functionality of 3:8 decoder using FPGA.

6. Design and verify the functionality of Binary to Gray Code converter

7. Verify the functionality of 2-bit Comparator using FPGA

8. Verify the functionality of ALU using FPGA

9. Verify the functionality of Mod-4 Counter using FPGA

10. Verify the functionality of Delay Flip flop using FPGA

Note: A minimum of any five experiments have to be done from each cycle.
 DATA STRUCTURES LABORATORY
ECE 329 Credits:1.5
Instruction: 3 Practical’s & 1 O/week Sessional Marks:50
End Exam: 3 Hours End Exam Marks:50
Pre -requisites: Digital Electronics, Integrated Circuits and Applications, VHDL/Verilog Language
Course Outcomes:
By the end of the course, the student will be able to:
1. Implement the techniques for searching and sorting and hashing techniques.

2. Implement of stack and queue and Linked list data structures and their applications.

3. Implement operations like insertion, deletion, search and traversing mechanism on binary search
tree
4. Apply BFS and DFS algorithms to implement graph traversal.

5. Implement the techniques for searching and sorting and hashing techniques.

LIST OF EXPERIMENTS

Experiments:

1. Write a C Program to search whether an item K present in an array of N elements (Using Linear and
binary Search algorithms) CO1
Constraints: 1<K<1000
1<N<1000
Sample Input array: 45, 78,123, 48, 34, 89, 67, 54, and 74,543
Search Item: 34 Search Item: 343
Output: Key Found Output: Key Not Found

2. Write a program to sort the given array of N elements using divide and conquer method (merge sort and
quick sort algorithms) CO1
Constraints: 1<N<1000
Sample Input array: 87, 36, 9, 12, 24, 5, 78, 567, 456, 34, 96, 45, 39, and 89,123
Sample Output array: 5, 9, 12, 24, 34, 36, 39, 45, 78, 87, 89, 96, 123, 456, and 567

3. Write a C program to store k keys into an array of size n at the location computed using a hash function,
loc = key % n, where k<=n and k takes values from [1 to m], m>n. CO1
Design, Develop and Implement a C program to handle the collisions using the following collision
resolution Technique CO1
a) Linear probing: In linear probing, we linearly probe for next slot, let store k keys into an array of size S
at the location computed using a hash function, hash(x) where k<=n and k takes values from [1 to m], m>n.
Constraints: If slot hash(x) % S is full, then we try (hash(x) + 1) % S
If (hash(x) + 1) % S is also full, then we try (hash(x) + 2) % S If
(hash(x) + 2) % S is also full, then we try (hash(x) + 3) % S
..................................................
................................................

Sample Test Case:

Let us consider a simple hash function as ―key mod 7‖ and sequence of keys as 50, 700, 76, 85, 92, 73, 101.
b) Quadratic probing: Quadratic Probing we look for i2„th slot in i‟th iteration, let store k keys into an
array of size S at the location computed using a hash function, hash(x) where k<=n and k takes values from
[1 to m], m>n.
Constraints: let hash(x) be the slot index computed using hash function.
If slot hash(x) % S is full, then we try (hash(x) + 1*1) % S
If (hash(x) + 1*1) % S is also full, then we try (hash(x) + 2*2) % S If
(hash(x) + 2*2) % S is also full, then we try (hash(x) + 3*3) % S
.................................................

Sample Test Case:

c) Separate Chaining: The idea is to make each cell of hash table points to a linked list of records that have
same hash function value.
Let us store K keys into hash table of size S, where k<=n and k takes values from [1 to m], m>n.
Sample Test Case:
Let us consider a simple hash function as ―key mod 7‖ and sequence of keys as 50, 700, 76, 85, 92, 73, 101.
4. Design, Develop and Implement a menu driven Program in C for the following. CO2
Operations on STACK of Integers (Array Implementation of Stack with maximum size MAX)

1. Push an Element on to Stack

2. Pop an Element from Stack
3. Demonstrate Overflow and Underflow situations on Stack
4. Display the status of Stack
5. Exit

5. Design, Develop and Implement a Program in C for the following CO2

a) Converting an Infix Expression to Postfix Expression. Program should support for both parenthesized
and free parenthesized expressions with the operators: +, -, *, /, % (Remainder), ^(Power) and
alphanumeric operands.

b) Evaluation of postfix expression with single digit operands and operators: +,-, *, /, %, ^

6. Operations on QUEUE of Characters (Array Implementation of Queue with maximum size MAX) CO2

1. Insert an Element on to QUEUE

2. Delete an Element from QUEUE
3. Demonstrate Overflow and Underflow situations on QUEUE
4. Display the status of QUEUE
5. Exit
Note: Support the program with appropriate functions for each of the above operations

7. Design, Develop and Implement a menu driven Program in C for the following : CO2
a) Circular Queue
• Insert an Element on to Circular QUEUE
• Delete an Element from Circular QUEUE
• Demonstrate Overflow and Underflow situations on Circular QUEUE
• Display the status of Circular QUEUE
• Exit
b) Priority Queue
 • Insert an Element on to Priority QUEUE
• Delete an Element with highest priority from Priority QUEUE
• Demonstrate Overflow and Underflow situations on Priority QUEUE
• Display the status of Priority QUEUE
• Exit

Support the program with appropriate functions for each of the above operations

8. Design, Develop and Implement a menu driven C program to Perform Operations on dequeue (double
ended queue) using circular array. CO2
a) insertFront(): Adds an item at the front of Deque.
b) insertRear(): Adds an item at the rear of Deque.
c) deleteFront(): Deletes an item from front of Deque
d) deleteRear(): Deletes an item from rear of Deque
e) getFront(): Gets the front item from queue
f) getRear(): Gets the last item from queue
g) isEmpty(): Checks whether Deque is empty or not
h) isFull(): Checks whether Deque is full or not

Support the program with appropriate functions for each of the above operations

9. Design, Develop and Implement a C program to do the following using a singly linked list. CO2

a) Stack- In single linked list store the information in the form of nodes .Create nodes using dynamic memory
allocation method. All the single linked list operations perform based on Stack operations LIFO (last in first
out).
A stack contains a top pointer. Which is ―head‖ of the stack where pushing and popping items happens at the
head of the list. first node have null in link field and second node link have first node address in link field and
so on and last node address in ―top‖ pointer.
Stack Operations:
1. push() : Insert the element into linked list nothing but which is the top node of Stack.
2. pop() : Return top element from the Stack and move the top pointer to the second node of linked list or
Stack.
3. peek(): Return the top element.
4. display(): Print all element of Stack.

b) Queue- All the single linked list operations perform based on queue operations FIFO (First in first out).
 In a Queue data structure, we maintain two pointers, front and rear. The front points the first item of
queue and rear points to last item.
1. enQueue() This operation adds a new node after rear and moves rear to the next node.
2. deQueue() This operation removes the front node and moves front to the next node.
3. Display() Display all elements of the queue.

Note: Sample node information: Student Data with the fields: USN, Name, Branch, Sem, PhNo.

10. Design, Develop and Implement a menu driven Program in C for the following operations on
Binary Search Tree (BST) of Integers
CO3
a. Create a BST of N Integers: 6, 9, 5, 2, 8, 15, 24, 14, 7
b. Delete 2,8 and 6 and display tree
c. Traverse the BST in Inorder, Preorder and Post Order
d. exit

11. Implement graph traversal techniques CO4

a. BFS
b. DFS