Experiment 5 MUX DEMUX
Experiment 5 MUX DEMUX
Experiment 5 MUX DEMUX
Multiplexer &Demultiplexer
Aim:
a. Design of MUX using 74153 for Arithmetic circuits
b. Design of DEMUX using 74139 for code converter
Appertus :Ic 74153,74139,7404,7408,wires
Multiplexer
Multiplexing is the generic term used to describe the operation of sending one or more
analogue or digital signals over a common transmission line at different times or speeds and
as such, the device we use to do just that is called a Multiplexer.
Multiplexer is a combinational circuit that has maximum of 2 n data inputs, ‘n’ selection lines
and single output line. One of these data inputs will be connected to the output based on the
values of selection lines.
Since there are ‘n’ selection lines, there will be 2 n possible combinations of zeros and ones.
So, each combination will select only one data input. Multiplexer is also called as Mux.
4x1 Multiplexer
4x1 Multiplexer has four data inputs I3, I2, I1 & I0, two selection lines s1 & s0 and one
output Y. The block diagram of 4x1 Multiplexer is shown in the following figure.
74153
74153 is a data multiplexer or data selector IC. It has inverters and drivers that supply fully
complementary data selection to the AND-OR-NOT gates. It also has on-chip and binary
decoding. It has 2 1 of 4 data multiplexer in one IC package.
IC 74LS139
The 74LS139 comprises two separate two-line-to-four line decoders in a single package. The
active-low enable input can be used as a data line in demultiplexing applications. All of these
decoders/demultiplexers feature fully buffered inputs, presenting only one normalized load to
its driving circuit. All inputs are clamped with high-performance Schottky diodes to suppress
line-ringing and simplify system design.
These Schottky-clamped circuits are designed to be used in high-performance memory-
decoding or data-routing applications, requiring very short propagation delay times. In high-
performance memory systems these decoders can be used to minimize the effects of system
decoding. When used with high-speed memories, the delay times of these decoders are
usually less than the typical access time of the memory. This means that the effective system
delay introduced by the decoder is negligible.
Features:-
• Designed specifically for high speed: Memory decoders Data transmission systems
• 74LS139 contains two fully independent 2-to-4-line decoders/demultiplexers
• Schottky clamped for high performance
• Typical propagation delay (3 levels of logic) is 21 ns
• Typical power dissipation is 34 mW
CONCLUSION