OPA365

OPA2365
SBOS365D − JUNE 2006 − REVISED JUNE 2009

50MHz, Low-Distortion, High CMRR,

RRI/O, Single-Supply
OPERATIONAL AMPLIFIER
FEATURES DESCRIPTION
D GAIN BANDWIDTH: 50MHz The OPAx365 zer∅-crossover series, rail-to-rail, high-
D ZERO−CROSSOVER DISTORTION TOPOLOGY: performance, CMOS operational amplifiers are opti-
− Excellent THD+N: 0.0004% mized for very low voltage, single-supply applications.
Rail-to-rail input/output, low-noise (4.5nV/√Hz) and
− CMRR: 100dB (min)
high-speed operation (50MHz Gain Bandwidth) make
− Rail-to-Rail Input and Output
these devices ideal for driving sampling analog-to-digi-
− Input 100mV Beyond Supply Rail
tal converters (ADCs). Applications incude audio, sig-
D LOW NOISE: 4.5nV//Hz at 100kHz nal conditioning, and sensor amplification. The OPA365
D SLEW RATE: 25V/µs family of op amps are also well-suited for cell phone
D FAST SETTLING: 0.3µs to 0.01% power amplifier control loops.
D PRECISION: Special features include an excellent common-mode
− Low Offset: 100µV rejection ratio (CMRR), no input stage crossover distor-
− Low Input Bias Current: 0.2pA tion, high input impedance, and rail-to-rail input and out-
put swing. The input common-mode range includes
D 2.2V TO 5.5V OPERATION both the negative and positive supplies. The output volt-
age swing is within 10mV of the rails.
APPLICATIONS The OPA365 (single version) is available in the micro-
D SIGNAL CONDITIONING SIZE SOT23-5 and SO-8 packages. The OPA2365
(dual version) is offered in the SO-8 package. All ver-
D DATA ACQUISITION sions are specified for operation from −40°C to +125°C.
D PROCESS CONTROL Single and dual versions have identical specifications
D ACTIVE FILTERS for maximum design flexibility.
D TEST EQUIPMENT
D AUDIO
D WIDEBAND AMPLIFIERS
R2
2kΩ

C2
2.2pF
V−
V−
SD1 U2
U1 BAT17 VOUT
OPA365
OPA365
R1
7.5Ω V+
VIN V+ C1
10nF

Fast Settling Peak Detector

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.

 

       
 Copyright  2006−2009, Texas Instruments Incorporated
            

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SBOS365D − JUNE 2006 − REVISED JUNE 2009

ABSOLUTE MAXIMUM RATINGS(1) This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5.5V handled with appropriate precautions. Failure to observe
Signal Input Terminals, Voltage(2) . . . . (V−) −0.5V to (V+) + 0.5V proper handling and installation procedures can cause damage.
Signal Input Terminals, Current(2) . . . . . . . . . . . . . . . . . . . . ±10mA
Output Short-Circuit(3) . . . . . . . . . . . . . . . . . . . . . . . . . Continuous ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
Operating Temperature . . . . . . . . . . . . . . . . . . . . . −40°C to +150°C
susceptible to damage because very small parametric changes could
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . −65°C to +150°C cause the device not to meet its published specifications.
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
ESD Rating
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4000V
Charged Device Model . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000V
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400V
(1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods
may degrade device reliability. These are stress ratings only, and
functional operation of the device at these or any other conditions
beyond those specified is not supported.
(2) Input terminals are diode-clamped to the power-supply rails.
Input signals that can swing more than 0.5V beyond the supply
rails should be current limited to 10mA or less.
(3) Short-circuit to ground, one amplifier per package.

ORDERING INFORMATION(1)
PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR PACKAGE MARKING
SOT23-5 DBV OAVQ
OPA365
SO-8 D O365A
OPA2365 SO-8 D O2365A
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site
at www.ti.com.

PIN CONFIGURATIONS
Top View

OPA365 OPA365 OPA2365

VOUT 1 5 V+ NC(1) 1 8 NC(1) VOUTA 1 8 V+

V− 2 −IN 2 7 V+ −IN A 2 7 VOUTB

+IN 3 4 −IN +IN 3 6 VOUT +IN A 3 6 −IN B

V− 4 5 NC(1) V− 4 5 +IN B
SOT23−5

SO−8 SO−8

(1) NC denotes no internal connection.

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ELECTRICAL CHARACTERISTICS: VS = +2.2V to +5.5V

Boldface limits apply over the specified temperature range, TA = −40°C to +125°C.
At TA = +25°C, RL = 10kΩ connected to VS/2, VCM = VS/2, and VOUT = VS/2, unless otherwise noted.
OPAx365
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
Input Offset Voltage VOS 100 200 µV
Drift dVOS/dT 1 µV/°C
vs Power Supply PSRR VS = +2.2V to +5.5V 10 100 µV/V
Channel Separation, dc 0.2 µV/V
INPUT BIAS CURRENT
Input Bias Current IB ±0.2 ±10 pA
over Temperature See Typical Characteristics
Input Offset Current IOS ±0.2 ±10 pA
NOISE
Input Voltage Noise, f = 0.1Hz to 10Hz en 5 µVPP
Input Voltage Noise Density, f = 100kHz en 4.5 nV/√Hz
Input Current Noise Density, f = 10kHz in 4 fA/√Hz
INPUT VOLTAGE RANGE
Common-Mode Voltage Range VCM (V−) − 0.1 (V+) + 0.1 V
Common-Mode Rejection Ratio CMRR (V−) − 0.1V 3 VCM 3 (V+) + 0.1V 100 120 dB
INPUT CAPACITANCE
Differential 6 pF
Common-Mode 2 pF
OPEN-LOOP GAIN
Open-Loop Voltage Gain AOL RL = 10kΩ, 100mV < VO < (V+) − 100mV 100 120 dB
RL = 600Ω, 200mV < VO < (V+) − 200mV 100 120 dB
RL = 600Ω, 200mV < VO < (V+) − 200mV 94 dB
FREQUENCY RESPONSE VS = 5V
Gain-Bandwidth Product GBW 50 MHz
Slew Rate SR G = +1 25 V/µs
Settling Time, 0.1% tS 4V Step, G = +1 200 ns
0.01% 4V Step, G = +1 300 ns
Overload Recovery Time VIN x Gain > VS < 0.1 µs
Total Harmonic Distortion + Noise(1) THD+N RL = 600Ω, VO = 4VPP, G = +1, f = 1kHz 0.0004 %
OUTPUT
Voltage Output Swing from Rail
over Temperature RL = 10kΩ, VS = 5.5V 10 20 mV
Short-Circuit Current ISC ±65 mA
Capacitive Load Drive CL See Typical Characteristics
Open-Loop Output Impedance f = 1MHz, IO = 0 30 Ω
POWER SUPPLY
Specified Voltage Range VS 2.2 5.5 V
Quiescent Current Per Amplifier IQ IO = 0 4.6 5 mA
over Temperature 5 mA
TEMPERATURE RANGE
Specified Range −40 +125 °C
Thermal Resistance qJA °C/W
SOT23-5 200 °C/W
SO-8 150 °C/W
(1) 3rd-order filter; bandwidth 80kHz at −3dB.

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TYPICAL CHARACTERISTICS
At TA = +25°C, VS = +5V, and CL = 0pF, unless otherwise noted.

POWER SUPPLY AND COMMON−MODE

OPEN−LOOP GAIN/PHASE vs FREQUENCY REJECTION RATIO vs FREQUENCY
140 0 140
CMRR
120 120
100 −45
100

PSRR, CMRR (dB)

Voltage Gain (dB)

Phase
80

Phase (_ )
80
60 −90 PSRR
60
40
Gain 40
20 −135

0 20

−20 −180 0
10 100 1k 10k 100k 1M 10M 100M 10 100 1k 10k 100k 1M 10M 100M
Frequency (Hz) Frequency (Hz)

OFFSET VOLTAGE OFFSET VOLTAGE DRIFT

PRODUCTION DISTRIBUTION PRODUCTION DISTRIBUTION

VS = 5.5V
Population
Population
−200
−180
−160
−140
−120
−100
−80
−60
−40
−20
0
20
40
60
80
100
120
140
160
180
200

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0
Offset Voltage (µV) Offset Voltage Drift (µV/_ C)

INPUT BIAS CURRENT vs TEMPERATURE INPUT BIAS CURRENT vs COMMON−MODE VOLTAGE

1000 500
900
800 400

700
Input Bias (pA)

600 300
IB (pA)

500
200
400
300 VCM Specified Range
100
200
100
0
0 −25
−50 −25 0 25 50 75 100 125 −0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Temperature (_C) VCM (V)

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TYPICAL CHARACTERISTICS (continued)

At TA = +25°C, VS = +5V, and CL = 0pF, unless otherwise noted.

OPA365 OUTPUT VOLTAGE OPA2365 OUTPUT VOLTAGE SWING

vs OUTPUT CURRENT vs OUTPUT CURRENT
3 3
VS = ±1.1V VS = ±1.1V
VS = ±2.75V VS = ±2.75V
2 2
Output Voltage (V)

Output Voltage (V)

1 1
−40_C
−40_ C +25_ C
−40_ C +25_ C
0 0 +125_C +25_C −40_C
+125_C +25_ C +125_ C +125_ C

−1 −1

−2 −2

−3 −3
0 10 20 30 40 50 60 70 80 90 100 0 10 20 30 40 50 60 70 80 90 100
Output Current (mA) Output Current (mA)

SHORT−CIRCUIT CURRENT vs TEMPERATURE QUIESCENT CURRENT vs SUPPLY VOLTAGE

70 4.75
60
50
Short−Circuit Current (mA)

40
Quiescent Current (mA)

30 4.50
20
10
0 Dual Single 4.25
−10
−20 VS = ±2.75V
−30
−40 4.00
−50
−60
−70
−80 3.75
−50 −25 0 25 50 75 100 125 2.2 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Temperature (_ C) Supply Voltage (V)

0.1Hz to 10Hz
QUIESCENT CURRENT vs TEMPERATURE INPUT VOLTAGE NOISE
4.80

4.74
Quiescent Current (mA)

4.68
2µV/div

4.62

4.56

4.50
−50 −25 0 25 50 75 100 125 1s/div
Temperature (_ C)

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TYPICAL CHARACTERISTICS (continued)

At TA = +25°C, VS = +5V, and CL = 0pF, unless otherwise noted.

TOTAL HARMONIC DISTORTION + NOISE

vs FREQUENCY INPUT VOLTAGE NOISE SPECTRAL DENSITY
0.01 1k

G = 10, RL = 600Ω VO = 1VRMS

Voltage Noise (nV/√Hz)

100
THD+N (%)

0.001
VO = 1.448VRMS

10

G = +1, RL = 600Ω VO = 1VRMS

0.0001 1
10 100 1k 10k 20k 10 100 1k 10k 100k
Frequency (Hz) Frequency (Hz)

OVERSHOOT vs CAPACITIVE LOAD

60
SMALL−SIGNAL STEP RESPONSE

50 G=1
G = +1 RL = 10kΩ
VS = ±2.5
Output Voltage (50mV/div)

40
Overshoot (%)

G = −1
30
G = +10

20

10
G = −10
0
0 100 1k
Capacitive Load (pF) Time (50ns/div)

LARGE−SIGNAL STEP RESPONSE SMALL−SIGNAL STEP RESPONSE

G=1 G=1
RL = 10kΩ RL = 600Ω
VS = ±2.5 VS = ±2.5
Output Voltage (50mV/div)
Output Voltage (1V/div)

Time (250ns/div) Time (50ns/div)

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TYPICAL CHARACTERISTICS (continued)

At TA = +25°C, VS = +5V, and CL = 0pF, unless otherwise noted.

LARGE−SIGNAL STEP RESPONSE

G=1
RL = 600Ω
VS = ±2.5

Output Voltage (1V/div)

Time (250ns/div)

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APPLICATIONS INFORMATION R2
10kΩ
OPERATING CHARACTERISTICS
The OPA365 amplifier parameters are fully specified
from +2.2V to +5.5V. Many of the specifications apply +1.5V
from −40°C to +125°C. Parameters that can exhibit sig-
nificant variance with regard to operating voltage or
C1
temperature are presented in the Typical Characteris- 100nF
tics. R1
V+
1kΩ

OPA365 VOUT
GENERAL LAYOUT GUIDELINES
The OPA365 is a wideband amplifier. To realize the full VIN
V− C2
operational performance of the device, good high-fre- 100nF
quency printed circuit board (PCB) layout practices are
required. Low-loss, 0.1µF bypass capacitors must be
connected between each supply pin and ground as
−1.5V
close to the device as possible. The bypass capacitor
traces should be designed for minimum inductance. a) Dual Supply Connection

BASIC AMPLIFIER CONFIGURATIONS R2

As with other single-supply op amps, the OPA365 may 10kΩ

be operated with either a single supply or dual supplies.

A typical dual-supply connection is shown in Figure 1, +3V
which is accompanied by a single-supply connection.
The OPA365 is configured as a basic inverting amplifier
with a gain of −10V/V. The dual-supply connection has C1
100nF
an output voltage centered on zero, while the single− R1
V+
supply connection has an output centered on the com- 1kΩ
mon-mode voltage VCM. For the circuit shown, this volt-
OPA365 VOUT
age is 1.5V, but may be any value within the common-
mode input voltage range. The OPA365 VCM range VIN
extends 100mV beyond the power-supply rails. V−

VCM = 1.5V

b) Single−Supply Connection

Figure 1. Basic Circuit Connections

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Figure 2 shows a single-supply, electret microphone

application where VCM is provided by a resistive divider.
The divider also provides the bias voltage for the elec- 49kΩ
Clean 3.3V Supply
tret element.
3.3V

INPUT AND ESD PROTECTION 4kΩ

The OPA365 incorporates internal electrostatic dis- OPA365 VOUT

charge (ESD) protection circuits on all pins. In the case
of input and output pins, this protection primarily con- Electret 6kΩ 5kΩ
sists of current steering diodes connected between the Microphone
input and power-supply pins. These ESD protection 1µF

diodes also provide in-circuit, input overdrive protec-

tion, provided that the current is limited to 10mA as
stated in the Absolute Maximum Ratings. Figure 3
shows how a series input resistor may be added to the
Figure 2. Microphone Preamplifier
driven input to limit the input current. The added resistor
contributes thermal noise at the amplifier input and its
value should be kept to the minimum in noise-sensitive
applications.

V+
RAIL-TO-RAIL INPUT
I OVERLOAD
The OPA365 product family features true rail-to-rail in-
10mA max
put operation, with supply voltages as low as ±1.1V OPA365 VOUT
(2.2V). A unique zer∅-crossover input topology elimi- VIN
5kΩ
nates the input offset transition region typical of many
rail-to-rail, complementary stage operational amplifiers.
This topology also allows the OPA365 to provide superi-
or common-mode performance over the entire input
range, which extends 100mV beyond both power-sup-
Figure 3. Input Current Protection
ply rails, as shown in Figure 4. When driving ADCs, the
highly linear VCM range of the OPA365 assures that the
op amp/ADC system linearity performance is not com-
OFFSET VOLTAGE vs COMMON−MODE VOLTAGE
promised. 200
VS = ±2.75V
150

100
OPA365
50
VOS (µV)

−50

−100
Competitors
−150

−200
−3 −2 −1 0 1 2 3
Common−Mode Voltage (V)

Figure 4. OPA365 has Linear Offset Over the

Entire Common-Mode Range

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A simplified schematic illustrating the rail-to-rail input

circuitry is shown in Figure 5. VS

Regulated
Charge Pump
VO U T = VC C +1.8V
CAPACITIVE LOADS
VC C + 1.8V
The OPA365 may be used in applications where driving
Patent Pending
a capacitive load is required. As with all op amps, there Very Low Ripple
may be specific instances where the OPA365 can be- IB IAS Topology

come unstable, leading to oscillation. The particular op

amp circuit configuration, layout, gain and output load- IB IA S
ing are some of the factors to consider when establish-
ing whether an amplifier will be stable in operation. An
op amp in the unity-gain (+1V/V) buffer configuration
and driving a capacitive load exhibits a greater tenden-
cy to be unstable than an amplifier operated at a higher
noise gain. The capacitive load, in conjunction with the
op amp output resistance, creates a pole within the
feedback loop that degrades the phase margin. The IBI A S VO U T
degradation of the phase margin increases as the ca-
VIN − VI N +
pacitive loading increases.
When operating in the unity-gain configuration, the
OPA365 remains stable with a pure capacitive load up
to approximately 1nF. The equivalent series resistance
(ESR) of some very large capacitors (CL > 1µF) is suffi-
cient to alter the phase characteristics in the feedback
loop such that the amplifier remains stable. Increasing
the amplifier closed-loop gain allows the amplifier to IB IA S

drive increasingly larger capacitance. This increased

capability is evident when observing the overshoot re-
sponse of the amplifier at higher voltage gains. See the
typical characteristic graph, Small-Signal Overshoot
vs. Capacitive Load.
One technique for increasing the capacitive load drive Figure 5. Simplified Schematic
capability of the amplifier operating in unity gain is to in-
sert a small resistor, typically 10Ω to 20Ω, in series with
the output; see Figure 6. This resistor significantly re-
duces the overshoot and ringing associated with large V+
capacitive loads. A possible problem with this technique
is that a voltage divider is created with the added series RS
resistor and any resistor connected in parallel with the OPA365 VOUT
capacitive load. The voltage divider introduces a gain VIN 10Ω to
CL
20Ω RL
error at the output that reduces the output swing. The
error contributed by the voltage divider may be insignifi-
cant. For instance, with a load resistance, RL = 10kΩ,
and RS = 20Ω, the gain error is only about 0.2%. Howev-
er, when RL is decreased to 600Ω, which the OPA365 Figure 6. Improving Capacitive Load Drive
is able to drive, the error increases to 7.5%.

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ACHIEVING AN OUTPUT LEVEL OF

ZERO VOLTS (0V)
V+ = +5V
Certain single-supply applications require the op amp
output to swing from 0V to a positive full-scale voltage
and have high accuracy. An example is an op amp
OPA365 VOUT
employed to drive a single-supply ADC having an input VIN
range from 0V to +5V. Rail-to-rail output amplifiers with 500µA RP = 10kΩ
very light output loading may achieve an output level
within millivolts of 0V (or +VS at the high end), but not Op Amps
0V. Furthermore, the deviation from 0V only becomes Negative
−V = −5V
Supply
greater as the load current required increases. This in- Grounded
(Additional
Negative Supply)
creased deviation is a result of limitations of the CMOS
output stage.
When a pull-down resistor is connected from the ampli-
fier output to a negative voltage source, the OPA365 Figure 7. Swing-to-Ground
can achieve an output level of 0V, and even a few milli-
volts below 0V. Below this limit, nonlinearity and limiting
conditions become evident. Figure 7 illustrates a circuit R3
using this technique. 549Ω
A pull-down current of approximately 500µA is required
when OPA365 is connected as a unity-gain buffer. C2
150pF
A practical termination voltage (VNEG) is −5V, but
other convenient negative voltages also may be
V+
used. The pull-down resistor RL is calculated from
R1 R2
RL = [(VO −VNEG)/(500µA)]. Using a minimum output
549Ω 1.24kΩ
voltage (VO) of 0V, RL = [0V−(−5V)]/(500µA)] = 10kΩ. VIN
Keep in mind that lower termination voltages result in OPA365 VOUT
smaller pull-down resistors that load the output during C1
1nF
positive output voltage excursions. V−
Note that this technique does not work with all op amps
and should only be applied to op amps such as the
OPA365 that have been specifically designed to oper-
ate in this manner. Also, operating the OPA365 output Figure 8. Second-Order Butterworth 500kHz
at 0V changes the output stage operating conditions, Low-Pass Filter
resulting in somewhat lower open-loop gain and band-
width. Keep these precautions in mind when driving a
capacitive load because these conditions can affect cir-
cuit transient response and stability.

ACTIVE FILTERING
The OPA365 is well-suited for active filter applications
requiring a wide bandwidth, fast slew rate, low-noise,
single-supply operational amplifier. Figure 8 shows a
500kHz, 2nd-order, low-pass filter utilizing the multiple−
feedback (MFB) topology. The components have been
selected to provide a maximally-flat Butterworth
response. Beyond the cutoff frequency, roll-off is
−40dB/dec. The Butterworth response is ideal for ap-
plications requiring predictable gain characteristics
such as the anti-aliasing filter used ahead of an ADC.

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One point to observe when considering the MFB filter OPA365 an ideal driver for modern ADCs. Also, be-
is that the output is inverted, relative to the input. If this cause it is free of the input offset transition characteris-
inversion is not required, or not desired, a noninverting tics inherent to some rail-to-rail CMOS op amps, the
output can be achieved through one of these options: OPA365 provides low THD and excellent linearity
1) adding an inverting amplifier; 2) adding an additional throughout the input voltage swing range.
2nd-order MFB stage; or 3) using a noninverting filter Figure 10 shows the OPA365 driving an ADS8326,
topology such as the Sallen-Key (shown in Figure 9). 16-bit, 250kSPS converter. The amplifier is connected
MFB and Sallen-Key, low-pass and high-pass filter syn- as a unity-gain, noninverting buffer and has an output
thesis is quickly accomplished using TI’s FilterPro pro- swing to 0V, making it directly compatible with the ADC
gram. This software is available as a free download at minus full-scale input level. The 0V level is achieved by
www.ti.com. powering the OPA365 V− pin with a small negative volt-
age established by the diode forward voltage drop.
A small, signal-switching diode or Schottky diode
DRIVING AN ANALOG-TO-DIGITAL CONVERTER provides a suitable negative supply voltage of −0.3 to
Very wide common-mode input range, rail-to-rail input −0.7V. The supply rail-to-rail is equal to V+, plus the
and output voltage capability and high speed make the small negative voltage.

C3
220pF

R1 R2 R3
1.8kΩ 19.5kΩ 150kΩ
VIN = 1VRMS
C1 C2 OPA365 VOUT
3.3nF 47pF

Figure 9. Configured as a 3-Pole, 20kHz, Sallen-Key Filter

+5V

C1
100nF +5V
R1(1)
V+
100Ω
+IN
OPA365 ADS8326
V− C3(1) 16−Bit
1nF −IN 250kSPS
VIN
0 to 4.096V REF IN
Optional(2) +5V
R2 SD1
500Ω BAS40
−5V REF3240
C2 4.096V
C4
100nF 100nF

NOTES: (1) Suggested value; may require adjustment based on specific application.
(2) Single−supply applications lose a small number of ADC codes near ground due
to op amp output swing limitation. If a negative power supply is available, this
simple circuit creates a −0.3V supply to allow output swing to true ground
potential.

Figure 10. Driving the ADS8326

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One method for driving an ADC that negates the need to maintain the ADC gain accuracy. An additional bene-
for an output swing down to 0V uses a slightly com- fit of this method is the elimination of the negative sup-
pressed ADC full-scale input range (FSR). For exam- ply voltage; it requires no additional power-supply cur-
ple, the 16-bit ADS8361 (shown in Figure 11) has a rent.
maximum FSR of 0V to 5V, when powered by a +5V An RC network, consisting of R1 and C1, is included be-
supply and VREF of 2.5V. The idea is to match the ADC tween the op amp and the ADS8361. It not only pro-
input range with the op amp full linear output swing vides a high-frequency filter function, but more impor-
range; for example, an output range of +0.1 to +4.9V. tantly serves as a charge reservoir used for charging
The reference output from the ADS8361 ADC is divided the converter internal hold capacitance. This capability
down from 2.5V to 2.4V using a resistive divider. The assures that the op amp output linearity is maintained
ADC FSR then becomes 4.8VPP centered on a com- as the ADC input characteristics change throughout the
mon-mode voltage of +2.5V. Current from the ADS8361 conversion cycle. Depending on the particular applica-
reference pin is limited to about ±10µA. Here, 5µA was tion and ADC, some optimization of the R1 and C1 val-
used to bias the divider. The resistors must be precise ues may be required for best transient performance.

R2
10kΩ

+5V

C1
100nF
R1 +5V
V+
10kΩ R3(1)
100Ω
−IN ADS8361
OPA365
16−Bit
VIN C2(1) 100kSPS
0.1V to 4.9V V− 1nF +IN
REF OUT REF IN

+2.5V

NOTE: (1) Suggested value; may require adjustment R4

based on specific application. 20kΩ
+2.4V

R5 C3
480kΩ 1µF

Figure 11. Driving the ADS8361

13


"#$


%"#$
www.ti.com
SBOS365D − JUNE 2006 − REVISED JUNE 2009

Figure 12 illustrates the OPA2365 dual op amp provid- For best performance, the +5V supply should be as free
ing signal conditioning within an ADS1258 bridge sen- as possible of noise and transients.
sor circuit. It follows the ADS1258 16:1 multiplexer and When the ADS1258 data rate is set to maximum and
is connected as a differential in/differential out amplifier. the chop feature enabled, this circuit yields 12 bits of
The voltage gain for this stage is approximately 10V/V. noise-free resolution with a 50mV full-scale input.
Driving the ADS1258 internal ADC in differential mode,
rather than in a single-ended, exploits the full linearity The chop feature is used to reduce the ADS1258 offset
performance capability of the converter. For best com- and offset drift to very low levels. A 2.2nF capacitor is
mon-mode rejection the two R2 resistors should be required across the ADC inputs to bypass the sampling
closely matched. currents. The 47Ω resistors provide isolation for the
OPA2365 outputs from the relatively large, 2.2nF ca-
Note that in Figure 12, the amplifiers, bridges, pacitive load. For more information regarding the
ADS1258 and internal reference are powered by the ADS1258, see the product data sheet available for
same single +5V supply. This ratiometric connection down load at www.ti.com.
helps cancel excitation voltage drift effects and noise.

+5V

RFI
+
0.1µF 10µF

2kΩ
RFI AIN0 AVSS AVDD

2kΩ REFP
RFI AIN1 +
10µF 0.1µF
…
…

REFN
2kΩ
RFI
ADS1258
AIN14
MUXOUTN

MUXOUTP

2kΩ
ADCINN
ADCINP

RFI AIN15

AINCOM
RFI +5V

2.2nF
0.1µF R3
47Ω
OPA2365

R2 = 10kΩ

R1 = 2.2kΩ
R2 = 10kΩ

R3
47Ω
OPA2365

NOTE: G = 1 + 2R2/R1. Match R2 resistors for optimum CMRR.

Figure 12. Conditioning Input Signals to the ADS1258 on a Single-Supply

14
 www.ti.com
SBOS365D − JUNE 2006 − REVISED JUNE 2009

Revision History

DATE REV PAGE SECTION DESCRIPTION

Changed title.
Changed feature bullets.
6/09 D 1 Front Page
Changed drawing.
Deleted table.
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

15
 PACKAGE OPTION ADDENDUM

www.ti.com 23-Feb-2011

PACKAGING INFORMATION

Orderable Device Status

(1) Package Type Package Pins Package Qty Eco Plan
(2) Lead/ MSL Peak Temp
(3) Samples
Drawing Ball Finish (Requires Login)
OPA2365AID ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM
& no Sb/Br)
OPA2365AIDG4 ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM
& no Sb/Br)
OPA2365AIDR ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM
& no Sb/Br)
OPA2365AIDRG4 ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM
& no Sb/Br)
OPA365AID ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM
& no Sb/Br)
OPA365AIDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM
& no Sb/Br)
OPA365AIDBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM
& no Sb/Br)
OPA365AIDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM
& no Sb/Br)
OPA365AIDBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM
& no Sb/Br)
OPA365AIDG4 ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM
& no Sb/Br)
OPA365AIDR ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM
& no Sb/Br)
OPA365AIDRG4 ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM
& no Sb/Br)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 23-Feb-2011

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)

(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF OPA365 :

• Automotive: OPA365-Q1

NOTE: Qualified Version Definitions:

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 20-Jul-2010

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA2365AIDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
OPA365AIDBVR SOT-23 DBV 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
OPA365AIDBVT SOT-23 DBV 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
OPA365AIDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 20-Jul-2010

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
OPA2365AIDR SOIC D 8 2500 346.0 346.0 29.0
OPA365AIDBVR SOT-23 DBV 5 3000 203.0 203.0 35.0
OPA365AIDBVT SOT-23 DBV 5 250 203.0 203.0 35.0
OPA365AIDR SOIC D 8 2500 346.0 346.0 29.0

Pack Materials-Page 2
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