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Brief about USB 3.0 and Comparison with USB 2.0

Research · May 2015

DOI: 10.13140/RG.2.1.4095.8885

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 USB 3.0 Protocol
Comparision of USB 2.0 and USB 3.0

Tailor Neel Kishorkumar

Institute of Technology, Nirma University,
Ahmedabad, India.
[email protected]

Abstract—One of the most common digital interfaces found

today is USB. This paper describes how super speed USB 3.0
works and in which area it is differing from its previous version
high speed USB 2.0.

Keywords—SuperSpeed,USB 2.0, USB 3.0

I. INTRODUCTION
USB (Universal Serial Bus), as its name suggests it is
external bus architecture to connect peripheral to host compute
devices which are USB capable. The USB was formed by Fig. 1. USB 3.0 logo[4]
group of seven companies named Compaq, DEC(Digital B. Bandwidth
Equipment Corporation), IBM(International Business Machine
Corporations), Intel, Microsoft, NEC and Nortal in 1994.[1] USB 2.0 is having half-duplex two wire signaling which
The goal was to make it fundamentally easier to connect means unidirectional data flow with negotiated directional bus
external devices to PCs by replacing the multitude of transitions. The template is used to format your paper and style
connectors at the back of PCs. USB was mainly designed to the text. While USB 3.0 is having dual-simplex four wire
make a standard for connecting computer peripherals like signaling which means bi-directional data flows.
digital cameras, disk drives, keyboards, portable media players,
printers, network adapters to personal computers, both to C. Bus Tranaction Protocol
communicate and to supply power. USB 2.0 is host directed in which host polls continuously to
all connected peripheral devices that any of them is having data
Initially, the USB 1.0 specification was introduced with
to transfer and for this all devices must keep “on” at all times.
only a data transfer rate of 1.5 Mbit/s in January 1996. Then
In USB 3.0 polling is replaced by asynchronous notification. In
the USB 1.1 was launched with a maximum data transfer rate
SuperSpeed the host waits until a higher level application tells
of 12 Mbit/s in September 1998. Moving on to USB 2.0
it that a peripheral is having data to share. Then the host
specification war released in April 2000 and was ratified by
USB-IF(USB Implementers Forum) at the end of 2001. contacts that specific peripheral to check if data is ready to
HP(Hewlett-Packard), Intel, Lucent Technologies(now share or not and when both ends of links that are peripheral and
Alcatel-Lucent), NEC and Philips jointly led the initiative to host are ready, the data is shared. With this USB 3.0 has also
develop a higher data transfer rate, with the resulting eliminated broadcast nature of USB 2.0.
specification achieving 480 Mbit/s, a 40 times faster than the
original USB 1.1 specification. The USB 3.0 specification was D. Power Management
released on 12 November 2008. Here, in USB 3.0, it is having USB 3.0 is reducing power requirement by eliminating
an increased data transfer rate (up to 5Gbit/s), decreased polling and broadcasting nature of USB 2.0 and with that it
power consumption, increased power output and most uses link-, device-, and function- level power management.
importantly, USB 3.0 is backwards-compatible with USB 2.0. Power management is done by using four different states in
Also, USB 3.0 consists of a new higher speed bus known as link power management which are U0, U1, U2 and U3. U0 is
SuperSpeed that is in parallel with the USB 2.0 bus. for activating link, U1 for link idle-fast exit, U2 for link idle-
slower exit and U3 for link suspend.
II. COMPARISION OF USB 2.0 AND USB 3.0

A. Speed
In USB 3.0 a new transfer type is introduced called
SuperSpeed or SS which supports almost 5 Gbit/s where high
speed USB 2.0 supports only 480 Mbit/s. So, USB 3.0 is 10
times faster than USB 2.0.
III. USB 3.0 CABLE CONSTRUCTION AND WIRE ASSIGNMENTS

Fig. 2. Illustration of a USB 3.0 cable cross-section[2]

TABLE I. CABLE WIRE ASSIGNMENTS[3]

Wire Wire Assignments

No. Signal Name Description Color Fig. 3. USB 3.0 Dual Bus Topology[3]
1 PWR Power Red

2 UTP_D- Unshielded twist pair, Negative White When the host is powered on with a support of SuperSpeed,
3 UTP_D+ Unshielded twist pair, Positive Green it enabled on its downstream ports by default the following
events will take place
4 GND_PWRrt Ground for power return Black
 Hub detects VBUS and SuperSpeed support and
5 SDP1- Shielded differential pair1,Negative Blue powers its downstream ports with SuperSpeed
6 SDP1+ Shielded differential pair1,Positive Yellow enabled.
7 SDP1_Drain Drain wire for SDP1 -  Hub connects both as a SuperSpeed and as a high-
speed device
8 SDP2- Shielded differential pair2,Negative Purple

9 SDP2+ Shielded differential pair1,Positive Orange

 Device detects VBUS and SuperSpeed support
and connect as a SuperSpeed device
10 SDP2_Drain Drain wire for SDP2 -
 Host system begins hub enumeration at both
Cable external braid to be 360°
Braid Shield - SuperSpeed and high-speed
terminated on to plug metal shell
 Host system begins device enumeration at
Fig. 1 illustrates the cross section of a USB 3.0 cable. There SuperSpeed
are basic three group of wires: UTP signal pair, SDP and power
and ground wires. The purpose of intending UTP is to transmit B. USB 2.0 host
USB 2.0 signaling while the SDPs are for SuperSpeed where When the host is powered off, the hub will not provide
shield is needed signal integrity and EMI performance for the power to its downstream ports unless the hub is supporting
SuperSpeed differential pair. Each SDP is attached with a drain charging applications.
wire, which is connected to system ground the GND_DRAIN
pins in the connector. When the host is powered on and not having support of
SuperSpeed hardware, the following events will take place
IV. USB 3.0 BUS ARCHITECTURE  Hub detects VBUS and connects at a high-speed
device
A. SuperSpeed Capable Host with SuperSpeed Capable
Software  Host system begins hub enumeration at high-
speed
When the host is powered off, the hub will not provide
power to its downstream ports unless the hub is supporting  Hubs power downstream ports when directed by
charging applications. software with disabling SuperSpeed support
 Device connects at high-speed
  Host system begins device enumeration at high- communication relationship is known as pipe. It is a host
speed directed protocol, which indicates that the host always
determines when application data is transferred between the
V. SUPERSPEED ARCHITECTURE device and host. In this, device is able to request
asynchronously service from the host on behalf of a particular
The SuperSpeed bus is having a layered communication endpoint.
architecture that is having main three elements which are
SuperSpeed Interconnect which is path for devices through VI. USB 3.0 ENUMERATION
which they connected to and communicate with the host,
Devices which is for implementing the required device-end USB enumeration is the process in which host detects that a
and Host which is for implementing the required host-end. USB device is connected or not, identifies which devise is
Devices and Host are the sources or sinks of information connected and then loads the relevant device drivers. The USB
which communicate or exchange information using the specifications have defined six different device states. During
SuperSpeed bus. Host is the owner of the SuperSpeed data enumeration, a device goes through four of the states which
activity schedule, management of the SuperSpeed bus and all are Powered, Default, Address and Configured.(Other two
devices which are connected to it. states are Attached and Suspend). This involves a combination
of hardware techniques to detect something is connected and
A. Physical layer software techniques to identify what has been connected. After
The Physical layer defines the PHY portion of a port and detection of a device the host will start an exchange with a
the physical connection between the upstream facing port and device to determine what it is. The host does this by asking for
the downstream facing port (on a hub or host). The SuperSpeed device descriptors which will define the device class and what
physical connection is a combination of two differential data drivers will need to be loaded. During the enumeration the
pairs which are transmit path and receive path. A transmitter, following sequence of steps will be followed.
channel and receiver are the electrical aspects of each path
which combined represent a unidirectional differential link. At A. Attaching device to USB port
an electrical level, all differential links are initialized by The Port may be on the root hub at the host or a hub that
enabling its receiver termination. The transmitter is responsible connects downstream from the host. The hub provides power to
to detect the far end receiver termination as an indication of a the port, and the device will be in the Powered state. The
bus connection and to inform the link layer so the connect device can maximum draw up to 150 mA from the bus before
status can be factored into link operation and management. configuration and 900 mA after configuration.

B. Link Layer B. The host detects a device

The SuperSpeed link is a connection of two ports which are The USB hub continually monitors the voltage levels on
logical and physical. The connected ports are called link D+ and D- signal lines of each of its ports because a USB port,
partners. The link layer defines the communication between having no device connected to it uses 15 kohm pull-down
link partners and the logical portion of a port. resistors to make connection between USB D+ and D- signal
The logical portion of a port has: lines and GND line. When a device inserts into a port, the
device’s brings its line high with its own pull-up resistors
 State machines to manage its end of the physical which will enable the host to detect that a device is connected.
connections which includes initialization and
event management of the physical layer i.e. C. Detecting a Device type
connect, power management and removal. On detecting a downstream SuperSpeed termination at a
 State machines and buffering to manage port, a host initializes and trains the port’s link. Enumeration
information exchanges with the link partner which then proceeds at SuperSpeed with no need for further speed
implements protocol for control, power detecting.
management and reliable delivery of packet Detecting whether connected device supports high speed,
headers from port to port. USB host uses two special signal states known as J and k
 Ability to provide correct framing of sequences of Chirp. Host sends a series of alternating Chirp K and Chirp J.
bytes into packets during transmission On detecting the pattern KJKJKJ, the device removes (switch
OFF) its full-speed pull-up resistors and performs all further
 Ability to detect received packets and error checks communications at high speed. If this initial communication
of received header packets for reliable delivery fails then the USB host assumes that the device is a full speed
device.
C. Protocol Layer
The protocol layer defines the “end-to-end” D. Establishing Signal Pair
communications rules between a host and device. The Once the USB host identify that device is connected and at
SuperSpeed protocol provides for application data information what data transfer rate it should communicate, the host will
exchanges between a host and a device endpoint. This send a reset to the USB device. The device will start
communication with host by using the default address of 00h. CONCLUSION
The device is in the Default state and device’s USB registers
This paper overviewed the concept of SuperSpeed USB 3.0
are in their reset states. Now the device is ready to respond to and differences which make it faster and more preferable than
control transfers at endpoint zero. This reset is visible to the USB 2.0. USB 3.0 is basic requirement of any system because
new device only and the other devices on the bus don’t see the it is the easiest way to make communication between a PC and
reset. For USB 3.0, the host is not required to reset the port external peripherals or any two end devices which supports
after learning of a new device connection. USB like keyboard, printer, scanner, flash drives etc. Even this
E. Get Descriptor Request communication is fast and requires less power in comparisons
of other communication techniques because of its power
The host sends the request to device address 00h, end- management technique.
point zero. Because the host enumerates only one device at a
time, only one device will respond to communications
REFERENCES
addressed to device address 00h even if several devices attach
at once. There are different descriptors among them these two
[1] Jan Axelon, “THE DEVELOPER’S GUIDE USB COMPLETE”, 4th ed.,
are specially for SuperSpeed. Penram International Publishing (INDIA) Pvt. Ltd., 2011
 The BOS descriptor functions as a base [2] Ankur Tomar, Edmud Lim, “Introduction to USB 3.0 Protocol”, vol.1,
descriptor for one or more related device April, 2011
capability descriptors. This provides a way to [3] Hewlett-Packard Company, Intel Corporation, Microsoft Corporation,
support NEC Corporation, ST-NXP Wireless, Texas Instruments, “Universal
Seril Bus 3.0 Specifications”, revision 1.0, November, 2008
 The Device Capability Descriptor provides
[4] POINTGREY Innovation in Imaging, “USB 3.0: Improvements over
information that is specific to a technology or USB 2.0”, February, 2013
another aspect of a device or its function. [5] Bob Dunstan, “USB 3.0 Architecture Overview”, March, 2010
F. Assigning Address and Loading Drivers
When reset is complete, the host controller assigns a
unique address to the device by sending a Set Address
request. The address is valid until the device is detached a
hub resets the port, or the system reboots. After learning
about a device from its descriptor, the host looks for the
best match in a driver to manage communications with the
device. Windows hosts use INF files to identify the best
match.

TABLE II. BOS Descriptor[1]

Offset Field Size Description
(Decimal) (Bytes)
0 bLength 1 Descriptor size in bytes(05h)
1 bDescriptorType 1 BOS(0Fh)
2 wTotalLength 2 The no. of bytes in this
descriptor and all of its
subordinate descriptors
4 bNumDeviceCaps 1 The no. of device capability
descriptors subordinate to this
BOS descriptor

TABLE III. Device Capability Descriptor[1]

Offset Field Size Description
(Decimal) (Bytes)
0 bLength 1 Descriptor size in
bytes(varies)
1 bDescriptorType 1 Device Capability(10h)
2 bDevCapabilityType 1 01h = Wireless USB
02h = USB 2.0 Extension
03h = SuperSpeed_USB
04h = Container ID
00h,05h-FFh (reserved)
3 Capability- Varies Capability specific data and
Dependent format

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