Adld l6

Advanced Digital Logic Design – EECS 303
http://ziyang.eecs.northwestern.edu/eecs303/
Teacher: Robert Dick

Office: L477 Tech
Email: [email protected]
Phone: 847–467–2298
Review of MUX composition
Steering logic
Implementation technologies
ROMs
Homework
FPGAs
Transformations for CMOS
Outline
1. Implementation technologies
2. Homework
2 Robert Dick Advanced Digital Logic Design

Steering logic
ROMs
Homework
FPGAs
Section outline
Steering logic
ROMs
FPGAs

Steering logic
ROMs
Homework
FPGAs
5:32 decoder/demultiplexer
G1 Y7 \Y 31
\EN 1G 1Y 3 Y6 30
G2 A
Y5 29
S4 139 1 Y 2 G2B
S3 1B 1 Y 1 Y4 28
1A 1Y 0 138 Y3 27
S2 Y2 26
C
2G 2 Y 3 S1 Y1 25
2Y 2 B
S0 Y0 24
2B 2 Y 1 A
2A 2Y 0
G1 Y7 23
G2 A Y6 22
G2B Y5 21
\EN \Y31 Y4 20
138 Y3 19
S2 Y2 18
S1 C
5 : 32 . S0
B Y1 17
Y0 16
De c ode r . A
S ub s y s t e m .
15
G1 Y7
14
G2 A Y6
\Y0 G2B Y5
13
Y4
12
138 11
S4 S3 S2 S1 S0 S2
Y3
10
C Y2
S1 B Y1 9
S0 A Y0 8
Y7
7
G1
6
G2 A Y6
5
G2B Y5
Y4 4
138 3
Y3
S2 2
C Y2
S1 Y1 1
B
S0 Y0 \Y 0
A

Steering logic
ROMs
Homework
FPGAs
5:32 decoder/demultiplexer implementation details
Why is G1 connected to an inverted active-low enable signal?

Why are 2A, 2B, and 2G not connected on the 74139 part?
What would happen if this design were used and the parts were
TTL (I don’t expect you to know this one already)?
How about CMOS?

Steering logic
ROMs
Homework
FPGAs
Section outline
Steering logic
ROMs
FPGAs

Steering logic
ROMs
Homework
FPGAs
Tally circuit example
Given n-input circuit

Count number of 1s in input
I1 Zero One
0 1 0
1 0 1

Steering logic
ROMs
Homework
FPGAs
I1 Zero One
0 1 0
1 0 1
Can implement using logic gates
Zero

One
Steering logic
ROMs
Homework
FPGAs
I1 Zero One
0 1 0
1 0 1
Can implement using TGs
I
1
"0 " On e
"1 " Ze ro
"0 "

Steering logic
ROMs
Homework
FPGAs
I1 Zero One
0 1 0
1 0 1
Can implement using TGs
I
1
"0 " On e
"1 " Ze ro
"0 "

Steering logic
ROMs
Homework
FPGAs
TG tally circuit
I
1
"0 " On e
"1 " Ze ro
"0 "

Steering logic
ROMs
Homework
FPGAs
TG tally circuit
I
1
"0 " On e
"1 " Ze ro
"0 "

Steering logic
ROMs
Homework
FPGAs
TG tally circuit
I
1
"0 " On e
"1 " Ze ro
"0 "

Steering logic
ROMs
Homework
FPGAs
TG tally circuit
I
1
"0 " On e
"1 " Ze ro
"0 "

Steering logic
ROMs
Homework
FPGAs
TG tally circuit
I
1
"0 " On e
"1 " Ze ro
"0 "

Steering logic
ROMs
Homework
FPGAs
TG tally circuit
I
1
"0 " On e
"1 " Ze ro
"0 "

Steering logic
ROMs
Homework
FPGAs
TG tally circuit
I
1
"0 " On e
"1 " Ze ro
"0 "

Steering logic
ROMs
Homework
FPGAs
TG tally circuit
I
1
"0 " On e
"1 " Ze ro
"0 "

Steering logic
ROMs
Homework
FPGAs
4-input tally
I1 I2 Zero One Two

0 0 1 0 0
0 1 0 1 0
1 0 0 1 0
1 1 0 0 1

Steering logic
ROMs
Homework
FPGAs
4-input tally
I1 I2 Zero One Two

0 0 1 0 0
0 1 0 1 0
1 0 0 1 0
1 1 0 0 1
I2
"0 " Tw o
I1
O ne
"0 " O ne
Z e ro
"1 " Z e ro
"0 " "0 "

Steering logic
ROMs
Homework
FPGAs
4-input tally
I1 I2 Zero One Two
0 0 1 0 0
0 1 0 1 0
1 0 0 1 0
1 1 0 0 1
I2
I1
"0 " Tw o
O ne
"0 " O ne
Z e ro
"1 " Z e ro
"0 " "0 "

Steering logic
ROMs
Homework
FPGAs
TG tally circuit
I2
"0 " Tw o
I1
O ne
"0 " O ne
Z e ro
"1 " Z e ro
"0 " "0 "

Steering logic
ROMs
Homework
FPGAs
TG tally circuit
I2
"0 " Tw o
I1
O ne
"0 " O ne
Z e ro
"1 " Z e ro
"0 " "0 "

Steering logic
ROMs
Homework
FPGAs
TG tally circuit
I2
"0 " Tw o
I1
O ne
"0 " O ne
Z e ro
"1 " Z e ro
"0 " "0 "

Steering logic
ROMs
Homework
FPGAs
TG tally circuit
I2
"0 " Tw o
I1
O ne
"0 " O ne
Z e ro
"1 " Z e ro
"0 " "0 "

Steering logic
ROMs
Homework
FPGAs
TG tally circuit
I2
"0 " Tw o
I1
O ne
"0 " O ne
Z e ro
"1 " Z e ro
"0 " "0 "

Steering logic
ROMs
Homework
FPGAs
TG tally circuit
I2
"0 " Tw o
I1
O ne
"0 " O ne
Z e ro
"1 " Z e ro
"0 " "0 "

Steering logic
ROMs
Homework
FPGAs
TG tally circuit
I2
"0 " Tw o
I1
O ne
"0 " O ne
Z e ro
"1 " Z e ro
"0 " "0 "

Steering logic
ROMs
Homework
FPGAs
TG tally circuit
I2
"0 " Tw o
I1
O ne
"0 " O ne
Z e ro
"1 " Z e ro
"0 " "0 "

Steering logic
ROMs
Homework
FPGAs
TG tally circuit
I2
"0 " Tw o
I1
O ne
"0 " O ne
Z e ro
"1 " Z e ro
"0 " "0 "

Steering logic
ROMs
Homework
FPGAs
TG tally circuit
I2
"0 " Tw o
I1
O ne
"0 " O ne
Z e ro
"1 " Z e ro
"0 " "0 "

Steering logic
ROMs
Homework
FPGAs
TG tally circuit
I2
"0 " Tw o
I1
O ne
"0 " O ne
Z e ro
"1 " Z e ro
"0 " "0 "

Steering logic
ROMs
Homework
FPGAs
TG tally circuit
I2
"0 " Tw o
I1
O ne
"0 " O ne
Z e ro
"1 " Z e ro
"0 " "0 "

Steering logic
ROMs
Homework
FPGAs
TG tally circuit
I2
I1
"0 " Tw o
O ne
"0 " O ne
Z e ro
"1 " Z e ro
"0 " "0 "

Steering logic
ROMs
Homework
FPGAs
TG tally circuit
I2
I1
"0 " Tw o
O ne
"0 " O ne
Z e ro
"1 " Z e ro
"0 " "0 "

Steering logic
ROMs
Homework
FPGAs
TG tally circuit
I2
I1
"0 " Tw o
O ne
"0 " O ne
Z e ro
"1 " Z e ro
"0 " "0 "

Steering logic
ROMs
Homework
FPGAs
TG tally circuit
I2
I1
"0 " Tw o
O ne
"0 " O ne
Z e ro
"1 " Z e ro
"0 " "0 "

Steering logic
ROMs
Homework
FPGAs
TG tally circuit
I2
I1
"0 " Tw o
O ne
"0 " O ne
Z e ro
"1 " Z e ro
"0 " "0 "

Steering logic
ROMs
Homework
FPGAs
TG tally circuit
I2
I1
"0 " Tw o
O ne
"0 " O ne
Z e ro
"1 " Z e ro
"0 " "0 "

Steering logic
ROMs
Homework
FPGAs
TG tally circuit
I2
I1
"0 " Tw o
O ne
"0 " O ne
Z e ro
"1 " Z e ro
"0 " "0 "

Steering logic
ROMs
Homework
FPGAs
TG tally circuit
I2
I1
"0 " Tw o
O ne
"0 " O ne
Z e ro
"1 " Z e ro
"0 " "0 "

Steering logic
ROMs
Homework
FPGAs
TG tally circuit
I2
I1
"0 " Tw o
O ne
"0 " O ne
Z e ro
"1 " Z e ro
"0 " "0 "

Steering logic
ROMs
Homework
FPGAs
TG tally circuit
I2
I1
"0 " Tw o
O ne
"0 " O ne
Z e ro
"1 " Z e ro
"0 " "0 "

Steering logic
ROMs
Homework
FPGAs
TG tally circuit
I2
I1
"0 " Tw o
O ne
"0 " O ne
Z e ro
"1 " Z e ro
"0 " "0 "

Steering logic
ROMs
Homework
FPGAs
TG tally circuit
I2
I1
"0 " Tw o
O ne
"0 " O ne
Z e ro
"1 " Z e ro
"0 " "0 "

Steering logic
ROMs
Homework
FPGAs
Section outline
Steering logic
ROMs
FPGAs

Steering logic
ROMs
Homework
FPGAs
ROMs, FPGAs, and multi-level minimization
Programmable read-only memories (PROMs)

Field-programmable gate arrays (FPGAs)
Programmable devices for prototyping

Steering logic
ROMs
Homework
FPGAs
2-D array of binary values

Input: Address
Output: Word

Steering logic
ROMs
Homework
FPGAs
PROM
+5 V +5 V +5 V +5 V
n
2 −1
i W o rd Li n e 0011
De c
j W o rd Li n e 1010
B i t Lin e s
0 n− 1
A dd re s s

Steering logic
ROMs
Homework
FPGAs
Implementing logic with PROMs
F0 = A B C + A B C + A B C
F1 = A B C + A B C + A B C
F2 = A B C + A B C + A B C
F3 = A B C + A B C + A B C

Steering logic
ROMs
Homework
FPGAs
Truth table
A B C F3 F2 F1 F0
0 0 0 0 1 0 0
0 0 1 0 1 1 1
0 1 0 0 0 1 0
0 1 1 1 0 0 0
1 0 0 1 1 0 1
1 0 1 0 0 0 1
1 1 0 1 0 0 0
1 1 1 0 0 1 0

Steering logic
ROMs
Homework
FPGAs
Truth table
A B C F3 F2 F1 F0
0 0 0 0 1 0 0
0 0 1 0 1 1 1
0 1 0 0 0 1 0
0 1 1 1 0 0 0
1 0 0 1 1 0 1
1 0 1 0 0 0 1
1 1 0 1 0 0 0
1 1 1 0 0 1 0
Address

Steering logic
ROMs
Homework
FPGAs
Truth table
A B C F3 F2 F1 F0
0 0 0 0 1 0 0
0 0 1 0 1 1 1
0 1 0 0 0 1 0
0 1 1 1 0 0 0
1 0 0 1 1 0 1
1 0 1 0 0 0 1
1 1 0 1 0 0 0
1 1 1 0 0 1 0
Word

Steering logic
ROMs
Homework
FPGAs
PROM suitable for implementing example
outputs
8 words x
4 bits
addresses
Steering logic
ROMs
Homework
FPGAs
Memory composition
2764 EPR OM
8K x 8
2764
VPP
PGM
A12
A11
A10
O7
A9
O6
A8
O5
A7
O4
A6
O3
A5
O2
A4 O1
A3 O0
A2
A1
A0
CS
OE

Steering logic
ROMs
Homework
FPGAs
Memory composition
2764 2764
VP P VP P
+ P GM + P GM
A12 A12
A11 A11
A10 O7 A10 O7
A9 O6 A9 O6
A8 O5 A8 O5
A7 O4 A7 O4
A6 O3 A6 O3
A5 O2 A5 O2
A4 O1 A4 O1
A3 O0 A3 O0
A2 A2
A1 A1
A0 A0
CS U3 CS U 2
OE OE
A13
/OE
A12:A0
D 15:D 8
D 7:D 0
2764 2764
VP P VP P
+ + P GM
P GM
A12 A12
A11 A11
A10 O7 A10 O7
A9 O6 A9 O6
A8 O5 A8 O5
A7 O4 A7 O4
A6 O3 A6 O3
A5 O2 A5
A4 O1
O2
A4 O1
A3 O0 A3
A2 A2 O0
A1 A1
A0 A0
CS U1 CS U 0
OE OE
16K x 16

Steering logic
ROMs
Homework
FPGAs
Memory composition
2764 2764
VP P VP P
+ P GM + P GM
A12 A12
A11 A11
A10 O7 A10 O7
A9 O6 A9 O6
A8 O5 A8 O5
A7 O4 A7 O4
A6 O3 A6 O3
A5 O2 A5 O2
A4 O1 A4 O1
A3 O0 A3 O0
A2 A2
A1 A1
A0 A0
CS U3 CS U 2
OE OE
A13
/OE
A12:A0
D 15:D 8
D 7:D 0
2764 2764
VP P VP P
+ + P GM
P GM
A12 A12
A11 A11
A10 O7 A10 O7
A9 O6 A9 O6
A8 O5 A8 O5
A7 O4 A7 O4
A6 O3 A6 O3
A5 O2 A5
A4 O1
O2
A4 O1
A3 O0 A3
A2 A2 O0
A1 A1
A0 A0
CS U1 CS U 0
OE OE
16K x 16
Chip select

Steering logic
ROMs
Homework
FPGAs
PLA/PAL vs. PROM
PLA
Takes advantage of don’t-cares
Good at random logic
Good when product terms shared
PAL
More area-efficient for certain designs
OR-plane can’t be programmed, usually no sharing

Steering logic
ROMs
Homework
FPGAs
PLA/PAL vs. PROM
PROM
Design trivial
Can’t take advantage of don’t-cares
Area-inefficient
Product/sum terms not shared

Steering logic
ROMs
Homework
FPGAs
Section outline
Steering logic
ROMs
FPGAs

Steering logic
ROMs
Homework
FPGAs
Field-programmable gate arrays (FPGAs)
PLAs
10–100 gate equivalent
FPGAs
Altera
Actel
Xilinx
100–1,000,000 gate equivalent

Steering logic
ROMs
Homework
FPGAs
Altera EPLDs
Each has from 8–48 macrocells

Macrocell behavior controlled with EPROM bits
Can be used sequentially
Has synchronous and asynchronous modes

Steering logic
ROMs
Homework
FPGAs
Altera erasable programmable logic devices (EPLDs)
Composed of many macrocells – 8 product term AND/OR array with

programmable MUXs
C lk
MUX
Ou tpu t
AND pad
Q MUX I/O P i n
ARR AY
In v e r t
Con tro l
F /B
MUX S e q. Lo g ic
B lo c k
P ro g ram m ab l e p o l a rity P ro g ram m ab l e fee dba c k

Steering logic
ROMs
Homework
FPGAs
Multiple array matrix (MAX)
Altera macrocells quite limited

Can’t share product terms between macrocells
Workaround: Connect together macrocells with programmable
interconnect

Steering logic
ROMs
Homework
FPGAs
Multiple array matrix (MAX)
Lo g i c G l o ba l R o uti n g :
LA B A LA B H
Arra y P ro g ram m ab l e
B lo c k s Inte rc o nn ec t
LA B B LA B G
(s i m il a r to Arra y
P EP M5128:
m a c ro ce ll s ) I
A 8 Fi x e d Inputs
LA B C LA B F
52 I/O P i n s
8 LA B s
16 Ma c ro ce ll s /LA B
LA B D LA B E
32 Expand e rs /LA B

Steering logic
ROMs
Homework
FPGAs
MAX expander terms
I/O Pad
Ma c roce ll
I/O
ARRAY
B l oc k
I
N I/O Pad
P
P I
U A
T
S E xpand e r
P ro du c t
Te rm
ARRAY

Steering logic
ROMs
Homework
FPGAs
MAX expander terms
Ma c ro c e ll
P − Te rm s
Expand e r
P − Te rm s
Expander product terms shared among all macrocells

Steering logic
ROMs
Homework
FPGAs
Altera 22V10 PAL

IN CREM EN T 2904
1
0 4 8 12 16 20 24 28 32 36 40 2948
0
AS Y NCHRONOUS RE S E T 2992
(T O ALL RE GIS T E RS )
3036
F IRST 44 3080
F U SE 3124
NUM BERS
88 3168
132 11
176 3212 OUT P UT
LOGIC
220 AR
10 3256 MA CROCE L 18
264 D Q 23 3300 L
00 3344
308 Q 01 3388
352 SP
5808
3432 P − 5818
396 P 3476 R− 5819
R 3520
1 5809 3564
0 3608
6
440
3652
484
528 3696
572 3740
616 OUT P UT 3784
660 LOGIC 3828
704 MA CROCE LL
22 3872
748 3916 OUT P UT
3960 LOGIC
792 MA CROCE L 17
836 P − 5810
4004 L
880 R − 5811 4048
4092
2 4136 P − 5820
4180 R − 5821
4224
924 4268
968 7
1012
1056 4312
1100
1144 OUT P UT 4356
1188 LOGIC
4400
1232 MA CROCE LL 21 4444
1276 4488
1320 4532 OUT P UT
LOGIC
1364 4576 MA CROCE L 16
P − 5812 4620 L
1408 R− 5813 4664
1452 4708
3
4752 P − 5822
4796 R − 5823
4840
1496
8
1540
1584 4884
1628
1672 4928
1716 4972
1760 OUT P UT 5016
1804 LOGIC
20 5060 OUT P UT
1848 MA CROCE LL
5104 LOGIC
1892 5148 MA CROCE L 15
1936 5192
L
1980 P − 5814 5236
2024 R − 5815 5280
2068 P − 5824
2112 5324 R − 5825
4 9
2156 5368
5412
2200 5456
2244 5500 OUT P UT
2288 5544 LOGIC
MA CROCE L 14
2332 5588 L
2376 5632
2420 5676
2464 OUT P UT 5720 P − 5826
2508 LOGIC
19 R − 5827
2552 MA CROCE LL
2596 10
2640
2684 P − 5816 S Y NCHRONOUS
2728 R− 5817 5764 P RE S E T
2772
2816 11 13
2860
5 IN CREM EN 0 4 8 12 16 20 24 28 32 36 40
T

Steering logic
ROMs
Homework
FPGAs
Altera 22V10 PAL
Many product terms per output

Latches and MUXs associated with outputs
22 IO pins
10 may be used as outputs

Steering logic
ROMs
Homework
FPGAs
Actel programmable gate arrays
Rows of programmable logic blocks

Rows of interconnect
Columns of interconnect
Attach to rows using antifuses

Steering logic
ROMs
Homework
FPGAs
Each combinational logic block has 8 inputs, 1 output

No built-in sequential elements
Build flip-flops using logic blocks

Steering logic
ROMs
Homework
FPGAs
Actel logic block
S OA S0 S1
D0
2:1 MUX
D1
2:1 MUX Y
D2
2:1 MUX
D3
S OB
Modified 4:1 MUX

Steering logic
ROMs
Homework
FPGAs
Actel logic block
R "0 "
2:1 MUX
"0 "
2:1 MUX Q
"1 "
2:1 MUX
Cross-couple for sequential use

Steering logic
ROMs
Homework
FPGAs
IO buffers, programming & test logic
IO buf., prog. & test logic

IO buf., prog. & test logic
Logic modules
Wiring tracks
IO buffers, programming & test logic

Steering logic
ROMs
Homework
FPGAs
Actel interconnect
Log ic M o dule
Ho rizo n t al
Tra c k A n t i− f u s e
Ve rt ic al
Tra c k

Steering logic
ROMs
Homework
FPGAs
Antifuse routing
Build long routing lines from short segments

Steering logic
ROMs
Homework
FPGAs
Actel routing example
Log i c Mo du le
Inpu t
Log ic Mo du le
Lo g ic Mo du le
O u t pu t
Inpu t
Minimize number of antifuse hops for critical path

2-3 hops for most interconnections

Steering logic
ROMs
Homework
FPGAs
Xilinx logic cell arrays (LCAs)
CMOS static RAM

Run-time programmable
Serial shift-register based programming
Program on power-up (external PROM)

Steering logic
ROMs
Homework
FPGAs
Xilinx LCA components
Configurable logic blocks (CLBs)

IO blocks (IOBs)
Wiring channels

Steering logic
ROMs
Homework
FPGAs
Xilinx LCAs
IO B IO B IO B IO B
IO B
CLB CLB
IO B
W i ri n g Chann e l s
IO B
CLB CLB
IO B

Steering logic
ROMs
Homework
FPGAs
Xilinx LCA features
Inputs
Input variables
Tri-state (high-Z) enable bit for output
Output clocks

Steering logic
ROMs
Homework
FPGAs
Xilinx LCA features
Output the input bit

Contains internal flip-flops for inputs and outputs
Fast and slow outputs available, e.g., 5 ns vs. 30 ns
Slower option limits slew rate
Lower noise
Lower power consumption

Steering logic
ROMs
Homework
FPGAs
Xilinx LCA
P rog ram C o ntro ll e d Opti o n s

Vcc
OUT TS OUTP UT S LEW P A S S IVE
INV INV S OURCE RATE P ULLU P
E nab l e
Output
MUX P AD
Out D Q Output
Buffe r
R
Direc t In
Q D
R eg i s te re d In TTL o r CMOS
Input Buffe r
Cl oc k s Gl o ba l R e s e t

Steering logic
ROMs
Homework
FPGAs
Xilinx CLB
2 flip-flops
General function of 4 variables
2 non-general functions of 5 variables
Certain special-case functions of 6 variables
Global reset
Clock
Clock enable
Independent input, DIN

Steering logic
ROMs
Homework
FPGAs
Xilinx CLB
Res et
D IN Mux D RD
Q
CE
Q1 Mux X
F
A
B C o m b ina tio na l
C F un c tio n
D G e n e ra t o r
E G
Q2 Mux Y
Mux D RD
Q
Clo c k Mux CE
Clo c k
Enab le

Steering logic
ROMs
Homework
FPGAs
Function generator
Q1
A
B Mux F
F un c tio n
C Mux of 5
Va riable s
D G
E
Q2
Two constrained functions of five variables

Steering logic
ROMs
Homework
FPGAs
Function generator
Q1
A
B Mux
F un c tio n
C Mux of 4 F
Va riab le s
D Mux
E
Q2
Q1
A
B Mux
F un c tio n
C Mux of 4 G
Va riab le s
D Mux
E
Q2
Two arbitrary functions of four variables

Steering logic
ROMs
Homework
FPGAs
Function generator
Q1
A
B Mux
F un c tio n
C Mux of 4
Va riab le s
D E
F
Q2
Mux
Q1
A G
B Mux
F un c tio n
C Mux of 4
Va riab le s
D
Q2
Certain limited functions of 6 variables

Steering logic
ROMs
Homework
FPGAs
PARITY5 CLB cost example
Determine whether the number of 1s is even or odd

F =AB C D E
Implement using 1 CLB

Steering logic
ROMs
Homework
FPGAs
2-bit comparator CLB cost example
A B = C D or A B > C D
GT = A C + A B D + B C D
EQ = A B C D + A B C D + A B C D + A B C D
Only 1 CLB required

Steering logic
ROMs
Homework
FPGAs
Majority CLB cost example

High whenever dn/2e outputs are high
5 − input Ma jo rity C irc uit
CLB
7 − input Ma jo rity C irc uit
CLB
CLB
CLB

Steering logic
ROMs
Homework
FPGAs
Large parity CLB cost example

2 levels allow up to 25 inputs
9 Input Pa rity Log ic
CLB
CLB

Steering logic
ROMs
Homework
FPGAs
4-bit adder CLB cost example
Full adder, 4 CLB delays to final carry out (CO), 4 CLBs

A3 B3 A2 B2 A1 B1 A0 B0 Ci n
CLB CLB CLB CLB
C o ut S3 C2 S2 C1 S1 C0 S0

Steering logic
ROMs
Homework
FPGAs
4-bit adder CLB cost example

Composition from 2 2-bit adders give 2 CLB delay, 6 CLB cost
A 3 B3 A 2 B2 A 1 B1 A 0 B0 Ci n
CLB CLB
S2 S0
S3 S1
C o ut C2

Steering logic
ROMs
Homework
FPGAs
Xilinx interconnect
Short direct connections

Global long lines
Horizontal/vertical long lines
Switching matrix connections

Steering logic
ROMs
Homework
FPGAs
Xilinx interconnect
Hierarchical routing organization

Some designs are constrained by routing resources
Can use logic CLBs to control routing
Substantial communication power consumption

Steering logic
ROMs
Homework
FPGAs
Xilinx interconnect
Direc t
Co nn ec t i o n s
Inte rc o nn ec t DI CE A DI CE A
B X B X
C C L B0 C C L B1
K Y K Y
Direc t C o nn ec ti o n s E D R E D R
Ho ri z o n t a l
Lo n g Li n e
G l o ba l Lo n g Li n e
Swi t c h i n g
M a t ri x
Ho ri zo nta l/Ve rti c a l Ho ri z o n t a l

Lo n g Li n e
Lo n g Li n e s
DI CE A DI CE A
B X B X
C C L B2 C C L B3
K K
S w itc h in g Matrix E D R
Y
E D R
Y
C o nn ec ti o n s
Ve r t i c a l Gl o ba l
Lo n g Li n e s Lo n g Li n e

Steering logic
ROMs
Homework
FPGAs
Example Xilinx parts
Parameter XC4024 XC3195 XC2018

Number of FFs 2,560 1,320 174
Number of IOs 256 176 74
Number of logic inputs per CLB 9 5 4
Function generators per CLB 3 2 2
Fast carry logic yes no no
Number of logic outputs per CLB 4 2 2
RAM bits 32,768 0 0

Steering logic
ROMs
Homework
FPGAs
Dynamic reconfiguration
Serial configuration slow

Parallelize
Full reconfiguration slow
Partial reconfiguration
Reconfiguration slow
Use configuration cache

Steering logic
ROMs
Homework
FPGAs
FPGA application examples
Prototyping
Constant coefficient multiplication
Direct HW implementation of problem instance, e.g.,
3SAT
Design rule checking (DRC)

Steering logic
ROMs
Homework
FPGAs
Prototype designs
Discrete packages
Slow
Error-prone
Custom layout requires circuit fabrication
Slow
Expensive for small runs
Can’t be changed

Steering logic
ROMs
Homework
FPGAs
Programmable devices in prototyping
Multiplexers (MUXs) and demultiplexers (DMUXs)

Wiring them up is tedious and error-prone
Programmable array logic (PAL) and programmable logic array
(PLA)
Fuses blown, write-once
Generic array logic (GAL)
Electrically reprogrammable

Steering logic
ROMs
Homework
FPGAs

Inefficient for implementing random logic
Write-once
Erasable programmable read-only memories (EPROMs)
Can be erased
Erasure slow (UV)
Expensive package window

Steering logic
ROMs
Homework
FPGAs
Electrically erasable programmable read-only memories

(EEPROMs)
Erasure fast
Packaging less expensive
Potential for in-circuit erasure
Field-programmable gate arrays (FPGAs) are ideal
If market size small, ship FPGAs
In-circuit programming practical

Steering logic
ROMs
Homework
FPGAs
Section outline
Steering logic
ROMs
FPGAs

Steering logic
ROMs
Homework
FPGAs
DeMorgan’s Law for CMOS
(A + B) = A B
(AB) = A + B
A+B =A B
AB = A + B

Steering logic
ROMs
Homework
FPGAs
DeMorgan’s Law for CMOS
OR is the same as NAND with complemented inputs

AND is the same as NOR with complemented inputs
NAND is the same as OR with complemented inputs
NOR is the same as AND with complemented inputs

Steering logic
ROMs
Homework
FPGAs
DeMorgan’s Law for OR/NAND
A A B B A+B (A B ) A +B (AB)
0 1 0 1 0 0 1 1
0 1 1 0 1 1 1 1
1 0 0 1 1 1 1 1
1 0 1 0 1 1 0 0

Steering logic
ROMs
Homework
FPGAs
DeMorgan’s Law for AND/NOR
A A B B AB (A + B ) A B (A + B)
0 1 0 1 0 0 1 1
0 1 1 0 0 0 0 0
1 0 0 1 0 0 0 0
1 0 1 0 1 1 0 0

Steering logic
ROMs
Homework
FPGAs
AND/OR → NAND/NOR
A
B
C
D

Steering logic
ROMs
Homework
FPGAs
AND/OR → NAND/NOR
A
B
C
D
A
B AND
OR
C
D AND

Steering logic
ROMs
Homework
FPGAs
AND/OR → NAND/NOR
A
B AND
OR
C
D AND
NAND
A
B
C
D NAND
NAND

Steering logic
ROMs
Homework
FPGAs
AND/OR → NAND/NOR
NAND
A
B
C
D NAND
NAND
NAND
A
B
C
D
NAND
NAND

Steering logic
ROMs
Homework
FPGAs
AND/OR/NOT network to NAND/NOR
=
Homework
Outline
2. Homework

Homework
Homework
Review for midterm exam on Thursday

Will post solutions to homework tonight
Responsible for all reading, assignments, labs

Homework
Review
Two-level transformations and minimization

Multi-level minimization
Design with various implementation technologies

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Advanced Digital Logic Design – EECS 303

Teacher: Robert Dick

2 Robert Dick Advanced Digital Logic Design

3 Robert Dick Advanced Digital Logic Design

4 Robert Dick Advanced Digital Logic Design

5:32 decoder/demultiplexer implementation details

Why is G1 connected to an inverted active-low enable signal?

5 Robert Dick Advanced Digital Logic Design

6 Robert Dick Advanced Digital Logic Design

Tally circuit example

Given n-input circuit

7 Robert Dick Advanced Digital Logic Design

Tally circuit example

8 Robert Dick Advanced Digital Logic Design

Tally circuit example

9 Robert Dick Advanced Digital Logic Design

Tally circuit example

10 Robert Dick Advanced Digital Logic Design

11 Robert Dick Advanced Digital Logic Design

11 Robert Dick Advanced Digital Logic Design

11 Robert Dick Advanced Digital Logic Design

11 Robert Dick Advanced Digital Logic Design

12 Robert Dick Advanced Digital Logic Design

12 Robert Dick Advanced Digital Logic Design

12 Robert Dick Advanced Digital Logic Design

12 Robert Dick Advanced Digital Logic Design

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