ALU Report

Arithmetic Logic Unit
Digital Logic Design Project

DE-30 Mechanical SYN-A
Muhammad Yawar Reg-461 Abdul Saim Reg-616
Table of Contents
Introduction: ........................................................................................................................................... 2 Assignment:............................................................................................................................................. 2 Assignment Objectives: ........................................................................................................................ 2 Block Diagram of Arithmetic Logic Unit: ............................................................................................... 3 How to use this ALU? ............................................................................................................................... 5 Construction of ALU: ................................................................................................................................ 6 Comparator: ........................................................................................................................................ 6 Adder/ Subtractor: ............................................................................................................................... 6 Multiplier:............................................................................................................................................ 7 Bit Shifter:............................................................................................................................................ 8 Bit Rotation: ........................................................................................................................................ 9 Bitwise AND/OR/XOR/NOT: ................................................................................................................. 9 Output of ALU: ...................................................................................................................................... 10
Introduction:
Arithmetic logic unit is that part of the computer which performs the different logic operations and arithmetic calculations like addition, subtraction, multiplication and division. It can also perform bitwise logic operations like AND, OR, XOR, etc. The arithmetic logic unit performs bit-shifting operations like rotating or shifting a certain word to either the left or the right by a given number of bits. These can also be represented as divisions by 2 and also multiplications by 2. These are the simple operations carried out by the arithmetic logic unit. Typically, the ALU has direct input and output access to the processor controller, main memory (random access memory or RAM in a personal computer), and input/output devices. A rough schematic is shown below:
Assignment:
Design an ALU.
Assignment Objectives:
1) 2) 3) 4) Can perform addition, subtraction multiplication and division. Can perform bitwise AND, OR, NOT and XOR operations Can perform bit shifting and bit rotation Can compare two numbers
Use Input Registers and Control Unit
Block Diagram of Arithmetic Logic Unit:
The schematic diagram of the ALU in Proteus:
How to use this ALU?

There are two four bit inputs through which two, four bit numbers can be entered. There is one input for clock pulse as well. Along with these inputs are the control unit inputs. The control unit input is an 8-bit number. The first two bits determine the amount of bit rotation of input A. 00 means no rotation, 01 means rotation of one bit to the right,10 means rotation of 2-bits, similarly 11 means rotation of 3-bits. The next most significant bit controls the shifting. A LOW-HIGH-LOW pulse must be sent to this input to cause shifting. The LOW-HIGH pulse loads the input A into the shift register, the HIGH-LOW Pulse starts shifting. The HIGH state must be held for at least one clock cycle. The next two bits control whether addition, subtraction or multiplication is to be performed. 00 is for addition, 01 for multiplication and 10 for subtraction. 11 is an
unused state and the outputs for this combination will be neither the result of multiplication nor subtraction. The last three bits determine which result to give at the 4-bit output register.
State (CH2 CH1 CH0)

000
Function
No Special Function (Result of ADD, Subtract or Multiply transferred, depending on more significant bits) A AND B A OR B A XOR B A (NOT) B (NOT) Result of Bit rotation of A Result of Bit Shifting of A
001 010 011 100 101 110 111
Construction of ALU:
Comparator:
Compares the two input numbers and turns one of the three outputs ON, corresponding to the result of comparison. The function used is: Output (A=B) = x3 x2 x1 x0 Output (A<B) =A3B3 + x3 A2 B2 + x3 x2 A1 B1 + x3 x2 x1 A0 B0 Output (A>B) =A3 B3 + x3 A2 B2 + x3 x2 A1 B1 + x3 x2 x1 A0 B0 Where, xi= AiBi + A iB i i=0,1,2,3
So, the output that gets high gives result of the comparison.
Adder/ Subtractor:
The adder circuit consists of four full adders connected in such a way that carry out of one is connected to the carry in of the second. The inputs to each adder are the respective bits of both numbers. The functions are: S=A (XOR) B (XOR) Cin Cout=A.B+C.(A (XOR) B) The circuit is:
The subtractor uses the property that A-B=A+(2 s Complement of B). This is achived by using an XOR gate at the input B. One of the inputs of the XOR is connected to the input register B, the other input is connected to the carry in of the first full adder. In this way, when this input is ON, 2 s complement of B is delivered to the adder and we get subtraction operation.
4 Full Adders
Multiplier:
The circuit for a 2-bit multiplier is:
We also know that if: (25 x 34)= (2x3)x100 + (2x4)x10 + (3x5)x10 + (5x4) Similarly, (1101x1000) = (11x10)x100 + (11x00)x10 + (01x10)x10 + (01x00) Using this principle we generated four 4-bit products. Now two of these four products (which are actually 6 bit numbers), can be added using the four bit adder stated above. Then using a 7-bit adder and then an 8-bit adder we add the products previously generated to get the final product which is an 8bit number.
Bit Shifter:
Bit Shifting was done using shift registers. The shift register used is called Parallel in-Parallel out Register. This name is given because the data (in the form of bits) is not transferred in series (throughneoutput) but in parallel. The basic circuit used is:
Bit Rotation:
Bit rotation (also called circular shifting) means shifting bit such that the bits are "rotated" as if the left and right ends of the register were joined. The value that is shifted in on the right during a left-shift is whatever value was shifted out on the left, and vice versa.
The bit shifting is achieved by using multiplexers. Each of the four multiplexers is given input from the same four bits but in different orders. For example, the first multiplexer is given input in the order A3A2A1A0 but the next is given A2A1A0A3 and so on. In this way, if both the select lines are OFF then we get normal output i.e. equal A3A2A1A0, but for S1=0 and S0=1, we get A2A1A0A3 and so on.
Bitwise AND/OR/XOR/NOT:
These operations were very simple to perform. We used simple gates between the two bit, on which bitwise operation was to be performed (single bit in case of NOT). The output of these gates were given to the multiplexer.
Output of ALU:

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Arithmetic Logic Unit

Digital Logic Design Project

Muhammad Yawar Reg-461 Abdul Saim Reg-616

Use Input Registers and Control Unit

Block Diagram of Arithmetic Logic Unit:

The schematic diagram of the ALU in Proteus:

How to use this ALU?

State (CH2 CH1 CH0)

001 010 011 100 101 110 111

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