Digital Systems Design (DSD)

4th Year Electrical Engineering Dept.

Lecture 1(8-12/3/2020)

Logic circuits are of two types:

1. Combinational circuits
2. Sequential circuits

The combinational logic circuit is built from logical gates only.

While the sequential logic circuit is mainly built from flip flops in
addition to logical gates.



 The sequential logic circuit (or state machine) differs from the
combinational circuit in that it has a memory. Its output(s) depend(s) on
its present input(s) and the previous states of the circuit.

 The state machines are either synchronous or asynchronous

circuits.

 In the synchronous state machine, all the units (flip flops) of the
circuit change their present states to the next states simultaneously
(controlled by a master clock).

 In the asynchronous state machine, there is no master clock

controlling the transition of the circuit’s units from the present states to
the next states.

 There are two models for designing state machines (the Mealy model
and the Moore model).
Example:

Suppose a circuit is required to recognize the three – bit pattern (101), and to
produce an output (Z = 1) whenever it occurs in the continuous serial input (X) to
the circuit. Then the circuit will reset and start testing again.
 0/0

1/0

B 1/0
0/0 0/0
0/0
1/0
C

1/1

State diagram
(Mealy model)
Directed lines: X/Z
Circles: state-code

Starting from an initial waiting state A, if a 0 is received the circuit stays in the
same state. For a 1, however, there is a transition to state B, indicating the start of
the required sequence. If, while in this state, a 0 is received, i.e. sequence (10), the
circuit changes to state C. When in state C, if a 1 is received, completing the
sequence (101), the circuit changes to state D, giving the required output. An input
of 0 returns the circuit to state A to await the start of another sequence. When the
circuit is in state D, a 1 returns it to state B, and a 0 returns it to state A.
 0

A/0

B/0 1 0
0
0
1
C/0

D/1

State diagram
(Moore model)
Directed lines: X
Circles: state-code/Z
 Digital Systems Design (DSD)

4th Year Electrical Engineering Dept.

Lecture 2 (16/3/2020)

Design of Synchronous State Machines

STEP 2: Construction of State Table

• The information that exists in the state diagram is tabulated in what is called the state table.
• The state table consists of three columns.

• The first column is for the present state of the

circuit.

• The second column is for the next states that correspond for each present state in the first column and for
different combinations of input values.

• The third column is as the second column, but for the output(s) of the circuit.
Referring to the example in (Lecture 1), the state – table of the Mealy model is as
follows:

Mealy State - Table

Present Next State Output (Z)
State Input (X) Input (X)
0 1 0 1

A A B 0 0
B C B 0 0
C A D 0 1
D A B 0 0

The state – table of the Moore model is as follows:

Moore State - Table

Present Next State Output (Z)
State Input (X)
0 1

A A B 0
B C B 0
C A D 0
D A B 1

It is clear that the output column in the Moore state – table has a unique value for
each state.
Example :

Develop the state–diagram and state–table for a circuit that continuously compares
two (four-bit) serial message channels, on a repetitive basis, and gives an output
(Z=1) when coincidence is found.

Solution :

We have two message inputs of the form (just for clarity):

Channel X1 : 1101 1111 1000 1110 0001 etc.
Channel X2 : 0001 1101 0011 1111 0001 etc.
Clock timing : 1234 1234 1234 1234 1234
and we want to compare each four-bit word in turn, signaling an output when they
are identical, as in the last word above.

1
01/0, 10/0 00/0, 11/0

3 2
00/0, 01/0, 00/1, 01/0,
10/0, 11/0 00/0, 01/0, 00/0, 11/0 10/0, 11/1
10/0, 11/0 01/0, 10/0

5 4
00/0, 01/0,
10/0, 11/0 00/0, 11/0
01/0, 10/0
7 6

State - Diagram
If an identical pattern appeared on both input lines, the path through the state –
diagram, starting from initial state 1, would be via states 2, 4, 6 and back to state 1.
If we have had different inputs, the messages cannot be identical and we must wait
for the next word, this is the reason for the delaying path via states 3, 5, 7 (it can be
entered at any stage of the four-bit comparison).

State - Table
Present Next State
State Inputs (X X ) Output (Z)
1 2
Inputs (X1 X2)
00 01 10 11 00 01 10 11

1 2 3 3 2 0 0 0 0
2 4 5 5 4 0 0 0 0
3 5 5 5 5 0 0 0 0
4 6 7 7 6 0 0 0 0
5 7 7 7 7 0 0 0 0
6 1 1 1 1 1 0 0 1
7 1 1 1 1 0 0 0 0

The Mealy model is used in the solution of the above example.

Note :
If you have any questions about this lecture, please don’t hesitate to write to me.
 Explanatory Appendix (DSD2)

This appendix is to make more explanation to the solution of the example in

DSD2.

Example :

Develop the state–diagram and state–table for a circuit that continuously compares
two (four-bit) serial message channels, on a repetitive basis, and gives an output
(Z=1) when coincidence is found.

Solution :

We have two message inputs of the form (just for clarity):

Channel X1 : 1101 1111 1000 1110 0001 etc.
Channel X2 : 0001 1101 0011 1111 0001 etc.
Clock timing : 1234 1234 1234 1234 1234
and we want to compare each four-bit word in turn, signaling an output (Z=1)
when they are identical, as in the last word above.
Here, the circuit has two inputs X1 and X2 , so there are four combinations to be
considered (X1 X2 = 00, 01, 11, 10). When drawing the state-diagram, in each state
the four combinations are considered.

At first, the circuit is in state 1 (the starting state), there are four possibilities of
values of the first inputs. If they are equal (i.e. X1 X2 = 00, or 11), then the first bits
of X1 X2 are equal and the circuit goes to state 2 to check the second bits of X1 and
X2 .

1
01/0, 10/0 00/0, 11/0

3 2
The output Z = 0, the values of (X1 X2 / Z) are written on the arrow from state 1 to
state 2.

The other possibility is that the values of the first inputs are not equal (i.e. X 1 X2 =
01, or 10), the circuit goes to state 3. The output Z = 0, the values of (X1 X2 / Z) are
written on the arrow from state 1 to state 3.

The circuit reaches state 2 when the first inputs of X1 and X2 are equal. In (state 2)
the circuit tests the second inputs of X1 and X2 , if they are equal then the circuit
moves to state 4, otherwise, it moves to state 5.

1
01/0, 10/0 00/0, 11/0

3 2

00/0, 11/0
01/0, 10/0

5 4

The circuit reaches state 3 when the first inputs of X1 and X2 are not equal. In
(state 3) the circuit tests the second inputs of X1 and X2 , whatever they are equal
or not the circuit moves to state 5, because the equality of four-bit of X1 and X2
will not be satisfied.

1
01/0, 10/0 00/0, 11/0

3 2
00/0, 01/0, 00/0, 11/0
10/0, 11/0 01/0, 10/0

5 4
The circuit reaches state 4 when the first and the second bits of X1 and X2 are
equal. Now, state 4 will test the third bits of X1 and X2 , if they are equal the circuit
moves to state 6, otherwise it moves to state 7.

1
01/0, 10/0 00/0, 11/0

3 2
00/0, 01/0, 00/0, 11/0
10/0, 11/0 01/0, 10/0

5 4

00/0, 11/0
01/0, 10/0
7 6

The circuit reaches state 5 when either the first and the second bits of X1 and X2
are not equal, or the first bits of X1 and X2 are equal but the second bits are not.

In (state 5) the circuit tests the third inputs of X1 and X2 , whatever they are equal
or not the circuit moves to state 7, because the equality of four-bit of X1 and X2
will not be satisfied.

1
01/0, 10/0 00/0, 11/0

3 2
00/0, 01/0, 00/0, 11/0
10/0, 11/0 01/0, 10/0

5 4
00/0, 01/0,
10/0, 11/0 00/0, 11/0
01/0, 10/0
7 6
The circuit reaches state 6 when the first, second, and third bits of X1 and X2 are
equal. In (state 6), the circuit tests the fourth bits of X1 and X2 if they are equal
then the output (Z = 1) and the circuit moves back to state 1 to start a new cycle of
testing. Otherwise the output (Z = 0).

1
01/0, 10/0 00/0, 11/0

3 2
00/1, 01/0,
00/0, 01/0, 00/0, 11/0 10/0, 11/1
10/0, 11/0 01/0, 10/0

5 4
00/0, 01/0,
10/0, 11/0 00/0, 11/0
01/0, 10/0
7 6

In (state 7), the circuit moves back to state 1 for all combinations of X1 and X2 with
the output (Z = 0).
If an identical pattern appeared on both input lines, the path through the state –
diagram, starting from initial state 1, would be via states 2, 4, 6 and back to state 1.
If we have had different inputs, the messages cannot be identical and we must wait
for the next word, this is the reason for the delaying path via states 3, 5, 7 (it can be
entered at any stage of the four-bit comparison).
 1
01/0, 10/0 00/0, 11/0

3 2
00/0, 01/0, 00/1, 01/0,
10/0, 11/0 00/0, 01/0, 00/0, 11/0 10/0, 11/1
10/0, 11/0 01/0, 10/0

5 4
00/0, 01/0,
10/0, 11/0 00/0, 11/0
01/0, 10/0
7 6

State-Diagram

State - Table
Present Next State
State Inputs (X X ) Output (Z)
1 2
Inputs (X1 X2)
00 01 10 11 00 01 10 11

1 2 3 3 2 0 0 0 0
2 4 5 5 4 0 0 0 0
3 5 5 5 5 0 0 0 0
4 6 7 7 6 0 0 0 0
5 7 7 7 7 0 0 0 0
6 1 1 1 1 1 0 0 1
7 1 1 1 1 0 0 0 0

The Mealy model is used in the solution of the above example.

 Digital Systems Design (DSD)

4th Year Electrical Engineering Dept.

Lecture 3 (24/3/2020)

Design of Synchronous State Machines

STEP 3: Reduction of Internal States

The state-table, in step 2, may contain redundant states that should be eliminated
for minimal circuit design. Step 3 is concerned with the detection and elimination
of these redundant states.
The detection of redundant states is accomplished by using the implication chart
method.
The implication chart is shown below.

Implication Chart
The implication chart is a half-matrix of squares.
The number of rows = The number of columns = The number of the circuit’s states
Each square in the implication chart is the coincidence of two states, one presents
the row and the other presents the column.
For example, consider the state machine whose state-table is shown below.

Table (a): State-Table

Present Next State Output (Z)
State Input (X) Input (X)
0 1 0 1
1 8 3 0 0
2 8 6 0 0
3 8 1 1 0
4 1 8 1 0
5 4 7 0 0
6 4 2 1 0
7 4 5 1 0
8 5 4 1 0

Since there are 8 states then the implication chart should be

2
3

1 2 3 4 5 6 7
The rows are numbered (2, 3, …, 8) while the columns are numbered (1, 2, …, 7).
The first square is the coincidence of states 1 and 2 as shown below.

2
3

1 2 3 4 5 6 7

In this square, we should write the conditions that must be satisfied to make states
1 and 2 in the state-table equivalent.
Now, let us go back to the table (a), each row represents the next states and the
outputs of a present state. Any two present states are equivalent if they have the
same values of the outputs and next states. It is clear from the table below that
states 1 and 2 have the same output values. But, their next states are not identical.
Hence, there is a condition to be satisfied to make (state 1 = state 2). This condition
is that, (1 = 2) if (3 = 6). This condition is to be written in the first square of the
implication chart shown above.
Present Next State Output (Z)
State Input (X) Input (X)
0 1 0 1
1 8 3 0 0
2 8 6 0 0
 2 3,6
3

1 2 3 4 5 6 7

Similarly, the other squares in the implication chart are filled with the conditions of
equivalency. The next square is a coincidence of states 1 and 3. If we go to the
table (a) and compare state 1 with 3, we find that their output values are different.

Present Next State Output (Z)

State Input (X) Input (X)
0 1 0 1
1 8 3 0 0
2 8 6 0 0
3 8 1 1 0

In this situation, 1 ≠ 3 even if they have identical next states. Therefore, we write X
in the second square of states 1 and 3, as shown below.
It should be noted that if any two states are identical in their values of next states
and outputs then ( √ ) should be written in their corresponding square.
 2 3,6
3 X

1 2 3 4 5 6 7

The final implication chart is shown below.

2 3,6
3 X X

4 X X 1,8

5 4,8 4,8 X X
3,7 6,7
6 X X 4,8 1,4 X
1,2 2,8
7 X X 4,8 1,4 X 2,5
1,5 5,8
8 X X 5,8 1,5 X 4,5 4,5
1,4 4,8 2,4
1 2 3 4 5 6 7

Fig. (a)
When the chart is completed it is examined, starting from the extreme right-hand
column, for cells containing a cross.
The first cross occurs in column 5 for the state-pair (5, 8). Any other state-pairs
relying on (5, 8) for equivalence must also be crossed out, e.g. cells (4, 7) and (3,
8).

2 3,6
3 X X

4 X X 1,8

5 4,8 4,8 X X
3,7 6,7
6 X X 4,8 1,4 X
1,2 2,8
7 X X 4,8 1,4 X 2,5
1,5 5,8
8 X X 5,8 1,5 X 4,5 4,5
1,4 4,8 2,4
1 2 3 4 5 6 7

A convenient method of noting when an incompatible has been used is to mark the
cell by encircling the cross.
 2 3,6
3
X X

4 1,8
X X

5 4,8 4,8
3,7 6,7 X X

6 4,8 1,4
X X 1,2 2,8 X

7 4,8 1,4 2,5

X X 1,5 5,8 X

8 5,8 1,5 4,5 4,5

X X 1,4 4,8 X 2,4
1 2 3 4 5 6 7

The chart is processed in this way continuing with (5, 7), (5, 6), (4, 7), (4, 5), etc.

The final chart is shown below.

 2 3,6

3 X X

4 X X 1,8

4,8 4,8
5 3,7 6,7 X X

4,8 1,4
6 X X 1,2 2,8 X

4,8 1,4
7 X X 1,5 5,8 X 2,5

5,8 1,5 4,5

8 X X 1,4 4,8 X 2,4 4,5

1 2 3 4 5 6 7

Fig. (b)
The final step in the reduction process is to extract the equivalent states, sometimes
called pair-wise compatibles, from the chart (i.e. not crossed cells); reading from
the right-hand column of Fig. (b),
6 = 7, 4 = 8, 3 = 7, 3 = 6, 2 = 5, 1 = 5, 1 = 2
It can be deduced that (3 = 6 = 7) and (1 = 2 =5)
The minimal expression for the machine:
M = (1, 2, 5) (3, 6, 7) (4, 8)
Only one of the equivalent states is to be considered, while the others are
redundant states.
Thus states 2 and 5 are redundant and can be eliminated from the state-table (a).
Also, states 6 and 7 are redundant. Besides state 8 is redundant.
The reduced state-table (b) is shown below, note that states 1, 2, and 5 are replaced
by 1; likewise, 3, 6, and 7 are replaced by 3; 4 and 8 are replaced by 4.

Table (b): Reduced State-Table

Present Next State Output (Z)
State Input (X) Input (X)
0 1 0 1
1 4 3 0 0
3 4 1 1 0
4 1 4 1 0

Thus we have reduced the original eight-state machine (Table (a)) into a three-state
machine (Table (b)). Thus the final circuit will be simpler and with fewer
components. That is the importance of this step in the design of state machines.
Homework :
Reduce the following state-table using the implication chart method.
State - Table
Present Next State
State Inputs (X X ) Output (Z)
1 2
Inputs (X1 X2)
00 01 10 11 00 01 10 11

1 3 4 2 4 0 0 0 0
2 7 5 8 5 0 0 0 0
3 7 5 8 5 0 0 0 0
4 5 5 5 5 0 0 0 0
5 6 6 6 6 0 0 0 0
6 1 1 1 1 0 0 0 0
7 9 6 10 6 0 0 0 0
8 9 6 10 6 0 0 0 0
9 1 1 1 1 1 0 1 0
10 1 1 1 1 1 0 1 0

Your answers must be sent to me before (Monday 30/3/2020). Do not forget to

write your name in Arabic.
 Digital Systems Design (DSD)

4th Year Electrical Engineering Dept.

Lecture 4 (31/3/2020)

Design of Synchronous State Machines

STEP 4: State Assignments

Each state in the reduced state-table, from step 3, is represented by a symbol (a
letter or a number). Now, a binary code should be assigned for each state.
The simplest way to code states is to use the first integers in binary counting
order as shown in Table (1).

Table (1)

State Binary Assignment

y1 y2 y3

1 000

2 001

3 010

4 011

5 100
⋮ ⋮
Consider the state-table given below.
State-table
Present Next State Output (Z)
State Input (X) Input (X)
0 1 0 1
1 2 3 0 0
2 4 3 0 0
3 2 5 0 0
4 6 3 0 0
5 2 7 0 0
6 6 3 1 0
7 2 7 0 1

Now, we shall assign a binary code for each state as was shown in Table (1).
Since there are 7 states, then 3 bits are enough to assign a binary code for each
state. These 3 bits are denoted as 𝐲𝟏 𝐲𝟐 𝐲𝟑 . Then the state-table is rewritten with
binary codes instead of numbers as shown below. The new table is called the
binary-assignment table.
Binary-assignment table
Present Next State Output (Z)
State Input (X) Input (X)
0 1 0 1
𝐲𝟏 𝐲𝟐 𝐲𝟑 + + + + + +
𝐲𝟏 𝐲𝟐 𝐲𝟑 𝐲𝟏 𝐲𝟐 𝐲𝟑
000 001 010 0 0
001 011 010 0 0
010 001 100 0 0
011 101 010 0 0
100 001 110 0 0
101 101 010 1 0
110 001 110 0 1

Note that the bits in the next state column are denoted 𝐲𝟏+ 𝐲𝟐+ 𝐲𝟑+ as representing
the next values of 𝐲𝟏 𝐲𝟐 𝐲𝟑 .
Now, let us take an example to review the previous four steps of designing
synchronous state machines.
Example :
Suppose we wish to design a circuit that detects a sequence of three or more
consecutive 1’s in a string of bits coming through an input line (i.e., the input is a
serial bit stream). Use the Moore model in the design.
Solution :
The circuit has one input (X) and one output (Z). The input is a serial bit stream
and the output becomes 1 when three or more consecutive 1’s occurs. To clarify
the problem consider the following:
X=0 1 1 0 0 1 1 1 0 0 1 1 1 1 1 0 0
Z=0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 0 0
Step 1: Drawing the state-diagram.
Starting with state S0 , the starting state. If the input is 0, the circuit stays in S0 ,
but if the input is 1, it goes to state S1 to indicate that a 1 was detected. The
outputs of states S0 and S1 are 0’s written inside the two state circles because the
Moore model is used in the design.

1
S0 /0 S1 /0
If the next input is 1, the change is to state S2 to indicate the arrival of two
consecutive 1’s, but if the input is 0, the state goes back to S0 .

0 0

1
S0 /0 S1 /0

S2 /0

In state S2 , if the input is 0 the circuit goes back to S0 . While the third
consecutive 1 sends the circuit to state S3 and the output becomes 1.

0 0

1
S0 /0 S1 /0

0
1

S3 /1 S2 /0
1
If more 1’s are detected, the circuit stays in S3 . Any 0 input sends the circuit to
S0 . In this way, the circuit stays in S3 as long as there are three or more
consecutive 1’s received.

0 0

1
S0 /0 S1 /0

0
0 1

S3 /1 S2 /0
1

1
State-Diagram

Step 2 : Construction of state-table.

The state-table is derived from the state-diagram. This is done in Table (a).

Table (a) : State-Table

Present Next State

State Input (X) Output (Z)
0 1
S0 S0 S1 0
S1 S0 S2 0
S2 S0 S3 0
S3 S0 S3 1
Step 3 : Reduction of internal states.
In this step, we have to discover any redundant states in Table (a) and then
removed them from the table. This is accomplished by using the implication
chart shown below.

S1 S1, S2

S2 S1, S3 S2, S3

S3 X X X

S0 S1 S2

Implication Chart

The last crossed cell in the chart is (S2, S3). The cell (S1, S2) contains (S2, S3),
therefore it should be crossed as shown below.

S1 S1, S2

S2 S1, S3 S2, S3

S3 X X X

S0 S1 S2

Now, the cell (S2, S3) should be encircled, as is shown below.

 S1 S1, S2

S2 S1, S3 S2, S3

S3 X X X

S0 S1 S2

The next crossed cell is (S1, S3). The cell (S0, S2) contains (S1, S3), so it must be
crossed, as below.

S1 S1, S2

S2 S1, S3 S2, S3

S3 X X X

S0 S1 S2

After that, the cell (S1, S3) is to be encircled, as below.

 S1 S1, S2

S2 S1, S3 S2, S3

S3 X X X

S0 S1 S2

The next crossed cell is (S1, S2). The cell (S0, S1) contains (S1, S2), hence it must
be crossed, as bellow.

S1 S1, S2

S2 S1, S3 S2, S3

S3 X X X

S0 S1 S2

The cell (S1, S2) is encircled as shown below.

 S1 S1, S2

S2 S1, S3 S2, S3

S3 X X X

S0 S1 S2

The next crossed cell is (S0, S3). However, there is no cell contains (S0, S3). We
encircle this cell as below.

S1 S1, S2

S2 S1, S3 S2, S3

S3 X X X

S0 S1 S2

The next crossed cell is (S0, S2). However, there is no cell contains (S0, S2). We
encircle this cell as below.
 S1 S1, S2

S2 S1, S3 S2, S3

S3 X X X

S0 S1 S2

Finally, the cell (S0, S1) is encircled as shown below.

S1 S1, S2

S2 S1, S3 S2, S3

S3 X X X

S0 S1 S2

All the cells of the implication chart are crossed. Therefore, there is no redundant
states (i. e., no equal states) and no reduction in the state-table (a).
Step 4 : State assignments.
The four states are binary assigned as follows:

State symbol y1 y2
S0 00
S1 01
S2 10
S3 11

Now, the state-table (a) is rewritten by replacing the state symbols with their
corresponding codes to obtain the binary-assignment table (b).

Table (b) : Binary-assignment table

Present Next State

State Input (X) Output (Z)
0 1
+ + + +
y1 y2 𝐲𝟏 𝐲𝟐 𝐲𝟏 𝐲𝟐
00 00 01 0
01 00 10 0
10 00 11 0
11 00 11 1

In the next lecture, we will discuss the final step of the synchronous state
machines design.
 Digital Systems Design (DSD)

4th Year Electrical Engineering Dept.

Lecture 5 (7/4/2020)

Design of Synchronous State Machines

STEP 5: Circuit Realization

This step is the last in the design. Now, it is required to select one of the four
types of flip flops (SR, D, T, JK) for realizing the circuit. For simplicity, the D
flip flops are used.
In this step, we will derive from the binary-assignment table of step 4:
 the input equations of the flip flops.
 the outputs equations.
Finally, the circuit diagram is drawn.
The number of flip flops needed = the number of bits (y1, y2, …etc.) in the binary-
assignment table. For example, in the binary-assignment table of the previous
lecture, each state was represented by two bits y1 and y2. Hence two flip flops are
needed to realize the circuit. One flip-flop is used to store bit y1, while the other is
used to store bit y2 .
Let us consider the binary-assignment table of the previous lecture shown below

Table (b) : Binary-assignment table

Present Next State

State Input (X) Output (Z)
0 1
+ + + +
y1 y2 𝐲𝟏 𝐲𝟐 𝐲𝟏 𝐲𝟐
00 00 01 0
01 00 10 0
10 00 11 0
11 00 11 1

We choose two D flip flops to represent the four states, and we label their
outputs y1 and y2. The circuit has one input X and one output Z.
The characteristic equation of the D flip-flop is Q+ = D.
That means the next-state values in the binary-assignment table specify the D
input condition for the flip-flop.
The flip-flop input equations can be obtained directly from the next-state
columns of 𝐲𝟏+ and 𝐲𝟐+ and expressed in sum-of-minterms form and simplified
by K-map as shown below.

X
X
y1 y2 0 1
00

01
y2
11
y1
10
At first, let us derive the equation D1. The K-map is filled with the values of 𝐲𝟏+
in the binary-assignment table as shown below.

X
X
y1 y2 0 1
00 0 0

01 0 1
y2
11 0 1
y1
10 0 1

D1 = 𝐲𝟏+ = X y1 + X y2

Similarly, the input equation of the second flip-flop D2 is derived. But, at this
time the K-map is filled with the values of 𝐲𝟐+ in the binary-assignment table.

X
X
y1 y2 0 1
00 0 1

01 0 0
y2
11 0 1
y1
10 0 1

D2 = 𝐲𝟐+ = X y1 + X ̅̅̅
𝐲𝟐
The equation of the output (Z) is independent of input X because the Moore
model is used. It can be deduced directly from the binary-assignment table as:
Z = y1 y2
Finally, the state machine is drawn depending on the three Boolean equations:

D1 = 𝐲𝟏+ = X y1 + X y2

D2 = 𝐲𝟐+ = X y1 + X ̅̅̅
𝐲𝟐

Z = y1 y2

X
D Q
y1

̅
𝐐

Z
D Q
y2

̅
𝐐

Clock
Example :
Design the state machine whose state-assignment table is shown below.

Binary-assignment table
Output (Z)
Present Next State
State Input (X) Input (X )
0 1
+ + + + + +
y1 y 2 y3 𝐲𝟏 𝐲𝟐 𝐲𝟑 𝐲𝟏 𝐲𝟐 𝐲𝟑 0 1
000 000 010 0 0
001 011 110 0 1
010 010 000 0 0
011 011 001 0 1
100 001 101 1 0
101 010 100 1 0

Solution :
From the table, it is clear that the circuit has one input (X) and one output (Z).
Each state is represented by three bits (y1 y2 y3 ), therefore three D flip flops are
needed to realize the circuit.

Now we have to derive three equations for the inputs of the flip flops, as well as
an equation for the output (Z), to realize the circuit.

Each equation is a function of four parameters (y1 ,y2 ,y3 and X ). These
equations are to be simplified by K- maps. The K-map is as shown below.
 X
X y1
y2 y3 00 01 11 10
00

01
y3
11
y2
10

y1

At first, let us derive the equation D1. The K-map is filled with the values of 𝐲𝟏+
in the binary-assignment table as shown below. Of course, the cases not exist in
the table, their values are don’t care (or x) in the K-map.

X
X y1
y2 y3 00 01 11 10
00 0 0 1 0
01 0 0 1 1
y3
11 0 x x 0
y2
10 0 x x 0

y1
D1 = 𝐲𝟏+ = X y1 + X ̅̅̅
𝐲𝟐 y3
Similarly, the input equation of the second flip-flop D2 is derived. But, at this
time the K-map is filled with the values of 𝐲𝟐+ in the binary-assignment table.

‫اﻷﺗﺣﺎد ذو اﻟﻌﻧﺻرﯾن ﯾﺣذف ﻣﺗﻐﯾر واﺣد واﻷﺗﺣﺎد‬

‫ذو اﻻرﺑﻊ ﻋﻧﺎﺻر ﯾﺣذف ﻋﻧﺻرﯾن‬
X
X y1 ‫واﻻﺗﺣﺎد ذو اﻟﺛﻣﺎن ﻋﻧﺎﺻر‬
y2 y3 ‫ﯾﺣذف ﺛﻼﺛﺔ ﻋﻧﺎﺻر‬
00 01 11 10
00 0 0 0 1
01 1 1 0 1
y3
11 1 x x 0
y2
10 1 x x 0

y1

̅ y2 + 𝐗
D2 = 𝐲𝟐+ = 𝐗 ̅ y3 + X ̅̅̅
𝐲𝟏 ̅̅̅
𝐲𝟐

Similarly, the input equation of the third flip-flop D3 is derived. But, at this time
the K-map is filled with the values of 𝐲𝟑+ in the binary-assignment table.
X
X y1
y2 y3 00 01 11 10
00 0 1 1 0
01 1 0 0 0
y3
11 1 x x 1
y2
10 0 x x 0

y1
D3 = 𝐲𝟑+ = y2 y3 + y1 ̅̅̅ ̅ ̅̅̅
𝐲𝟑 + 𝐗 𝐲𝟏 y3
The equation of the output (Z) is derived as below. Here, the values of (Z) in the
state-assignment table are inserted in the K-map.

X
X y1
y2 y3 00 01 11 10
00 0 1 0 0
01 0 1 0 1
y3
11 0 x x 1
y2
10 0 x x 0

y1
̅ y1 + X ̅̅̅
Z= 𝐗 𝐲𝟏 y3

Finally, the state machine is drawn depending on the four Boolean equations:

D1 = 𝐲𝟏+ = X y1 + X ̅̅̅
𝐲𝟐 y3

̅ y2 + 𝐗
D2 = 𝐲𝟐+ = 𝐗 ̅ y3 + X ̅̅̅
𝐲𝟏 ̅̅̅
𝐲𝟐

D3 = 𝐲𝟑+ = y2 y3 + y1 ̅̅̅ ̅ ̅̅̅

𝐲𝟑 + 𝐗 𝐲𝟏 y3

̅ y1 + X ̅̅̅
Z= 𝐗 𝐲𝟏 y3
In this lecture, we have finished the various steps of synchronous state machines
design. These steps are:
 Construction of state diagram.
 Construction of state-table.
 Simplification of state-table.
 State assignment.
 Derivation of next-state and output functions.
 Implementation of the circuit.

After reviewing the previous lectures (1 – 5), do the following homework.

Your answers should be before Monday 13/4/2020.

Homework :
Design a Mealy synchronous state machine that has one input (X) and one output
(Z). The output Z = 1 if the total number of 1’s received is 3 or a multiple of 3.
 Digital Systems Design (DSD)

4th Year Electrical Engineering Dept.

Lecture 6 (14/4/2020)

Analysis of Synchronous State Machines

The analysis process is the reverse of the design process. Here, we have a
designed state machine (or sequential logic circuit) and it is required to obtain its
state-diagram.

In the design, we start with a state-diagram and end with the circuit diagram. But
in the analysis, we start with the circuit diagram and end with the state-diagram.

Therefore in the analysis, the steps of design are applied reversely:

 From the circuit diagram, the equations of the flip flops inputs as well as
the output(s) equation(s) are derived.
 Drawing the K-map of each equation.
 Construction of the binary-assignment table.
 Obtaining the state-table.
 Drawing the state-diagram.
Example 1 :
Let us analyze the following synchronous sequential circuit.

X1
D Q Z
y1

̅
𝐐

X2 D Q
y2

̅
𝐐

Clock

The following equations are derived from the circuit diagram:

D1 = X1 + ̅̅̅
y2
D2 = X2 + ̅̅̅̅
y1
Z = y1
Since Z is independent of the input X, so the circuit was designed by the Moore
model.
The K-map of the equation D1 = X1 + ̅̅̅
y2 is obtained as follows:
The first term in the equation is X1, the cells in the K-map that gives the value of
the group shown in blue color are filled by 1. The Boolean expression of this
group is X1.

X1
X1 X2
y1 y2 00 01 11 10
00 1 1
01 1 1
y2
11 1 1
y1
10 1 1

X2

Similarly, the other term of equation D1 is ̅̅̅

y2 and is shown by the red group in the
K-map.

X1
X1 X2
y1 y2 00 01 11 10
00 1 1 1 1
01 1 1
y2
11 1 1
y1
10 1 1 1 1

X2
Now, the blank cells are filled by 0. The final K-map of the equation
D1 = 𝐲𝟏+ = X1 + ̅̅̅
y2
is shown below.

X1
X1 X2
y1 y2 00 01 11 10
00 1 1 1 1
01 0 0 1 1
y2
11 0 0 1 1
y1
10 1 1 1 1

X2
D1 = 𝐲𝟏+ = X1 + ̅̅̅
y2

Similarly, the K-map of the equation D2 = X2 + ̅̅̅̅

y1 is derived as below.

X1
X1 X2
y1 y2 00 01 11 10
00 1 1 1 1
01 1 1 1 1
y2
11 0 1 1 0
y1
10 0 1 1 0

X2
D2 = 𝐲𝟐+ = X2 + ̅̅̅̅
y1
The binary-assignment table is obtained by collecting together the values of 𝐲𝟏+ and
𝐲𝟐+ shown in the above two K-maps.
Binary-assignment table

Present Next State

State Inputs (X1 X2) Output (Z)
00 01 11 10
y1 y2 𝐲𝟏+ 𝐲𝟐+ 𝐲𝟏 𝐲𝟐 𝐲𝟏+ 𝐲𝟐+
+ +
𝐲𝟏+ 𝐲𝟐+
00 11 11 11 11
01 01 01 11 11
11 00 01 11 10
10 10 11 11 10

Since Z = y1 then the last column of Z values is filled with the same values of y 1 in
the first column. The final binary-assignment table will be:

Binary-assignment table

Present Next State

State Inputs (X1 X2) Output (Z)
00 01 11 10
y1 y2 𝐲𝟏+ 𝐲𝟐+ 𝐲𝟏 𝐲𝟐 𝐲𝟏+ 𝐲𝟐+
+ +
𝐲𝟏+ 𝐲𝟐+
0 0 11 11 11 11 0
0 1 01 01 11 11 0
1 1 00 01 11 10 1
1 0 10 11 11 10 1
In the state-assignment table, each state is denoted by a binary code. Now, we have
to represent the states by symbols instead of codes.

State code State symbol

00 S1

01 S2

11 S3

10 S4

State-Table

Present Next State

State Inputs (X1 X2) Output (Z)
00 01 11 10

S1 S3 S3 S3 S3 0
S2 S2 S2 S3 S3 0
S3 S1 S2 S3 S4 1
S4 S4 S3 S3 S4 1

Finally, the state-diagram is constructed from the above state-table.

 11 00, 01, 11, 10

00
S3 /1 S1 /0

10, 11
10
01, 11
01

S4 /1 S2 /0

00, 10 00, 01

State Diagram
Example 2 :
Give the state-diagram of a synchronous sequential logic circuit that has one input
X and three outputs Z1, Z2, and Z3. It consists of two D flip flops y1 and y2. The
flip-flop input equations and the equations of the outputs are:
y1 y2 X + y1 ̅̅̅
D1 = ̅̅̅̅ X
D2 = ̅̅̅̅ y2 X + y2 ̅̅̅
y1 ̅̅̅̅ X
Z1 = ̅̅̅̅
y1 ̅̅̅̅
y2
Z2 = y1 ̅̅̅̅
y2 X
Z3 = y1 y2
Solution :

X
X
y1 y2 0 1
00 0 0

01 0 1
y2
11 1 0
y1
10 1 0

y1 y2 X + y1 ̅̅̅
D1 = 𝐲𝟏+ = ̅̅̅̅ X

X
X
y1 y2 0 1
00 0 1

01 1 0
y2
11 1 0
y1
10 0 0

D2 = 𝐲𝟐+ = ̅̅̅̅ y2 X + y2 ̅̅̅

y1 ̅̅̅̅ X
 Binary-assignment table

Present Next State Outputs

State Input (X) Input (X)
0 1 0 1
+ + + + Z Z Z Z Z Z
y1 y2 𝐲𝟏 𝐲𝟐 𝐲𝟏 𝐲𝟐 1 2 3 1 2 3
00 00 01 1 0 0 1 0 0
01 01 10 0 0 0 0 0 0
11 11 00 0 0 1 0 0 1
10 10 00 0 0 0 0 1 0

Let S1 = 00, S2 = 01, S3 = 11, S4 = 10. Therefore, the above table becomes

State table

Present Next State Outputs

State Input (X) Input (X)
0 1 0 1
Z1Z2Z3 Z1Z2Z3
S1 S1 S2 1 0 0 1 0 0
S2 S2 S4 0 0 0 0 0 0
S3 S3 S1 0 0 1 0 0 1
S4 S4 S1 0 0 0 0 1 0
 0 / 100

1 / 001
S1 S3

0 / 001
1 / 100 1 / 010

S2 S4
1 / 000

0 / 000 0 / 000

State Diagram

Homework :
Draw the state diagram of a synchronous sequential logic circuit with two D flip
flops y1 and y2, two inputs X1 and X2, and one output Z. It is specified by the
following next-state and output equations:

y1+ = X1 ̅̅̅̅
X 2 + X 1 y2

y +2 = X1 y1 + X1 ̅̅̅̅
y2

Z = y1
 Digital Systems Design (DSD)

4th Year Electrical Engineering Dept.

Lecture 7 (21/4/2020)

Design of Asynchronous State Machines

The previous lectures discussed the design and analysis of synchronous state
machines. This lecture starts discussing the design of asynchronous state
machines. The main difference between the two types of state machines is that
there is no master clock in asynchronous circuits. This clock controls the
operation of the synchronous state machine, where the circuit changes its present
state to the next state after the application of the clock. While in the
asynchronous state machines, there is no clock to control its operation and the
circuit changes its present state to the next state whenever the inputs change
values.

The steps of the design of the asynchronous state machines differ slightly from
those of the synchronous state machines. Three points are to be explained before
discussing the steps of the design of asynchronous machines.

1. We have to consider two possible conditions for an asynchronous circuit, the

stable and unstable states. An asynchronous sequential network is stable for
a given input state if the next state is the same as the present state; while it is
unstable for a given input state if the next state and present state are not the
same. ‫ ﻴﺠب ان ﻴﻛون اﻟﻨظﺎم‬stable ‫ﻓﻲ ﺤﺎﻟﺔ‬
‫ﺤﺼل ﺘﺸﺎﺒﻪ ﺒــ‬
present state & next state ‫ﻓﻲ‬
‫ﻨﻔس اﻟﺴطﺮ او اﻟﺤﺎﻟﺔ‬
‫ ﻓﻲ ﺣﺎﻟﺔ ﻛﺎن اﻟﻧظﺎم‬unstable
‫اﻟواﺤدة‬
‫ﻓﮭﻧﺎ ال ﯾوﺟود ﺗﺷﺎﺑﮫ ﻓﻲ‬
present state & next
state
2. To avoid the “race” problem, not more than a single input is allowed to be
changed at a time. In this way, two successive input states differ in only the
change of one bit in their n-tuples. For example, if the present two inputs of
the asynchronous state machine are 00, then the next input values should not
be 11, it should be either 01 or 10. Also, if the present input values are 01,
then the next input values should not be 10, it should be either 00 or 11.
‫ھﻧﺎ ال ﯾﺟوز ان ﯾﺣﺻل اﻧﺗﻘﺎل ﺑﻣرﺗﺑﺗﯾن ﻣن اﻟﺑﺗﺎت‬
‫ﻓﻲ آن واﺣد واﻧﻣﺎ ﯾﻛون اﻟﺗﻐﯾر ﺑواﺳطﺔ ﺑت واﺣدة‬
‫ﻓﻘط‬
3. When deriving the equations of the flip-flop inputs and circuit outputs using
K-map, if there are two adjacent 1’s such that each one of them belongs to a
different group then a static 1-hazard problem occurs. For example, consider
the K-map of the Boolean equation Z = X y2 + y1 ̅̅̅
y2 shown below. There is a
static 1-hazard problem since there are two adjacent 1’s and each one of them
belongs to a different group.

X
X ‫ﻻﯾﺟوز ﺗرك واﺣدﯾن ﻣﺗﺟﺎورﯾن‬
y1 y2 0 1 ‫ﻓﻲ ﺧﺎرطﺔ ﻛﺎرﻧوف ﻣن ﻏﯾر‬
00 ‫ﺿﻣﮭم ﺑﺎﺗﺣﺎد‬
0 0

01
0 1
y2
11
0 1
y1
10
1 1 Static 1-hazard

Z = X y2 + y1 ̅̅̅
y2
To overcome this hazard problem, we have to add a third group (shown in blue)
that covers these two adjacent 1’s as shown below. The Boolean equation
becomes: Z = X y2 + y1 ̅̅̅
y2 + X y1.

X
X
y1 y2 0 1
00
0 0

01
0 1
y2
11
0 1
y1
10
1 1
To remove the hazard

Z = X y2 + y1 ̅̅̅
y2 + X y1

Thus, in asynchronous state machine design, it is not allowed for two adjacent 1’s
in the K-map to be not included in a single group. Otherwise, a static 1-hazard will
occur.

In summary, the above three points have to be considered during

the design of asynchronous state machines.
 Step 1: Construction of state diagram

The construction of state diagram in asynchronous state machines differs in the

following points from that of synchronous state machines:
 There is a stable condition in each state (i.e., the circuit stays in the same
state for a certain value of inputs).
 For each state, the combinations of input values that differ in more than a
single input change than those of the stable condition are inhibited.
Example :
Design an asynchronous state machine which detects the sequence (00, 10, 11) on
two parallel input lines X1 and X2 and gives a (Z = 1) output during the final
combination. This output must go to 0 on the next input changes. Use the Moore
model in the design.
Solution :
The first step in the design is the construction of the state diagram.
At first, the circuit is in state 1. If the first inputs are 00, then the circuit stays in
state 1 and the circuit is in a stable condition. If the next inputs are 10, then the
circuit moves to state 2; while if the next inputs are 01, then the circuit moves to
state 3. The combination that the next inputs are 11 is not allowed in asynchronous
state machines to avoid the race problem.

00

1/0
01 10

3/0 2/0
Let us complete drawing the state diagram, the circuit reaches state 2 when the
input sequence (00, 10) has occurred. In state 2, if the inputs are still 10, then the
circuit stays in state 2 and this is a stable condition. But if the next inputs are 00,
then the circuit goes back to state 1. If the next inputs are 11, then the circuit
moves to state 4 and the output becomes 1 because the input sequence (00, 10, 11)
has occurred. Of course, in state 2 the inputs combination 01 is not allowed to
avoid a race problem. The state diagram becomes as below.

00

1/0 00
01 10

10
3/0 2/0

11

4/1
The circuit reaches (state 3) coming from (state 1) when input values 01 are
received. It stays in (state 3) as long as the inputs are 01, and this is a stable
condition. Here, the inputs combination 10 is not permissible to avoid the race
problem. If the combination of the next input is 00, then the circuit goes back to
(state 1); but if it is 11 will cause the circuit to move to (state 5). The state diagram
becomes as below.

00

00 1/0 00
01 10
01 10
3/0 2/0

11 11

5/0 4/1
Similarly, the circuit stays in (state 4) as long as the received input combinations
are 11. Here, the next inputs combination 00 is not permissible to avoid the race
problem. If the next input combinations are 01, then the circuit goes to (state 3).
While the next input combinations 10 cause to move the circuit to (state 6). The
state diagram will be as shown below.

00

00 1/0 00
01 10
01 10
3/0 2/0

11 01 11

5/0 4/1 11

10

6/0
Similarly, the last two states 5 and 6 are constructed as shown in the state diagram
shown below.

00

00 1/0 00
01 10
01 10
3/0 2/0

01 11 01 11

11 5/0 4/1 11
00
10
10
11
6/0

10

State Diagram

Now, it is clear that in asynchronous state machines, each state has a

stable condition shown by a closed arrow in the state diagram. Also,
in each state, the input combinations of more than a single bit
change are ignored.
These are the main differences between the synchronous and
asynchronous construction of state diagrams.
 Step 2: Construction of Primitive Flow Table

Like in the design of synchronous state machines, after the construction of the state
diagram it is required to tabulate the information in that diagram. That table is
called the (primitive flow-table) in asynchronous state machines. It differs slightly
from the state-table of the synchronous state machines.
Let us construct the primitive flow-table of the state diagram in step 1 as shown
below.
Each row in the table is concerned with a stable state. The first row is concerned
with the first state (state 1). The stable state is encircled in the table. The circuit is
stable in (state 1) when the inputs X1 X2 = 00, therefore we write 1 in column
00. The input values X1 X2 = 11 is not permissible, hence a ─ is written in column
11. The input values X1 X2 = 01 causes the circuit to move from (state 1) to (state
3), and this is an unstable condition. Therefore, we write 3 in column 01. Similarly,
we write 2 in column 10. In the output column, we write the value of (Z) when the
circuit is stable in (state 1) which is 0. The first row of the table is shown below.

Inputs X1 X2 Output (Z)

00 01 11 10

1 3 ─ 2 0

By following the same manner, we continue the filling of the table items.
The final primitive flow-table will be:

Inputs X1 X2 Output (Z)

00 01 11 10

1 3 ─ 2 0

1 ─ 4 2 0

1 3 5 ─ 0

─ 3 4 6 1

─ 3 5 6 0

1 ─ 5 6 0

Primitive Flow-Table

Homework:
An asynchronous sequential logic circuit has two inputs X1 and X2. The output Z
must go to 1 at the end of the input sequence X1 X2 = 00, 01, 11. This output must
go to 0 on the next input changes. Using the Moore model, find the state diagram
and the primitive flow-table of the circuit.
 Digital Systems Design (DSD)

4th Year Electrical Engineering Dept.

Lecture 8 (5/5/2020)

Design of Asynchronous State Machines

Step 3: Reduction of the primitive flow-table

In step 2, the primitive flow-table was constructed. In this step, reduction to that
table must be made to obtain a minimal size circuit.

The primitive flow-table consists of two columns. The first is for the next states,
and the second is for outputs. In each row, there is a single stable state. Each
stable condition of a state is encircled.

The reduction process consists of two phases:

 Phase (a): The elimination of the redundant stable states using the
implication chart method.
 Phase (b): The merging of rows that are possible to be merged. There will
be more than a single stable state in a row.
Example :
Let us consider the following primitive flow-table of a Mealy designed state
machine and start explaining how the two phases of reduction are made.

Next States Output (Z)

Inputs X1 X2 Inputs X1 X2
00 01 11 10 00 01 11 10

1 2 ─ 5 0 ─ ─ ─

1 2 3 ─ ─ 0 ─ ─

─ 6 3 4 ─ ─ 1 ─

1 ─ 3 4 ─ ─ ─ 1

1 ─ 7 5 ─ ─ ─ 0

8 6 3 ─ ─ 1 ─ ─

─ 9 7 5 ─ ─ 0 ─

8 6 ─ 10 1 ─ ─ ─

1 9 7 ─ ─ 0 ─ ─

8 ─ 3 10 ─ ─ ─ 1

(Primitive flow-table)
The method of finding the equivalent states is to compare the stable states in
each column. In the first column (X1 X2 = 00) there are two stable states
( 1 and 8 ), however, they cannot be equal since their outputs are
different. Therefore (1 ≠ 8).
The second column (X1 X2 = 01) contains three stable states (2, 6, and 9). States
2 and 9 have the same output value, therefore it is possible that (2 = 9) if (3 = 7).

The third column (X1 X2 = 11) contains two stable states (3 and 7), but their
output values are different and therefore (3 ≠ 7). Hence, (2 ≠ 9).

The fourth column (X1 X2 = 10) contains three stable states (4, 5, and 10). States
4 and 10 have the same output value, therefore it is possible that (4 = 10) if (1 =
8). But from the first column, we have that (1 ≠ 8), consequently (4 ≠ 10).

Hence, there are no equivalent states and no redundant states to be removed.

Therefore, this primitive table has a minimum number of rows.

The same result can be obtained by using the implication chart method as shown
below.
 2 X

3 X X

4 X X X

5 X X X X

6 X X X X X

7 X X X X X X

8 X X X X X X X

9 X 3, 7 X X X X X X

10 X X X 1, 8 X X X X X

1 2 3 4 5 6 7 8 9

The first phase of reduction shows that there are no redundant states to be
eliminated from the primitive flow-table. Therefore, the number of states will
still be 10.

Now we go to the second phase of reduction in which we try to merge rows if

possible in a single row.
It is obvious that in each row of the primitive table there is a single stable state as
well as an unspecified condition denoted as ( ─ ). It is required to benefit from
these ( ─ ) conditions to merge rows (i.e., more than one stable state in a single
row).

Two rows can be merged if they have no conflicting next-state entries. This
means that their next-state entries for any given valuation of inputs are either the
same or one of them is unspecified.

If the Moore model is used, then the two rows (states) must produce the same
outputs to be possible for merging. If the Mealy model is used, then it is possible
to merge rows (states) with different output values.

Let us go to the primitive flow-table and see if it is possible to merge the first
and the second rows in a single row.

Next States Output (Z)

Inputs X1 X2 Inputs X1 X2
00 01 11 10 00 01 11 10

1 2 ─ 5 0 ─ ─ ─

1 2 3 ─ ─ 0 ─ ─

It is clear that it is possible to merge the two rows because there are no
conflicting next-state entries. The merged row will be as shown below.
 Next States Output (Z)
Inputs X1 X2 Inputs X1 X2
00 01 11 10 00 01 11 10

1 2 3 5 0 0 ─ ─

After merging the number of rows is reduced causing to simplify the final circuit
to be designed.

Similarly, we continue testing the possible merging of each row with the rows
below it.

Rows for possible mergers:

m = (1, 2) (1, 5) (2, 4) (3, 4) (3, 6) (5, 7) (5, 9) (6, 8) (6, 10) (7, 9) (8, 10)

Now, we plot the merger diagram to see if it is possible to merge more than two
rows in a single row for more circuit simplification.

The merger diagram is constructed by distributing the ten states in such a way
that it is possible to draw a link between each state and the other nine states.

Then we draw a link (straight line) between every two states of possible mergers,
as shown below.
 1

10 2

9 3

8 4

7 5

6
1

(Merger Diagram)
After completing the construction of the merger diagram, we obtain geometric
forms. For example, the base of a pyramid can be constructed when four states
with each one of them has a link with the other three states. If that occurred, then
these four states can be merged in a single row.
If three states form the heads of a triangle, that means these three states can be
merged in a single row.
If there is only a single link between two states, that means it is possible to
merge these two states into a single row.
From the merger diagram, there are two triangles, one is shown in brown color
and the other in green color.
It is apparent that the best row merge is:
M = (1, 2) (3, 4) (5, 7, 9) (6, 8, 10)
Of course, any state cannot be merged in more than a single row. For example,
state 5 is merged with 7 and 9 in a single row, so it is not possible to merge it
with 1 though there is a link between 1 and 5.

The final merged flow-table will be,

Next States Output (Z)

Inputs X1 X2 Inputs X1 X2
00 01 11 10 00 01 11 10

1 2 3 5 0 0 ─ ─

1 6 3 4 ─ ─ 1 1

1 9 7 5 ─ 0 0 0

8 6 3 10 1 1 ─ 1

(Merged flow-table)

It is clear that the primitive flow-table (of ten rows) has been reduced to the
merged flow-table (of four rows). That is considered as a big simplification.
Homework:
Consider the following primitive flow-table of an asynchronous state machine.
a. Are there any redundant states to be removed?
b. Give the merged flow-table?

Inputs X1 X2 Output (Z)

00 01 11 10

1 2 ─ 3 0

1 2 4 ─ 0

1 ─ 5 3 0

─ 6 4 3 1

─ 6 5 3 0

1 6 5 ─ 0

Primitive Flow-Table
 Digital Systems Design (DSD)

4th Year Electrical Engineering Dept.

Lecture 9 (12/5/2020)

Design of Asynchronous State Machines

Step 4: State Assignments

In step 3, the merged flow-table was constructed. In this step, a binary code is to
be assigned for every state in the flow-table. Let us consider the merged flow-
table below (from the previous lecture).

Next States Output (Z)

Inputs X1 X2 Inputs X1 X2
00 01 11 10 00 01 11 10

1 2 3 5 0 0 ─ ─

1 6 3 4 ─ ─ 1 1

1 9 7 5 ─ 0 0 0

8 6 3 10 1 1 ─ 1

(Merged flow-table)

Each row is to be given a symbol. The first row is denoted as (a). The second,
third, and fourth rows are denoted as (b), (c), and (d), respectively, as shown
below.
 Next States Output (Z)
Inputs X1 X2 Inputs X1 X2
00 01 11 10 00 01 11 10

a 1 2 3 5 0 0 ─ ─

b 1 6 3 4 ─ ─ 1 1

c 1 9 7 5 ─ 0 0 0

d 8 6 3 10 1 1 ─ 1

Now, we have to assign the adjacency sets as below:

In column (X1 X2 = 00), the rows (a, b, and c) have the same next states, so these
rows should be given adjacent assignments.
In column (X1 X2 = 01), the rows (b, and d) have the same next states, so these
rows should be given adjacent assignments.
In column (X1 X2 = 11), the rows (a, b, and d) have the same next states, so
these rows should be given adjacent assignments.
In column (X1 X2 = 10), the rows (a and c) have the same next states, so these
rows should be given adjacent assignments.

Therefore,
Adjacency sets : (a, b, c) ; (b, d) ; (a, b, d) ; (a, c)
are to be satisfied in the row transition map.
Here, we have four symbols (a, b, c, and d) to be given binary codes. Hence,
two bits (y1 and y2) are enough to be used.
 y1

y2
(Row transition map)

The row transition map has four cells, and the four symbols are to be distributed
in these four cells such that all the adjacency sets are satisfied.
Adjacency sets : (a, b, c) ; (b, d) ; (a, b, d) ; (a, c)

y1

a b
c d y2
(Row transition map)
The first adjacency set (a, b, c) is satisfied since these row symbols are
distributed in three adjacent cells. Also, the other adjacency sets are satisfied in
the above distribution. Therefore, the above row transition map satisfies all the
adjacency sets. All that is done to ensure that the race problem will not occur.
Now the binary code of each row symbol is deduced from the row transition map
as follows:
Row symbol y1 y2
a 00
b 10
c 01
d 11
To obtain the binary assigned flow-table, we have to rewrite the merged flow-
table with binary codes instead of symbols.

Next States Output (Z)

Inputs X1 X2 Inputs X1 X2
00 01 11 10 00 01 11 10

y1y2 Y1Y2 Y1Y2 Y1Y2 Y1Y2

a 00 1 2 3 5 0 0 ─ ─

b 10 1 6 3 4 ─ ─ 1 1

c 01 1 9 7 5 ─ 0 0 0

d 11 8 6 3 10 1 1 ─ 1

Each row has a binary code as shown above. The symbols of stable states in each
row will be replaced by the binary code of that row. While the symbols of
unstable states will be replaced by the binary code of the row at which it is
stable.
For example, in the first row states (1 and 2) are stable, hence they will be
replaced by (00) the code of that row. While state (3) is unstable and it will be
replaced by (10) the code of the row at which it is stable. Similarly, state 5 will
be replaced by (01).
The same procedure is followed for the other rows. The final assigned flow-table
will be:
 Next States Output (Z)
Inputs X1 X2 Inputs X1 X2
00 01 11 10 00 01 11 10

y1y2 Y1Y2 Y1Y2 Y1Y2 Y1Y2

a 00 00 00 10 01 0 0 ─ ─

b 10 00 11 10 10 ─ ─ 1 1

c 01 00 01 01 01 ─ 0 0 0

d 11 11 11 10 11 1 1 ─ 1

(Assigned flow-table)

The next states of (y1 and y2) are denoted as (Y1 and Y2), respectively.
We must test the assigned flow-table to be free from race problems. That is done
by checking the rows of the table. In each row, the codes of the next states
should not be more than a single bit change than the row's code.
The code of the first row is (00), then the code (11) should not exist in the first
row. Therefore there is not a race problem in the first row.
Similarly, the code (01) does not exist in the second row. The code (10) does not
exist in the third row. The code (00) does not exist in the fourth row. Hence, the
assigned flow-table is free from race problems.
 Step 5: Circuit Realization

There are two methods to realize asynchronous state machines. Either by using
delaying circuits or by using SR flip flops. We shall use the first method because
it is easier to derive the next states and the output equations that are required to
realize the circuit.
From the assigned flow-table (of step 4), we have to derive two equations of Y1
and Y2.
The K-map of Y1 is:

X1
X1 X2
y1 y2 00 01 11 10
00 0 0 1 0
01 0 0 0 0
y2
11 1 1 1 1
y1
10 0 1 1 1

X2
Y1 = y1 y2 + y1 X1 + y1 X2 + X1 X2 ̅̅̅
y2

In this K-map, there is no static 1-hazard problem.

The K-map of Y2 is:

X1
X1 X2
y1 y2 00 01 11 10
00 0 0 0 1
01 0 1 1 1
y2
11 1 1 0 1
y1
10 0 1 0 0

X2
In this K-map, there are four cases of the static 1-hazard problem. To avoid this
problem, we have to add the four dotted groups shown below.

X1
X1 X2
y1 y2 00 01 11 10
00 0 0 0 1
01 0 1 1 1
y2
11 1 1 0 1
y1
10 0 1 0 0

X2
Y2 = X2 ̅̅̅
X1 y1 + ̅̅̅ y1 y2 + X1 ̅̅̅
X2 y1 y2 + X2 ̅̅̅̅ y1 + X1 ̅̅̅
X2 ̅̅̅̅ X2 y2 + X1 ̅̅̅̅
y1 y2 +
X2 ̅̅̅
X1 y2 + ̅̅̅
X1 y1 y2
The K-map of the output (Z) equation is:

X1
X1 X2
y1 y2 00 01 11 10
00 0 0 X X
01 X 0 0 0
y2
11 1 1 X 1
y1
10 X X 1 1

X2

Z = y1
The circuit diagram is shown below.

y2 Y2
Delay Circuit

y1 Y1
Delay Circuit

Z
Homework:
Design the asynchronous state machine whose primitive flow-table is shown
below.

Next States Output (Z)

Inputs X1 X2 Inputs X1 X2
00 01 11 10 00 01 11 10

1 7 ─ 2 0 ─ ─ ─

1 ─ 9 2 ─ ─ ─ 1

4 3 6 ─ ─ 0 ─ ─

4 3 ─ 5 0 ─ ─ ─

4 ─ 6 5 ─ ─ ─ 0

─ 3 6 5 ─ ─ 0 ─

1 7 8 ─ ─ 0 ─ ─

─ 7 8 2 ─ ─ 1 ─

─ 3 9 10 ─ ─ 1 ─

4 ─ 9 10 ─ ─ ─ 1

(Primitive flow-table)
 Digital Systems Design (DSD)

4th Year Electrical Engineering Dept.

Lecture 10 (19/5/2020)

Analysis of Asynchronous State Machines

Let us analyze the asynchronous state machine that has two inputs (X 1 and X2)
and two outputs (Z1 and Z2). Its next states and outputs equations are:
Y1 = X1 y1 + X2 y1 + X1 X2
Y2 = X1 ̅̅̅
X2 + X1 y2 + ̅̅̅
X2 𝑦2
Z1 = y1 y2 + ̅̅̅
X1 ( y1 + y2 )
y2 + ̅̅̅
Z2 = y1 ̅̅̅ X2 ( y1 + ̅̅̅
y2 )

Firstly, it is required to draw the K-map of Y1 and Y2.

X1
X1 X2
y1 y2 00 01 11 10
00 0 0 1 0
01 0 0 1 0
y2
11 0 1 1 1
y1
10 0 1 1 1

X2
Y1 = X1 y1 + X2 y1 + X1 X2
 X1
X1 X2
y1 y2 00 01 11 10
00 0 0 0 1
01 1 0 1 1
y2
11 1 0 1 1
y1
10 0 0 0 1

X2
Y2 = X1 ̅̅̅
X2 + X1 y2 + ̅̅̅
X2 𝑦2

The binary assigned flow-table (by collecting the values of Y1 and Y2) is:

Next States Outputs (Z1 Z2)

Inputs X1 X2 Inputs X1 X2
00 01 11 10 00 01 11 10

y1y2 Y1Y2 Y1Y2 Y1Y2 Y1Y2

a 00 00 00 10 01

b 01 01 00 11 01

c 11 01 10 11 11

d 10 00 10 10 11

(Assigned flow-table)

Note that, the state is stable if y1 y2 = Y1 Y2, otherwise it is unstable.

The stable states are encircled.

Next States Outputs (Z1 Z2)

Inputs X1 X2 Inputs X1 X2
00 01 11 10 00 01 11 10

y1y2 Y1Y2 Y1Y2 Y1Y2 Y1Y2

a 00 00 00 10 01

b 01 01 00 11 01

c 11 01 10 11 11

d 10 00 10 10 11

(Assigned flow-table)
There are 8 stable states. Each stable state should be given a symbol instead of a
binary code.

Next States Outputs (Z1 Z2)

Inputs X1 X2 Inputs X1 X2
00 01 11 10 00 01 11 10

y1y2 Y1Y2 Y1Y2 Y1Y2 Y1Y2

a 00 00 00 10 01

b 01 01 00 11 01

c 11 01 10 11 11

d 10 00 10 10 11
The first stable state 00 is in the column (X1 X2 = 00), it should be given the
symbol 1 . Also, in this column and at the last row, there is an unstable state
with code 00, it should be given the symbol 1 (not encircled).
Thus, the above table becomes:

Next States Outputs (Z1 Z2)

Inputs X1 X2 Inputs X1 X2
00 01 11 10 00 01 11 10

y1y2 Y1Y2 Y1Y2 Y1Y2 Y1Y2

a 00 1 00 10 01

b 01 01 00 11 01

c 11 01 10 11 11

d 10 1 10 10 11

The second stable state 00 is in the column (X1 X2 = 01), it should be given
the symbol 2 . Also, in this column and at the second row, there is an unstable
state with code 00, it should be given the symbol 2 (not encircled).

Thus, the above table becomes:

 Next States Outputs (Z1 Z2)
Inputs X1 X2 Inputs X1 X2
00 01 11 10 00 01 11 10

y1y2 Y1Y2 Y1Y2 Y1Y2 Y1Y2

a 00 1 2 10 01

b 01 01 2 11 01

c 11 01 10 11 11

d 10 1 10 10 11

The third stable state 01 is in the column (X1 X2 = 00), it should be given the
symbol 3 . Also, in this column and at the third row, there is an unstable state
with code 01, it should be given the symbol 3 (not encircled).
Thus, the above table becomes:

Next States Outputs (Z1 Z2)

Inputs X1 X2 Inputs X1 X2
00 01 11 10 00 01 11 10

y1y2 Y1Y2 Y1Y2 Y1Y2 Y1Y2

a 00 1 2 10 01

b 01 3 2 11 01

c 11 3 10 11 11

d 10 1 10 10 11
Similarly, the fourth stable state is 01 in the last column, it should be given the
symbol 4 . The above table becomes:

Next States Outputs (Z1 Z2)

Inputs X1 X2 Inputs X1 X2
00 01 11 10 00 01 11 10

y1y2 Y1Y2 Y1Y2 Y1Y2 Y1Y2

a 00 1 2 10 4

b 01 3 2 11 4

c 11 3 10 11 11

d 10 1 10 10 11

Similarly, the fifth stable state is 11 in the third column, it should be given the
symbol 5 . The above table becomes:

Next States Outputs (Z1 Z2)

Inputs X1 X2 Inputs X1 X2
00 01 11 10 00 01 11 10

y1y2 Y1Y2 Y1Y2 Y1Y2 Y1Y2

a 00 1 2 10 4

b 01 3 2 5 4

c 11 3 10 5 11

d 10 1 10 10 11
Similarly, the sixth stable state is 11 in the fourth column, it should be given
the symbol 6 . The above table becomes:

Next States Outputs (Z1 Z2)

Inputs X1 X2 Inputs X1 X2
00 01 11 10 00 01 11 10

y1y2 Y1Y2 Y1Y2 Y1Y2 Y1Y2

a 00 1 2 10 4

b 01 3 2 5 4

c 11 3 10 5 6

d 10 1 10 10 6

Similarly, the seventh stable state is 10 in the second column, it should be

given the symbol 7 . The above table becomes:

Next States Outputs (Z1 Z2)

Inputs X1 X2 Inputs X1 X2
00 01 11 10 00 01 11 10

y1y2 Y1Y2 Y1Y2 Y1Y2 Y1Y2

a 00 1 2 10 4

b 01 3 2 5 4

c 11 3 7 5 6

d 10 1 7 10 6
Similarly, the last stable state is 10 in the third column, it should be given the
symbol 8 . The above table becomes:

Next States Outputs (Z1 Z2)

Inputs X1 X2 Inputs X1 X2
00 01 11 10 00 01 11 10

y1y2 Y1Y2 Y1Y2 Y1Y2 Y1Y2

a 00 1 2 8 4

b 01 3 2 5 4

c 11 3 7 5 6

d 10 1 7 8 6

The merged flow-table can be deduced as:

Next States Outputs (Z1 Z2)

Inputs X1 X2 Inputs X1 X2
00 01 11 10 00 01 11 10

1 2 8 4

3 2 5 4

3 7 5 6

1 7 8 6

Merged flow-table
Now, it is required to fill the values of the outputs (Z1 and Z2) in the merged
flow-table. To do that, the K-maps of the two outputs equations must be drawn
as below.

X1
X1 X2
y1 y2 00 01 11 10
00 0 0 0 0
01 1 1 0 0
y2
11 1 1 1 1
y1
10 1 1 0 0

X2
Z1 = y1 y2 + ̅̅̅
X1 ( y1 + y2 ) = y1 y2 + ̅̅̅
X1 y1 + ̅̅̅
X 1 y2

X1
X1 X2
y1 y2 00 01 11 10
00 1 0 0 1
01 0 0 0 0
y2
11 1 0 0 1
y1
10 1 1 1 1

X2
y2 + ̅̅̅
Z2 = y1 ̅̅̅ X2 ( y1 + ̅̅̅ y2 + ̅̅̅
y2 ) = y1 ̅̅̅ X2 y1 + ̅̅̅
X2 ̅̅̅
y2
The values of Z1 and Z2 are to be collected in a single K-map as follows:

X1
X1 X2
y1 y2 00 01 11 10
00 01 00 00 01
01 10 10 00 00
y2
11 11 10 10 11
y1
10 11 11 01 01

X2
Z1 Z2

Only the values of (Z1 Z2) for stable states are filled in the merged flow-table.
The final merged flow-table becomes:

Next States Outputs (Z1 Z2)

Inputs X1 X2 Inputs X1 X2
00 01 11 10 00 01 11 10

1 2 8 4 01 00 ─ ─

3 2 5 4 10 ─ ─ 00

3 7 5 6 ─ ─ 10 11

1 7 8 6 ─ 11 01 ─

Merged flow-table
To obtain the primitive flow-table, each row of the merged flow-table is divided
into two rows with a single stable state.
Consider the first row of the merged flow- table:

Next States Outputs (Z1 Z2)

Inputs X1 X2 Inputs X1 X2
00 01 11 10 00 01 11 10

1 2 8 4 01 00 ─ ─

In this row, there are two stable states. It is required to divide this row into two
rows each of them contains a single stable state. The first row contains state 1
as follows:

Next States Outputs (Z1 Z2)

Inputs X1 X2 Inputs X1 X2
00 01 11 10 00 01 11 10

1 2 ─ 4 01 ─ ─ ─

The second row contains state 2 as follows:

Next States Outputs (Z1 Z2)

Inputs X1 X2 Inputs X1 X2
00 01 11 10 00 01 11 10

1 2 ─ 4 01 ─ ─ ─

1 2 8 ─ ─ 00 ─ ─
By following the same procedure, the final primitive flow-table is constructed as
below:

Next States Outputs (Z1 Z2)

Inputs X1 X2 Inputs X1 X2
00 01 11 10 00 01 11 10

1 2 ─ 4 01 ─ ─ ─

1 2 8 ─ ─ 00 ─ ─

3 2 ─ 4 10 ─ ─ ─

3 ─ 5 4 ─ ─ ─ 00

─ 7 5 6 ─ ─ 10 ─

3 ─ 5 6 ─ ─ ─ 11

1 7 8 ─ ─ 11 ─ ─

─ 7 8 6 ─ ─ 01 ─

(Primitive flow-table)

Homework:
Draw the state diagram of the above primitive flow-table.
 Digital Systems Design (DSD)

4th Year Electrical Engineering Dept.

Lecture 11 (2/6/2020)

Semiconductor Memory Circuits

The term memory is used to describe a system with the ability to store digital
information.
The term semiconductor memory refers to systems that are implemented using
integrated circuit technology. These types of systems store the digital information
using transistors, fuses, and/or capacitors on a single semiconductor substrate.
Semiconductor memory does not have any moving parts, so it is called solid-state
memory and can hold more information per unit area than disk memory.

Semiconductor memories are usually divided into two groups: read/write

memories and read-only memories (ROM).
Read-only memory (ROM) is a device that cannot be written to during normal
operation. This type of memory is useful for holding critical system information or
programs that should not be altered while the system is running.
Read/write memory refers to memory that can be read and written to during
normal operation and is used to hold temporary data and variables.
A ROM is a non-volatile memory with its binary pattern of 0s and 1s permanently
programmed by the manufacturer.
The read/write memory is a memory that can be easily programmed, erased, and
reprogrammed by the user.
The programming is called writing into memory.
Copying data from memory, without destroying the contents, is called reading
from memory.
The read/write memory is most often called a RAM (random-access memory).
Generally, the RAM’s program is volatile, which means it will be lost if the power
to the IC is turned off for even an instant.

Semiconductor Memories

Read/write memories (or RAMs) Read-only memories (ROMs)

(Volatile) (nonvolatile)
1. ROM (standard), or “Mask programmed
1. Static RAM (SRAM).
ROM”.
2. Dynamic RAM (DRAM).
2. Programmable ROM (PROM).
3. Erasable PROM (EPROM).
4. Electrically alterable ROM (EAROM),
or
Electrically erasable PROM (EEPROM).

Read-only memories come in four versions:

1. The standard ROM is programmed by the manufacturer. These ROMs have
their bit pattern built-in at the time of manufacturing. They are also called
"Mask-programmed ROMs”.
 2. The PROM (programmable read-only memory) can be programmed
permanently by the user using special equipment. It can be programmed
only once.
3. The EPROM (erasable programmable read-only memory) can be
programmed and erased by the user. Stored data in the EPROM can be
erased by shining high-intensity ultraviolet light through a special
transparent window in the top of the IC.
4. The EAROM (electrically alterable read-only memory). It is another
erasable PROM, it can be erased and programmed by the user with special
equipment. The EAROM is erased electrically rather than with ultraviolet
(UV) light. It is also called electrically erasable PROM (EEPROM).

The ROM, PROM, EPROM, and EEPROM are all considered permanent
nonvolatile memories and do not lose their data when power to the IC is turned
off.

RAMs are also subdivided into two groups:

1. The static RAM, it uses nearly standard flip flops as memory cells.
2. The dynamic RAM. Because the memory cell of the dynamic RAM is based
on capacitance, the cells must be refreshed (restored) hundreds of times per
second. The static RAM needs no refreshing and will hold its binary
information indefinitely as long as the IC is powered.
Note: (In microcomputers, RAMs are used for the temporary storage of user
programs and data. ROMs are most often used to store machine language
instructions that may be referred to as the monitor program. The monitor program
may contain unchangeable initialization routines, input/output routines, and
arithmetic algorithms).
In summary, memory is classified into two categories depending on whether it can
store information when power is removed or not. The term non-volatile is used to
describe memory that holds information when the power is removed, while the
term volatile is used to describe memory that loses its information when power is
removed. Historically, volatile memory can run at faster speeds compared to non-
volatile memory, so it is used as the primary storage mechanism while a digital
system is running. Non-volatile memory is necessary to hold critical operation
information for a digital system such as start-up instructions, operations systems,
and applications.

Memory Organization
The organization of a RAM or ROM can be thought of as being similar to a truth
table. Figure 1 shows one possible organization of memory locations. This table
represents the organization of a 8 x 4 bit RAM. The table shows that data in the
memory is organized into eight 4-bit groups referred to as words in this table. This
type of data organization is called a memory map model.
Address Bit D Bit C Bit B Bit A
Word 0
Word 1
Word 2
Word 3
Word 4
Word 5
Word 6 0 1 0 1
Word 7
Figure 1. (Organization of a 8 x 4 bit RAM)
The RAM in Figure 1 contains 8 words, each word consists of 4 bits. This memory
would have a capacity of 8 x 4 = 32 bits. The data stored in word 6 are (0101).

Common memory ICs come organized as 256 x 1, 1024 x 1, 4096 x 1, 256 x 4,

1024 x 4, or 1024 x 8.The 1024 x 8-bit memory would contain 1024 words each 8
bits long. This memory would then have a total capacity of 8192 bits.

Implementation of Standard ROMs:

A possible implementation of the ROM is shown in Figure 2. An address decoder

is used to access individual data words within the memory system. The address
decoder asserts only one-word line (WL) for each unique binary address that is
present on its input.
For an n-bit address, the decoder can access 2n or M words in memory. The word
lines run horizontally across the memory array; thus they are often called row
lines, and the word line decoder is often called the row decoder. Bit lines (BL) run
perpendicular to the word lines to provide individual bit storage access at the
intersection of the bit and word lines. These lines typically run vertically through
the memory array; thus they are often called column lines. The output of the
memory system (i.e., Data Out) is obtained by providing an address and then
reading the word from buffered versions of the bit lines.

Figure 2 shows a possible implementation of the ROM using diode connections

between address and bit lines.
The ROM is a matrix of intersections between a set of input and output data lines.
The presence or absence of a coupling element at each of the intersections of the
matrix determines the data content of the ROM. The most commonly used
coupling elements are diodes and bipolar and metal-oxide-semiconductor (MOS)
transistors.
The presence of a coupling element at an intersection means logic 1 is stored.
While the absence of a coupling element means logic 0 is stored.
Referring to Figure 2, the data stored in word 6 (w6) is (0 1 0 1).

w0
Decoder w1
A0 w2
Address w3
inputs A1 w4
A2 w5
w6
w7

O4 O3 O2 O1

Data-Out
Figure 2. ROM implementation using diodes.

ROM operation during a read:

Let us read the contents of the ROM (in Figure 2) at address w6. We need to put
the binary code “110” on the address input and then the decoder output w6
becomes logic 1 (or Vcc), other outputs of the decoder are logic 0 (or 0V). Then the
information on Data-Out will be (0101) which is exactly the data stored in w6.
Access time: is the time required to write one word into memory or to read one
word from memory.
There are three types of implementing standard ROMs:
1. Using diodes:
In the diode array memories (Figure 2), a diode is used at each intersection
in the matrix that corresponds to a binary 1, and leave the other intersections
unconnected that corresponds to a binary 0. Their access time is ranging
from 250 nsec to 1 µsec.
2. Using bipolar transistors:
In this type of implementation, a bipolar transistor is used as a coupling
element instead of a diode. ROMs employing bipolar technology may have
access times as low as 15 nsec.
3. Using MOS transistors:
In this type of implementation, a MOS transistor is used as a coupling
element instead of a diode. ROMs employing MOS technology may have
access times as low as 400 nsec.

Note:
For simplicity, the (X) symbol is often used in drawing the organization of the
memory instead of a coupling element. For example, Figure 2 can be drawn as in
Figure 3. Each Data-Out column represents an OR gate.
 w0
Decoder w1
A0 w2
Address w3
inputs A1 w4
A2 w5
w6 X X
w7

O4 O3 O2 O1

Data-Out
Figure 3. ROM of Figure 2.

Programmable Read-Only Memory (PROM)

The PROM is implemented in such a way that the manufacturer locates a
connecting device (diode, bipolar, or MOS transistor) at every intersection.
However, with each such device, there is provided a fusible link (a fuse). By
passing an adequately large current (typically 20-30 mA) through the fuse, it will
melt, or blow, and create an open circuit. A blown link represents a logic 0. Thus,
the user of such a PROM may burn out fuses as necessary, leaving transistors only
on locations required to establish the memory storage desired. A PROM can only
be programmed once in this manner, thus it is a read-only memory and non-
volatile.
PROMS tend to be very fast (25-50 ns), of relatively high power (bipolar: 0.5-1 w),
and small to medium in size (32 x 8 up to 8k x 8).
Erasable Programmable Read-Only Memory (EPROM)
As an improvement to the one-time programming characteristic of PROMs, an
electrically programmable ROM with the ability to be erased with ultraviolet (UV)
light was created. The erasable programmable read-only memory (EPROM) is
implemented using MOS transistors. The gate of such a transistor is entirely
insulated and isolated from electrical connection to any other part of the IC. So, it
is possible to establish a charge on these gates by the application of a high voltage
between source and drain. This process is accomplished using a dedicated
programmer; thus the EPROM must be removed from its system to program.
The EPROM can be erased by exposure to ultraviolet (UV) light, which serves to
discharge any charged gate. Exposure time is about 20 minutes, and it is
accomplished by placing the chip about 1 inch from a light source. EPROMs
contain a transparent quartz window on the top of their package that allows the UV
light to strike the devices. The EPROM must be removed from its system to
perform the erase procedure.
EPROMs are a significant improvement over PROMs because they can be
programmed multiple times; however, the programming and erase procedures are
manually intensive and require an external programmer and external eraser.
An EPROM is non-volatile and read-only since the programming procedure takes
place outside of its destination system.
EPROMs are available in NMOS and CMOS varieties and are rather slow (200
ns), of low power, and large in size (8k x 8 to 128k x 8). Recent CMOS EPROMS
are approaching bipolar speeds (35 ns).
Electrically Erasable Programmable Read-Only Memory (EEPROM)
To address the inconvenient programming and erasing procedures associated with
EPROMs, the electrically erasable programmable ROM (EEPROM) was created.
In this type of circuit, the floating-gate transistor is erased by applying a large
electric field. The advantage of this approach is that the circuitry to provide the
large electric field can be generated using circuitry on the same substrate as the
memory array, thus eliminating the need for an external UV light eraser. Since the
circuitry exists to generate large on-chip voltages, the device can also be
programmed without the need for an external programmer. This allows an
EEPROM to be programmed and erased while it resides in its target environment.
Early EEPROMs were very slow and had a limited number of program/erase
cycles; thus they were classified into the category of non-volatile, read-only
memory. Modern floating-gate transistors are now capable of access times on scale
with other volatile memory systems; thus they have evolved into one of the few
non-volatile, read/write memory technologies used in computer systems today.
Examination:
Answer the following three questions. Your answers should be sent to me today
before 8 pm.

Q1:
An 8-bit wide memory has eight address lines. What is its capacity in bits?
A) 64 B) 256 C) 1024 D) 2048

Q2:
Which of the following is suitable for implementation in a read-only memory?
A) Variables that a computer program needs to continuously update
B) Information captured by a digital camera
C) A computer program on a spacecraft
D) Incoming digitized sound from a microphone

Q3:
Which of the following is suitable for implementation in a read/write memory?
A) A look up table containing the values of sine.
B) Information captured by a digital camera.
C) The boot up code for a computer.
D) A computer program on a spacecraft.
 Digital Systems Design (DSD)

4th Year Electrical Engineering Dept.

Lecture 12 (9/6/2020)

Semiconductor Memory Circuits

Comparison between Dynamic RAM and Static RAM

Dynamic RAM (DRAM) Static RAM (SRAM)

1. Low speed. 1.High speed.

2. High capacity. 2. Low capacity.
3. Low cost. 3. High cost.
4. Complex control needed. 4. Simple control needed.
5. Used in computer and large systems. 5. Used in small systems.
6. Low power dissipation. 6. High power dissipation.
7. Bit stored as a charge. 7. Bit stored as a voltage.

Applications of ROMs:
It is quite common to find ROMs applied as:
 Code converters.
 Character generators for displays.
 Trigonometric function generators.
 Process controllers.
The ROM is a device that maintains a fixed relationship between its inputs and
outputs at all times during normal operation.

Example 1:
(The organization of a ROM that acts as a Binary-to-Gray code converter)
Let us assume that the number of bits of the input Binary code is 3. Firstly, we
should construct the truth-table (or look-up table) of the ROM.

Binary Code Gray Code

A2 A1 A0 O3 O2 O1
0 0 0 0 0 0 w0
0 0 1 0 0 1 w1
0 1 0 0 1 1 w2
0 1 1 0 1 0 w3
1 0 0 1 1 0 w4
1 0 1 1 1 1 w5
1 1 0 1 0 1 w6

1 1 1 1 0 0 w7

Now, we must draw the organization diagram of the ROM as shown below. Each
logic 1 in the Gray code column should be represented as a coupling element in the
diagram.
 w0
3x8 w1
X
A0 w2
Binary X X
Decoder w3
Code X
A1 w4
Inputs X X
A2 w5
X X X
w6
X X
w7
X

O3 O2 O1

Gray Code Outputs

(The organization of a ROM that acts as a Binary-to-Gray code converter)

Example 2:
(ROMs that implement Boolean functions)
Consider the following Boolean equations:
O7 (A2, A1, A0) = ∑ (0, 2, 3, 5)
O6 (A2, A1, A0) = ∑ (2, 5, 6)
O5 (A2, A1, A0) = ∑ (0, 3, 5, 7)
O4 (A2, A1, A0) = ∑ (0, 1, 3, 7)
O3 (A2, A1, A0) = ∑ (1, 4, 6)
O2 (A2, A1, A0) = ∑ (0, 1, 2)
O1 (A2, A1, A0) = ∑ (0, 3, 5, 6, 7)
O0 (A2, A1, A0) = ∑ (1, 2, 4, 7)
To design a ROM that implements the above eight Boolean functions, we have to
construct the ROM truth-table as below.

Inputs Outputs

A2 A1 A0 O7 O6 O5 O4 O3 O2 O1 O0

0 0 0 1 0 1 1 0 1 1 0

0 0 1 0 0 0 1 1 1 0 1

0 1 0 1 1 0 0 0 1 0 1

0 1 1 1 0 1 1 0 0 1 0

1 0 0 0 0 0 0 1 0 0 1

1 0 1 1 1 1 0 0 0 1 0

1 1 0 0 1 0 0 1 0 1 0

1 1 1 0 0 1 1 0 0 1 1

Finally, we have to draw the organization of the ROM according to the above
truth-table. Each logic 1 in the output columns should be represented as a coupling
element in the diagram.
 0 X X X X X
3x8 1 X X X X
A0
2 X X X X
Decoder
A1 3 X X X X
4 X X
A2
5 X X X X
6 X X X
7 X X X X

O7 O6 O5 O4 O3 O2 O1 O0
(Programming the ROM According to Truth-Table)

Examination:
Answer the following question. Your answer should be sent to me today before 8
pm.

Q: Show, how to use the ROM circuits to multiply two binary numbers each of
two bits.
 Digital Systems Design (DSD)

4th Year Electrical Engineering Dept.

Lecture 13 (16/6/2020)

Programmable Logic Devices (PLDs)

The term PLD is used as a generic description for any circuit that can be
programmed to implement digital logic. This lecture provides a basic
understanding of the principles of programmable logic devices.
Figure 1 shows the general structure of the PLDs. It consists of two arrays of AND
and OR logic gates. Each input is applied to a (buffer/inverter) gate to provide the
input value and its complement which are then applied to the AND array. The
outputs of the AND array are called the product-terms. The OR array receives the
product-terms and calculates the output values. They are used to implement
Boolean functions in the sum – of – product (SOP) forms.

n p
buffer/ product-term
inverters lines

n m
AND OR
input output
lines array array lines

Figure 1. The general structure of PLDs

 Types of PLDs

Device AND – array OR – array

PROM Fixed Programmable

PLA Programmable Programmable

PAL Programmable Fixed

FPGA Programmable ──

The PROM circuits were discussed in the previous lecture.

Programmable Logic Arrays (PLAs)

A programmed logic array (PLA) performs the same basic functions as a ROM but
does not generate all the minterms as a ROM does. The size of a PLA is defined by
the number of inputs (n), the number of product terms in the AND – array (p), and
the number of outputs (m), as (n x p x m). For example, if there is a (3 x 5 x 4)
PLA, that means it has 3 inputs, 5 product terms, and 4 outputs.
The programming of the PLA is similar to the programming of PROMs, discussed
previously. PLAs are either mask programmed (i.e., programmed by the
manufacturer) or field programmed (i.e., programmed by the user).
 Fuse
a b c a bc
a
b ≡ X X X ≡ X
c
(a) Unprogrammed AND – gate (all its input fuses intact)

a b c
a
b ≡ X X
c

(b) Programmed AND – gate realizing the term (a c)

Figure 2. PLD notations

Figure 2 shows some important notations. In Figure 2(a), it is clear that there is a
fuse on each input of the gate. For simplicity, the gate is drawn with a single
horizontal input line. Each input is represented by a vertical line perpendicular to
the horizontal input line. The fuses on the inputs are represented by (X) signs
located at the intersections. If all the input fuses exist, then it is possible to put a
single (X) sign inside the gate symbol.

Figure 2(b) shows the programming of the gate to realize the term (a c). In this
case, input b is not allowed to apply to the gate, hence the fuse at the input b is
blown. The (X) signs are located only on inputs a and c, in this case.
Example 1:
Implement the following two Boolean functions with a PLA circuit.
F1 = A B ̅ B C̅
̅+AC+ A and F2 = ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
(AC+BC)
Here, F1 is a true function. While F2 is a complement function. The complement
function is implemented as a true (i.e., F2 = AC + BC), then the output is
complemented.
Firstly, we have to construct the PLA programming table.

(PLA Programming Table)

Product Inputs Outputs

Term A B C (T) (C) T = True
F1 F2 C = Complement

̅
AB 1 1 0 ─ 1 ─

AC 2 1 ─ 1 1 1

BC 3 ─ 1 1 ─ 1

̅ B C̅
A 4 0 1 0 1 ─

It is noted that:
0⨁ A=A
̅
1⨁ A= A
Therefore, the true output (F1) after is calculated, it is EXORed with 0. While the
complement output (F2) is EXORed with 1 to obtain its complement.
A

B
OR array
C

XX 1 X ̅
AB

X X 2 X X AC

X X 3 X BC

XX X 4 X ̅ B C̅
A
C C̅ B B ̅
̅ A A
X 0
AND array X 1

F1 F1

AC + BC F2
Example 2:
Implement the following two Boolean functions with a PLA:
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
F1 = AB + AC + BC and ̅B
F2 = AB + AC + A ̅
̅C
Solution:

(PLA Programming Table)

Product Inputs Outputs

Term A B C (C) (T) T = True
F1 F2 C = Complement

AB 1 1 1 ─ 1 1

AC 2 1 ─ 1 1 1

BC 3 ─ 1 1 1 ─

̅B
A ̅
̅C 4 0 0 0 ─ 1
A

B
OR array
C

X X 1 X X AB

X X 2 X X AC

X X 3 X BC

XX X 4 X ̅ ̅B C
A ̅
C C̅ B B ̅
̅ A A
X 0
AND array X 1
F1

F2
Examination:
Answer the following question. Your answer should be sent to me today before 8
pm.

Q. Implement the following two Boolean functions with a PLA:

̅B
F1 = A ̅ C̅ + A B C
̅C+AB

̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅ C̅ + A
F2 = (A ̅B ̅+ B ̅ C̅ + A B C)
 Digital Systems Design (DSD)

4th Year Electrical Engineering Dept.

Lecture 14 (23/6/2020)

Programmable Logic Devices (PLDs)

Programmable Array Logic (PAL)

The PAL devices were developed to overcome the deficiencies of PALs.
The PAL is a programmable logic device with a fixed OR array and a
programmable AND array, Because only the AND gates are programmable, the
PAL is easier to program but is not as flexible as the PLA.
Figure 1 shows the logic configuration of a typical PAL. It has four inputs and
four outputs. Each input has a buffer-invertor gate and each output is generated
by a fixed OR gate. There are four sections in the unit, each being composed of a
three-wide AND-OR array. This is the term used to indicate that there are three
programmable AND gates in each section and one fixed OR gate.

Each AND gate has 10 programmable input connections. This is shown in the
diagram by 10 vertical lines intersecting each horizontal line.
One of the outputs is connected to a buffer-inverter gate and then fed back into
two inputs of the AND gates.

A typical PAL integrated circuit may have eight inputs, eight outputs, and eight
sections, each consisting of an eight-wide AND-OR array. The output terminals
are sometimes driven by three-state buffers or inverters.
 Product
term 1 2 3 4 5 6 7 8 9 10
1
F1
2

3
I1

4
F2
5

I2

7
F3
8

I3

10
F4
11

12

I4

Figure 1. PAL with four inputs, four outputs, and three-wide AND-OR structure
When designing with a PAL, the Boolean functions must be simplified to fit into
each section. Unlike the PLA, a product term cannot be shared among two or more
OR gates. Therefore, each function can be simplified by itself without regard to
common product terms. The number of product terms in each section is fixed, and
if the number of terms in the function is too large, it may be necessary to use two
sections to implement one Boolean function.

Example:
Using a PAL of the structure shown in Figure 1, implement the following
Boolean functions:
W(A, B, C, D) = ∑ (2, 12, 13)
X(A, B, C, D) = ∑ (7, 8, 9, 10, 11, 12, 13, 14, 15)
Y(A, B, C, D) = ∑ (0, 2, 3, 4, 5, 6, 7, 8, 10, 11, 15)
Z(A, B, C, D) = ∑ (1, 2, 8, 12, 13)
Solution:

C
CD
AB 00 01 11 10
00 0 0 0 1
01 0 0 0 0
B
11 1 1 0 0
A
10 0 0 0 0

W = A B C̅ + A
̅B̅CD
̅
 C
CD
AB 00 01 11 10
00 0 0 0 0
01 0 0 1 0
B
11 1 1 1 1
A
10 1 1 1 1

X=A+BCD

C
CD
AB 00 01 11 10
00 1 0 1 1
01 1 1 1 1
B
11 0 0 1 0
A
10 1 0 1 1

D
̅ B+CD+ B
Y=A ̅ D
̅
 C
CD
AB 00 01 11 10
00 0 1 0 1
01 0 0 0 0
B
11 1 1 0 0
A
10 1 0 0 0

Z = A B C̅ + A
̅B ̅ + A C̅ D
̅CD ̅B
̅+A ̅ C̅ D

The four Boolean functions after simplifications are:

W = A B C̅ + A
̅B̅CD
̅
X=A+BCD
̅ B+CD+ B
Y=A ̅ D
̅
Z = A B C̅ + A
̅B ̅ + A C̅ D
̅CD ̅B
̅+A ̅ C̅ D = W + A C̅ D ̅B
̅+A ̅ C̅ D

The fuse map for the PAL is shown in Figure 2.

 Product
term ̅ ̅
A A B B C C̅ D ̅
D W ̅
W
1 X X X
W
2 X X X X

3 X
A

4 X
X
5 X X X

6 X

Always = 0
B

7 X X
Y
8 X X

9 X X

10 X
Z
11 X X X

12 X X X X

Figure 2. Fuse (connection) map for PAL to implement the four functions
 Note:
PALs and PLAs are the two basic kinds of programmable logic. They are ICs
with many gates whose interconnections can be programmed (like ROMs) to
form the desired logic functions. They are available in both bipolar and CMOS
construction. The bipolar construction uses fusible-link (one-time-
programmable). The CMOS construction uses floating-gate MOS (UV or
electrically erasable).

Sequential Programmable Logic Device (SPLD)

SPLD includes flip flops within the integrated circuit chip in addition to the
AND-OR array. The result is a sequential circuit as shown in Figure 3.

Multiplexers

Bypass the flip flops

0

Outputs
Inputs AND – OR array Flip
Flops 1
(PAL or PLA)

Select input
(0 or 1)

Figure 3. SPLD
The circuit outputs can be taken from the OR gates or the outputs of the flip
flops.
Additional programmable connections are available to include the flip-flop
outputs in the product terms formed with the AND array.
The flip flops may be of the D or the JK type. These are called registered PALs
and PLAs, and they are ideal for implementing custom sequential circuits.
The configuration mostly used for SPLD is the combinational PAL together with
D flip flops.
The PALs are more favorite than PLAs because they are faster (the signal passes
through only one array of fuses) and cheaper and will usually do the job.
Each section of an SPLD is called a macrocell. A typical SPLD has from 8 to 10
macrocells within one IC package.

Complex Programmable Logic Device (CPLD):

PLD PLD PLD PLD

I/O I/O

Control Programmable switch matrix Control

block block

PLD PLD PLD PLD

Figure 4. General CPLD Configuration

The design of a digital system using PLD often requires the connection of
several devices to produce the complete specification. For this type of
application, it is more economical to use a complex programmable logic device
(CPLD). A CPLD is a collection of individual PLDs on a single integrated
circuit.
Figure 4 shows a general configuration of a CPLD. It consists of multiple PLDs
interconnected through a programmable switch matrix. The input/output (I/O)
blocks provide the connections to the IC pins. Each I/O pin can be programmed
to act as input or output. The switch matrix receives inputs from the I/O block
and directs it to the individual macrocells. Similarly, selected outputs from
macrocells are sent to the outputs as needed. Each PLD typically contains from 8
to 16 macrocells.
A CPLD is a VLSI (Very Large Scale Integration) integrated circuit. VLSI
design refers to the design of digital systems that contain thousands to millions
of gates within a single IC chip. More recently, VLSI approaches have been
developed for PLDs to handle designs that in the past were implemented by
many small chips. The new approaches yield high-capacity CPLDs. A
programmable interconnection structure allows the PLDs to be connected to each
other in the same way that can be done with individual PLDs.
CPLDs have adequate speed with maximum system clock rates typically in the
range of 50 – 400 MHz. CPLDs are typically faster than FPGAs.
Applications of CPLDs include coprocessors for high-speed designs, finite
impulse response (FIR) filters, fast Fourier transforms (FFT), and discrete cosine
transforms (DCT).
 Note:
The integrated circuits (ICs) are subdivided into the followings:
SSI = small – scale – integration.
MSI = medium – scale – integration.
LSI = large – scale – integration.
VLSI = very large – scale – integration.

SSI ─ a chip containing up to about 100 transistors.

MSI ─ a chip containing 100 – 1000 transistors.
LSI ─ a chip containing 1000 – 100 000 transistors.
VLSI ─ a chip containing more than 100 000 transistors.

Examination 4:
Answer the following question? Your answer should be sent to me today before
8 p.m.

Q.
Use a PAL with four inputs, four outputs, and three-wide AND-OR structure;
to implement the following Boolean functions, given in sum of minterms:
w(A, B, C) = 𝚺 (1, 2, 4, 6)
x(A, B, C) = 𝚺 (0, 1, 3, 6, 7)
y(A, B, C) = 𝚺 (1, 2, 4, 6, 7)
z(A, B, C) = 𝚺 (1, 2, 3, 5, 7)
Give the fuse map of the PAL.
 Digital Systems Design (DSD)

4th Year Electrical Engineering Dept.

Lecture 15 (30/6/2020)

Logic Families
Digital circuits are grouped into logic families. A logic family is a group of parts
that all adhere to a common set of specifications so that they work together.

Transistor-Transistor-Logic (TTL)
One of the first logic families that emerged after the invention of the integrated
circuit was transistor transistor logic (TTL). This logic family uses bipolar junction
transistor (BJT) as its fundamental switching item. This logic family defined a set
of discrete parts that contained all of the basic gates in addition to more complex
building blocks. TTL was used to build the first computer systems in the 1960s.

TTL circuits are generally called 54-series or 74-series circuits. The 54-series is
designed to meet military requirements by satisfying specified performance over a
temperature range of (-55 to 125 ℃). The 74-series is the commercial series with
an operating temperature range of (0 to 70 ℃).

The TTL family is based on multi-emitter construction of transistors made possible

by integrated circuit technology.
The basic TTL NAND gate is shown in Figure 1, as an example of TTL circuits.

Vcc = + 5 V

130
4K 1.6 K
T4
A
T2 D
B T1 Output

Multi emitter T3
Transistor Totem-pole
configuration
1K

Figure 1. A 54/74 series standard TTL NAND gate

The input stage of TTL circuits is the multi-emitter transistor. The output stage is
the totem-pole configuration. Notice the totem-pole output transistors (T3 and T4),
which are used for their low output impedance enough to prevent excessive
loading when other TTL gates are connected. T3 is called the pull-down transistor,
while T4 is called the pull-up transistor. When T3 is ON, T4 is OFF, and vise versa.

In TTL circuits:
High logic level = logic “1” = 5 V
Low logic level = logic “0” = 0 V
Current and Voltage Definitions
VIHmin = minimum input voltage that the logic element is guaranteed to interpret as
the high logic level
VILmax = maximum input voltage that the logic element is guaranteed to interpret as
the low logic level
VOHmin = minimum high logic – level voltage appearing at the output terminal of
the logic element
VOLmax = maximum low logic – level voltage appearing at the output terminal of
the logic element
IIHmax = maximum current flowing into an input when a specified high logic – level
voltage is applied
IILmax = maximum current flowing into an input when a specified low logic – level
voltage is applied
IOH = current flowing into the output when a specified high-level output voltage is
present
IOL = current flowing into an output when a specified low-level output voltage is
presented
IOS = current flowing into an output when the output is shorted

Current flowing out of a terminal has a negative value.

Fan – Out
Fan-out (also called "loading factor") is defined as the number of TTL loads that a
TTL device can drive reliably. The 74-series has a fan-out of 10; this means you
can connect the output of a TTL gate, as an input to 10 other TTL gates. If you
exceed this number of loads, the worst-case values on the datasheet are no longer
guaranteed.
The Fan-out of the gate is calculated from the ratio (IOH / IIH ) or (IOL / IIL),
whichever is smaller.
For example, the standard TTL gates have the following values for the currents:
IOH = - 400 µA, IIH = 40 µA, IOL = 16 mA, IIL = - 1.6 mA.
400 µA 16 mA
The two ratios give the same number in this case: = 10, and = 10
40 µA 1.6 mA

Therefore, the fan-out of standard TTL is 10.

Noise Immunity
Noise immunity is defined as the maximum induced noise voltage a TTL device
can withstand without a false change in output state.
Common sources of noise are variations of the dc supply voltage, ground noise,
magnetically coupled voltages from adjacent lines, and radiated signals.

LOW level noise margin: (VNL = VIL(max) – VOL(max) )

HIGH level noise margin: (VNH = VOH(min) – VIH(min) )

The noise margin is VNL or VNH , whichever is smaller.

For standard TTL : VNL = 0.4 V and VNH = 0.4 V.

Open – Collector TTL Gates
Instead of a totem-pole output, some TTL devices have an open-collector output.
This means they use only the lower transistor of a totem-pole pair. For instance,
Figure 2 shows a two-input NAND gate with an open-collector output. Because the
collector of T3 is open, a gate like this won’t work properly until you connect an
external pull-up resistor, shown in Figure 3.

Vcc = + 5 V

4K 1.6 K

A
T2
B T1 Output

T3

1K

Figure 2. Open – collector TTL gate

Vcc = + 5 V

R Pull – up
resistor

Output
T3

Figure 3. Pull – up resistor

T3 provides an active pull-down when it saturates. But when it cuts off, there's no
upper transistor to pull up the output voltage. Because of this, any stray
capacitance or other load capacitance across the output has to charge through the
pull-up resistor. Since the charging is through a passive component, switching
from low to high output is called "passive pull-up". For TTL devices, the pull-up
resistor has to be hundreds to thousands of ohms. For this reason, the passive pull-
up is much slower than the active pull-up. This is the main disadvantage of open-
collector devices as compared with totem-pole devices.
It is common in digital systems to drive a single input line with several different
gate outputs. With normal TTL gates, this arrangement is inappropriate and
generally destroys some of the connected gates. The open-collector gate can solve
this problem. An external pull-up resistor must be added between the several gate
outputs and the positive power supply. The connection of the outputs of open-
collector gates to a common pull-up resistor automatically produces ANDing
action, and therefore it is called wire-AND connection.
There are upper and lower limits on the value of the pull-up resistance R.
The general equation for Rmax is given by
Vcc − VIHmin
R max =
N1 IOH + N2 IIH
Where N1 is the number of open collector gates and N2 is the number of gate inputs
driven.
The general equation for Rmin is given by
Vcc − VILmax
R min =
IOL + N2 IIL
The value of R should be selected to be as
R min ≤ R ≤ R max
Three – State TTL Devices
They are also called “tri-state” devices.
Wire-AND won’t work with standard totem-pole devices, because excessive
current destroys internal transistors for certain output conditions. This is what led
to tri-state TTL, a new variety of totem-pole TTL devices introduced in the early
1970s. With tri-state TTL, it is possible to wire-AND totem-pole outputs and avoid
the loss of switching speed that occurs with open-collector outputs. Three-state
output gates are often used with microprocessor circuits. In three-state circuits, an
additional input, called the enable (or disable), is provided on the chip.

Vcc = + 5 V

130
4K 1.6 K
T4
Input
T2 D2
T1 Output

T3

1K D1

̅̅̅̅̅̅̅̅̅̅̅
𝐃𝐢𝐬𝐚𝐛𝐥𝐞
Figure 4. Three-state TTL inverter (NOT gate)
Figure 4 shows the modification made (in red) to make the standard TTL circuit as
a three-state TTL.
The three output states are:
1. T3 is ON and T4 is OFF, the output is LOW.
2. T3 is OFF and T4 is ON, the output is HIGH.
3. Both T3 and T4 cut off, the output is floating (disconnected), or high
impedance (Hi – Z).
 Digital Systems Design (DSD)

4th Year Electrical Engineering Dept.

Lecture 16 (7/7/2020)

Logic Families

Emitter-Coupled Logic (ECL)

This logic family is the fastest, and that is an advantage. The good switching
characteristics of this family result from the avoidance of saturation of any
transistors within the gate.
Complementary
Multiple inputs Differential amplifier Bias circuit outputs

VCC (Gnd)

290 300 300

T8
OR output
T7
NOR output
T6
T1 T2 T3 T4 T5
VBB ≅ - 1.29 V
1.5 K 1.5 K

2K
1.2 K 2.3 K

VEE (-5.2V)
A B C D

‫ﻣن ﺧﺻﺎﺋص ھذه‬

Inputs Figure 1. An ECL OR/NOR gate circuit ‫اﻟﻣﺟﻣوﻋﺔ اﻧﮭﺎ ﺗﺗﺟﻧب‬
‫ ﺣﺎﻟﺔ اﻟﺗﺷﺑﻊ‬sat
 ‫ﺗوﻓر ھذه اﻟﻧوﻋﯾﺔ ﻣﺧرﺟﯾن‬
‫ ﻣﻧﻔﺻﻠﺔ ﻟﺑواﺑﺗﻲ‬OR&NOR
‫وھذا اﻟﺷﻲء ﻏﯾر ﻣﺗوﻓر ﻓﻲ‬
‫اﻟﺑواﺑﺎت اﻟﻣﻧطﻘﯾﺔ اﻻﺧرى‬

A+B+C+D
A
B
C
D
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
𝐀+𝐁+𝐂+𝐃

Figure 2. Logic symbol of the circuit in Figure 1

Figure 1 shows an ECL gate with two separate outputs, the OR output, and the
NOR output. Each ECL gate has two separate complementary outputs and that is
an advantage not to exist in other logic families.
The VCC supply voltage is taken as 0V and VEE as – 5.2V. Therefore the inputs
should be of negative values. That is a disadvantage.
Low level (logic 0) = - 1.75 V
High level (logic 1) = - 0.9 V

Because of the low output impedance of the emitter follower and the high input
impedance of the differential amplifier input, high fan-out (= 70) operation is
possible.

The ECL family has a disadvantage of requiring more input power than the TTL
family. In TTL, power dissipation per gate is 10mW. While it is 60mW in ECL.
Furthermore, the great variety of logic circuits that can be realized with TTL
cannot be duplicated with ECL.
Typical ECL circuits have noise margins from about 0.2V to 0.25V. This is less
than that for TTL and makes ECL unreliable in high noise environments.
Wired logic is possible with ECL gates. ‫ﻣن اﻟﻣﺿﺎر االﺧرى ﻟﮭذه اﻟﻌﺎﺋﻠﺔ اﻧﮭﺎ ﺗﺣﺗﺎج اﻛﺛر ﻣن ﻣدﺧل طﺎﻗﺔ وﻛﻣﯾﺔ‬
‫ اﺳﺗﮭﻼﻛﮭﺎ ﻟﻠﻘدرة اﻛﺑر ﻣن ﻋﺎﺋﻠﺔ (ت ت ل‬TTL(
‫وان اﻟﻛﺛﯾر ﻣن اﻟدواﺋر اﻟﻣﻧطﻘﯾﺔ ال ﯾﻣﻛن ﺗﻣﺛﯾﻠﮭﺎ ﺑﺎﺳﺗﺧدام ھذه اﻟﻌﺎﺋﻠﺔ ﺑﯾﻧﻣﺎ ﯾﻣﻛن‬
‫ ﺑﺣﯾث‬0.25-0.2 ‫ ﻛذﻟك ﻟﮭذه اﻟﻌﺎﺋﻠﺔ ﺿوﺿﺎء ﻣن‬، ‫ﺗﻣﺛﯾﻠﮭﺎ ﺑﺎالﻧواع االﺧرى‬
‫ﺗﻛون اﻗل ﻣن االﺧرﯾﺎت وھذا ﻣﺎﯾﺟﻌﻠﮭﺎ ﻏﯾر ﻣوﺛوﻗﺔ ﻓﻲ ﺑﯾﺋﺎت ﻋﺎﻟﯾﺔ اﻟﺿوﺿﺎء‬