0% found this document useful (0 votes)
184 views22 pages

Capacitance of The P-N Junction

Two types of capacitance are associated with PN junctions: junction capacitance (Cj) and storage capacitance (Cs). Cj is due to the changing depletion width under applied bias. It behaves similarly to a parallel plate capacitor where the depletion width represents the plate separation. Cs is due to stored charges in the junction region. It does not behave like a parallel plate capacitor. When the voltage across the PN junction changes, the stored charges Qj and Qs are affected, resulting in the capacitances Cj and Cs. Cj depends inversely on the square root of the applied voltage relative to the built-in potential. Physically, a finite time is required for charges

Uploaded by

Leng Ryan
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
0% found this document useful (0 votes)
184 views22 pages

Capacitance of The P-N Junction

Two types of capacitance are associated with PN junctions: junction capacitance (Cj) and storage capacitance (Cs). Cj is due to the changing depletion width under applied bias. It behaves similarly to a parallel plate capacitor where the depletion width represents the plate separation. Cs is due to stored charges in the junction region. It does not behave like a parallel plate capacitor. When the voltage across the PN junction changes, the stored charges Qj and Qs are affected, resulting in the capacitances Cj and Cs. Cj depends inversely on the square root of the applied voltage relative to the built-in potential. Physically, a finite time is required for charges

Uploaded by

Leng Ryan
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 22

Capacitance of the P-N Junction

Pg.1
Capacitance of the P-N Junction
Two kinds of capacitances are associated with pn junctions. These are junction
capacitance (or transition capacitance) and charge storage capacitance (or
diffusion capacitance). These are modeled by two capacitors, Cj and Cs
respectively, connected parallel to the p-n junction.

Cj

Cs
Ideal p-n junction Practical p-n junction

Pg.2
Junction capacitance has physical characteristics similar to that of a parallel-
plate capacitor and the expression that defines this capacitance is identical to
that of a parallel-plate capacitor.
The storage capacitance also possesses the charge storing property of a
capacitor but has no characteristics similar to those of a parallel-plate
capacitor.
Capacitance is present in any device if a small change in the applied voltage
dV across it results in a change in some charge dQ stored in it. By definition,
the capacitance C is given by
dQ
C  (68)
dV

In the special case of a parallel plate capacitor, since Q is proportional to V,


Q  V  Q  kV
Q
C  dQ Q
V C k
dV V
Pg.3
As the voltage V across a p-n junction varies, there are two stored charges in it,
Qj and Qs, that will be affected. Hence, there are two associated capacitances.
dQ j dQs
Cj  , Cs 
dV dV
From circuit point of view, the voltage across the p-n junction cannot change
instantaneously due to the presence of Cj and Cs. This implies that there will be
delay in circuits involving p-n junctions as the capacitors Cj and Cs will need
time to be charged up or discharged.

Physically, this delay is related to the fact that a finite time is required for
current to flow and charges to be transported to or away from the p-n junction,
so that the stored charge Qj and Qs can be built-up or reduced to their new
value upon changing V.

Let’s look at the source of Qj and Qs that give rise to Cj and Cs.

Pg.4
a) Junction Capacitance Cj
Upon changing the bias V across a p-n junction, the depletion width W and
hence the amount of space charge in the depletion region will be affected.

The space charge Qj in the depletion region W is given by


Qj  |Q |  qAx p Na  qAxn Nd (69)

Under FB, W decreases and hence Qj decreases. Under RB, W increases and
hence Qj increases. Thus, there is a capacitive effect associated with this
change of charge Qj. Unlike the parallel plate capacitor, Qj is not proportional
to V, viz., non-linear, and hence the above eqn. must be used to determine Cj.

Pg.5
Qj

= Cj
Note:
VD here is the
applied voltage
called the diode
voltage

VD

Pg.6
With applied bias V ( +ve when FB and –ve when RB )
1
 2 ( V V    2
) Na  Nd
W   o   
 (70)
q  Na Nd 
   
 

Now, recall the expressions for xn and xp


WN a WN d  xn N d  x p N a 
xn  and xp   
Na  Nd Na  Nd  xn  x p  W 

Thus, the space charge Qj can now be written as


Na Nd
Qj  qA W
Na  Nd
1
 Na Nd  2
 A  2 q (V V )  (71)
 
Na  Nd
o
 

Pg.7
The junction capacitance Cj is thus given by
1
dQ j dQ j A  2 q Na Nd  2
Cj     (72)
dV d (Vo V ) 2  (Vo V ) Na  Nd 

Note that Cj is voltage dependent (Cj  ( Vo - V )-1/2).


1
 2 ( V V    2
) Na  Nd
Rearranging, W   o   

q  Na Nd 
   
 
1
 q Na Nd  2  A
Cj   A   (73)


2 (Vo V ) N a  N d  W

The expression for Cj is an exact analogy with that of a parallel plate


capacitor, with the depletion width W corresponding to the plate separation of
the capacitor.

Pg.8
Physically as we change the bias V across the p-n junction, it takes time for
the majority carriers to respond in order to expose a larger space charge
region under RB, or a smaller space charge region under FB.
Cj is associated with this delay time for W to reach its steady state width. In
other words, W cannot change instantaneously in response to a sudden change
in the bias.
It is quite common to write the expression for Cj as a function of applied
voltage. Cj is often written as
1/ 2
 Vo 
C j (V )  C j 0  
 o
V  V 
where Cj0 is the zero-bias junction capacitance, given by
1
 q 1 Na Nd  2 
C j0   A 


2 Vo N a  N d 

Pg.9
m
 Vo 
C j (V )  C jo  
 o
V  V 

Pg.10
Work Example
The doping densities of an abrupt-junction silicon P-N diode are Na =
1017/cm3 and Nd = 81015/cm3 and the area of the junction is 2105 cm2.
Calculate the junction capacitance at (a) zero bias, (b) RB of 6 V and (c)
FB of 0.7 V. Assume ni = 1010 cm-3.
Solution: First, we have
1
 q Na Nd  2  A
Cj   A   (73)


2 (Vo V ) N a  N d  W

Also, the equilibrium contact potential Vo is


kT  N N 
Vo  ln  a 2 d 
q  ni 
 

Pg.11
Calculate Vo as
Vo = 0.0259 ln[(1017 8  1015)/(1010)2 ] = 0.77 V

(a) At zero bias


Cj  11.8  8.85 1014  2 105 
1
 19 15  2
 1.610 10  810 
17
 17

 2 11.88.851014 ( 0.77  0 ) 10 81015 

Cj = 0.56 pF

Pg.12
(b) With RB of 6 V,

Cj  11.8  8.85 1014  2 105 


1

 1.61019 1017  81015  2

 14

 2 11.88.8510 ( 0.77  6) 1017  81015 

Cj = 0.188 pF

Pg.13
(c) With FB of 0.7 V,
C j  11.8  8.85 1014  2 105 
1
 19  2
 1.610 1017  81015

 14
 17
 2 11.88.85 10 ( 0.77  0.7 ) 10 81015 

Cj = 1.85 pF

Note that junction capacitance in FB is much larger than that in RB as


the width of the depletion region is much smaller in FB.

Pg.14
b) Charge Storage Capacitance Cs
The application of FB to a diode results in a reduction in the barrier height, a
reduction in the depletion region width, and an injection of majority carriers
across the depletion region into the opposite region, where they are stored as
excess minority carriers. The density of the excess minority carriers
increases with increase in the FB.
Excess minority
Note that with changing bias V, holes pile-up
there will be a change in the
concentration of the excess
Hole
minority carriers stored at both injection
sides of the junction, near the
depletion region edges. The
concentration is increased upon
increasing the FB and decreased
upon decreasing the FB.

Pg.15
The increase in the minority carrier concentration does not take place
instantaneously with a sudden change in FB.
A delay time is involved in the minority carrier concentration attaining a
steady-state. This delay is due to capacitive effect as a result of stored
minority carrier charges in the neutral n and p regions. This is the origin of
storage capacitance.
The total excess stored charge for minority holes at n-side Qp is
   x '/ L p
Q p  qA
0 
pn ( x ') dx '  qApn x '0  0
e dx '

 qAL p pn x '0  


 p ( x ') p  x '0 e  x '/ L p  p ( e qV / kT 1 (74)
 n

n n0 ) e
 x '/ L p 

The total excess stored charge for minority electron at p-side Qn is


   x ''/ L p
Qn   qA
0 n p ( x '') dx p  
 qAn p x ''0  0 e dx ''

 
 qALn n p x ''0   n (x '')n  x ''0e
p p
 x ''/ Ln
 n p0 ( e qV / kT 1 ) e
 x ''/ Ln
(75) 
Pg.16
Here, pn(x’) and np(x’’) are the steady state profiles of the minority holes
and electrons respectively, given by
 x '/ L p  x '/ L p
p ( x ')   
pn x '0 e  pn0 ( e qV / kT
1 ) e

n p  x ''0  e
 x ''/ Ln  x ''/ Ln
n ( x '')   n p0 ( eqV / kT 1 ) e

Let Qs denote the total excess charge stored associated with the minority
carriers, viz., Qs = Qp + Qn.

Consider the case of a p+n junction under FB. Recall that the hole injection
current will dominate. This transforms to pn >> np, and hence Qp >> Qn.
(and Ip(x’ = 0) >> In(x’’ = 0) generally).

Pg.17
Hence,
dQs dQ p
Cs  
dV dV (76)

Recall 
pn x '0   pn ( x '  0)  pn0  pn0 ( eqV / kT 1 )

 pn0 eqV / kT

Thus, the storage charge capacitance Cs associated with this change of


storage charge is

d Qp q2 q
Cs   AL p pn0e qV / KT  Qp (77)
dV kT kT

Q p  qALp pn  x '  0 


Note:

Pg.18
Dp Dp
I p  x '  0  diff  qA pn  x '  0  e  x '/ Lp
 qA pn  x '  0 
Lp Lp

For p+n junction hole injection current will dominate and hence the total
current I is given by
q A Dp qAL p pn  x ' 0  Qp
I pn  x '  0    (78)
Lp p p
since Lp = (Dpp)1/2

Thus, Qp  Ip.

Hence, Cs can also be expressed in terms of I and p as

q
Cs  I p (79)
kT

Pg.19
It can be seen that Cs can be very large under FB due to the large I. Physically,
this can be understood because the storage charge depends exponentially on the
bias voltage V under FB, meaning that there will be a large change in the
amount of storage charge (dQs) of the minority carriers with changing bias
(dV), resulting in a large Cs. The Cs will impose a serious limitation for a FB
biased p-n junction in high frequency applications.
The total capacitance across the pn junction is CT = Cj + Cs.

During FB, Cs is dominant (Cs >> Cj) due to the large change in the amount of
storage charge of the minority carriers, hence CT  Cs.

During RB, Cs is not critical (Cs << Cj) since there is only very small change
in the amount of storage charge of the minority carriers. In comparison, the
junction capacitance Cj dominates under RB, viz., CT  Cj.

The presence of these capacitances will limit the speed of operation of any
circuits using p-n junction diodes.

Pg.20
Work Example
The doping densities of an abrupt-junction silicon PN diode are Na =
1017/cm3 and Nd = 8  1015/cm3 and the area of the junction is 2  105 cm2.
The lifetime of holes in the n region is 0.1 μs. Given the diffusion constant
for holes in N is 16 cm2/s, calculate, at room temperature, the storage
capacitance at (a) FB of 0.6 V and (b) 0.65 V. Assume ni = 1010 cm-3.

Solution: Recall
q2
Cs  AL p pn0 e qV / kT
kT
Equilibrium density of holes in the N region is
pn0 = ni2/Nd = 1020/8  1015 = 1.25  104 /cm3
Also, Lp = (Dpp)1/2 = (16 0.110-6)1/2 = 1.26  10-3 cm

Pg.21
q2
(a) When the FB is 0.6 V, storage capacitance is Cs  AL p pn0e qV / kT
kT
(1.61019 )2
Cs   2 105  1.26 103  1.25 104  e0.6 / 0.026
0.0261.61019
Cs = 20.4 pF

(b) Similarly, at FB of 0.65 V


(1.61019 )2
Cs   2 105  1.26 103  1.25 104  e0.65/ 0.026
0.0261.61019
Cs = 139.6 pF

Note the large value of Cs. It is in fact much larger than Cj in FB (compare
with the previous example for Cj value. It was 1.85 pF at a FB of 0.7 V).

Pg.22

You might also like