4Gb DDR3L SDRAM

4Gb DDR3L SDRAM

Lead-Free&Halogen-Free
( RoHS Compliant)
H5TC4G83AFR-xxA
H5TC4G83AFR-xxI
H5TC4G83AFR-xxL
H5TC4G83AFR-xxJ
H5TC4G63AFR-xxA
H5TC4G63AFR-xxI
H5TC4G63AFR-xxL
H5TC4G63AFR-xxJ

* SK Hynix reserves the right to change products or specifications w ithout notice.

Rev. 1.1 / Jan. 2013 1

Revision History

Revision No. History Draft Date Remark

1.0 Official Version Release Oct. 2012

1.1 x8 IDD update Jan. 2013

Rev. 1.1 / Jan. 2013 2

Description
The H5TC4G83AFR-xxA(I,L,J) and H5TC4G63AFR-xxA(I,L,J) are a 4Gb low power Double Data Rate III
(DDR3L) Synchronous DRAM, ideally suited for the main memory applications which requires large mem-
ory density, high bandwidth and low power operation at 1.35V. SK Hynix DDR3L SDRAM provides backward
compatibility with the 1.5V DDR3 based environment without any changes. SK Hynix 4Gb DDR3L SDRAMs
offer fully synchronous operations referenced to both rising and falling edges of the clock. While all
addresses and control inputs are latched on the rising edges of the clock (falling edges of the clock), data,
data strobes and write data masks inputs are sampled on both rising and falling edges of it. The data
paths are internally pipelined and 8-bit prefetched to achieve very high bandwidth.

Device Features and Ordering I nformation

FEATURES
• VDD= VDDQ= 1.35V + 0.100 / - 0.067V • 8banks
• Fully differential clock inputs (CK, CK) operation • Average Refresh Cycle (Tcase of0 oC~ 95 oC)
• Differential Data Strobe (DQS, DQS) - 7.8 µs at 0oC ~ 85 oC
• On chip DLL align DQ, DQS and DQStransition with CK - 3.9 µs at 85oC ~ 95 oC
transition Commercial Temperature( 0oC ~ 85 oC)
• DM masks write data-in at the both rising and falling Industrial Temperature( -40oC ~ 95 oC)
edges of the data strobe • JEDEC standard 78ball FBGA(x8), 96ball FBGA (x16)
• All addresses and control inputs except data, Driver strength selected by EMRS
data strobes and data masks latched on the • Dynamic On Die Termination supported
rising edges of the clock
• Asynchronous RESET pin supported
• Programmable CAS latency 6, 7, 8, 9, 10 and 11,13
supported • ZQ calibration supported

• Programmable additive latency 0, CL-1, and CL-2 • TDQS (Termination Data Strobe) supported (x8 only)
supported • Write Levelization supported
• Programmable CAS Write latency (CWL) = 5, 6, 7,8 • 8 bit pre-fetch

• Programmable burst length 4/ 8 with both nibble

sequential and interleave mode
• BL switch on the fly

* This product in compliance w ith the RoHS directive.

Rev. 1.1 / Jan. 2013 3

ORDERI NG I NFORMATI ON

Part No. Configuration Pow er Consumption Temperature Package

H5TC4G83AFR-* xxA Commercial

Normal Consumption
H5TC4G83AFR-* xxI Industrial
512M x 8 78ball FBGA
H5TC4G83AFR-* xxL Low Power Consumption Commercial

H5TC4G83AFR-* xxJ (IDD6 Only) Industrial

H5TC4G63AFR-* xxA Commercial

Normal Consumption
H5TC4G63AFR-* xxI Industrial
256M x 16 96ball FBGA
H5TC4G63AFR-* xxL Low Power Consumption Commercial

H5TC4G63AFR-* xxJ (IDD6 Only) Industrial

* xx means Speed Bin Grade

OPERATI NG FREQUENCY

Speed Frequency [ MHz]

Remark
Grade
( CL-tRCD-tRP)
( Marking) CL5 CL6 CL7 CL8 CL9 CL10 CL11 CL12 CL13 CL14

-G7 667 800 1066 1066 DDR3L-1066 7-7-7

-H9 667 800 1066 1066 1333 1333 DDR3L-1333 9-9-9

-PB 667 800 1066 1066 1333 1333 1600 DDR3L-1600 11-11-11

-RD 800 1066 1066 1333 1333 1600 1866 DDR3L-1866 13-13-13

Rev. 1.1 / Jan. 2013 4

x8 Package Ball out ( Top view ) : 78ball FBGA Package

1 2 3 4 5 6 7 8 9

A VSS VDD NC NF/TDQS VSS VDD A

B VSS VSSQ DQ0 DM/TDQS VSSQ VDDQ B
C VDDQ DQ2 DQS DQ1 DQ3 VSSQ C
D VSSQ DQ6 DQS VDD VSS VSSQ D
E VREFDQ VDDQ DQ4 DQ7 DQ5 VDDQ E
F NC VSS RAS CK VSS NC F
G ODT VDD CAS CK VDD CKE G
H NC CS WE A10/AP ZQ NC H
J VSS BA0 BA2 A15 VREFCA VSS J
K VDD A3 A0 A12/BC BA1 VDD K
L VSS A5 A2 A1 A4 VSS L
M VDD A7 A9 A11 A6 VDD M
N VSS RESET A13 A14 A8 VSS N

1 2 3 4 5 6 7 8 9

1 2 3 7 8 9

A
B
C
D
E
F
(Top View: See the balls through the Package)
G
H
Populated ball
J
Ball not populated
K
L
M
N

Rev. 1.1 / Jan. 2013 5

x16 Package Ball out ( Top view ) : 96ball FBGA Package

1 2 3 4 5 6 7 8 9

A VDDQ DQU5 DQU7 DQU4 VDDQ VSS A

B VSSQ VDD VSS DQSU DQU6 VSSQ B
C VDDQ DQU3 DQU1 DQSU DQU2 VDDQ C
D VSSQ VDDQ DMU DQU0 VSSQ VDD D
E VSS VSSQ DQL0 DML VSSQ VDDQ E
F VDDQ DQL2 DQSL DQL1 DQL3 VSSQ F
G VSSQ DQL6 DQSL VDD VSS VSSQ G
H VREFDQ VDDQ DQL4 DQL7 DQL5 VDDQ H
J NC VSS RAS CK VSS NC J
K ODT VDD CAS CK VDD CKE K
L NC CS WE A10/AP ZQ NC L
M VSS BA0 BA2 NC VREFCA VSS M
N VDD A3 A0 A12/BC BA1 VDD N
P VSS A5 A2 A1 A4 VSS P
R VDD A7 A9 A11 A6 VDD R
T VSS RESET A13 A14 A8 VSS T

1 2 3 4 5 6 7 8 9

1 2 3 7 8 9

A
B
C
D
E
F
G (Top View: See the balls through the Package)
H
J Populated ball
K Ball not populated
L
M
N
P
R
T

Rev. 1.1 / Jan. 2013 6

Pin Functional Description
Symbol Type Function

Clock: CK and CK are differential clock inputs. All address and control input signals are
CK, CK Input
sampled on the crossing of the positive edge of CK and negative edge of CK.
Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and
device input buffers and output drivers. Taking CKE Low provides Precharge Power-Down
and Self-Refresh operation (all banks idle), or Active Power-Down (row Active in any
bank).
CKE, (CKE0),
Input CKE is asynchronous for Self-Refresh exit. After VREFCA and VREFDQ have become stable
(CKE1)
during the power on and initialization sequence, they must be maintained during all
operations (including Self-Refresh). CKE must be maintained high throughout read and
write accesses. Input buffers, excluding CK, CK, ODT and CKE, are disabled during power-
down. Input buffers, excluding CKE, are disabled during Self-Refresh.
CS, (CS0), Chip Select: All commands are masked when CS is registered HIGH.
(CS1), (CS2), Input CS provides for external Rank selection on systems with multiple Ranks.
(CS3) CS is considered part of the command code.
On Die Termination: ODT (registered HIGH) enables termination resistance internal to the
DDR3L SDRAM. When enabled, ODT is only applied to each DQ, DQS, DQS and DM/ TDQS,
ODT, (ODT0), NU/ TDQS (When TDQS is enabled via Mode Register A11= 1 in MR1) signal for x4/ x8
Input
(ODT1) configurations. For x16 configuration, ODT is applied to each DQ, DQSU, DQSU, DQSL,
DQSL, DMU, and DML signal. The ODT pin will be ignored if MR1 is programmed to disable
ODT.
RAS. Command Inputs: RAS, CAS and WE (along with CS) define the command being entered.
Input
CAS. WE
Input Data Mask: DM is an input mask signal for write data. Input data is masked when
DM, (DMU), DM is sampled HIGH coincident with that input data during a Write access. DM is sampled
Input
(DML) on both edges of DQS. For x8 device, the function of DM or TDQS/ TDQS is enabled by
Mode Register A11 setting in MR1.
Bank Address Inputs: BA0 - BA2 define to which bank an Active, Read, Write or Precharge
BA0 - BA2 Input command is being applied. Bank address also determines if the mode register or extended
mode register is to be accessed during a MRS cycle.
Address Inputs: Provide the row address for Active commands and the column address for
Read/ Write commands to select one location out of the memory array in the respective
A0 - A15 Input
bank. (A10/ AP and A12/ BC have additional functions, see below).
The address inputs also provide the op-code during Mode Register Set commands.
Auto-precharge: A10 is sampled during Read/ Write commands to determine whether
Autoprecharge should be performed to the accessed bank after the Read/ Write operation.
(HIGH: Autoprecharge; LOW: no Autoprecharge).A10 is sampled during a Precharge
A10 / AP Input
command to determine whether the Precharge applies to one bank (A10 LOW) or all
banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by bank
addresses.
Burst Chop: A12 / BC is sampled during Read and Write commands to determine if burst
A12 / BC Input chop (on-the-fly) will be performed.
(HIGH, no burst chop; LOW: burst chopped). See command truth table for details.

Rev. 1.1 / Jan. 2013 7

 Symbol Type Function

Active Low Asynchronous Reset: Reset is active when RESET is LOW, and inactive when
RESET is HIGH. RESET must be HIGH during normal operation.
RESET Input
RESET is a CMOS rail-to-rail signal with DC high and low at 80% and 20% of VDD, i.e.
1.20V for DC high and 0.30V for DC low.
Input /
DQ Data Input/ Output: Bi-directional data bus.
Output
Data Strobe: output with read data, input with write data. Edge-aligned with read data,
DQU, DQL,
centered in write data. The data strobe DQS, DQSL, and DQSU are paired with differential
DQS, DQS, Input /
signals DQS, DQSL, and DQSU, respectively, to provide differential pair signaling to the
DQSU, DQSU, Output
system during reads and writes. DDR3L SDRAM supports differential data strobe only and
DQSL, DQSL
does not support single-ended.
Termination Data Strobe: TDQS/ TDQS is applicable for x8 DRAMs only. When enabled via
Mode Register A11 = 1 in MR1, the DRAM will enable the same termination resistance
TDQS, TDQS Output function on TDQS/ TDQS that is applied to DQS/ DQS. When disabled via mode register A11
= 0 in MR1, DM/ TDQS will provide the data mask function and TDQS is not used. x4/ x16
DRAMs must disable the TDQS function via mode register A11 = 0 in MR1.
NC No Connect: No internal electrical connection is present.
NF No Function
VDDQ Supply DQ Power Supply: 1.5 V + / - 0.075 V
VSSQ Supply DQ Ground
VDD Supply Power Supply: 1.5 V + / - 0.075 V
VSS Supply Ground
VREFDQ Supply Reference voltage for DQ
VREFCA Supply Reference voltage for CA
ZQ Supply Reference Pin for ZQ calibration
Note:
Input only pins (BA0-BA2, A0-A15, RAS, CAS, WE, CS, CKE, ODT, DM, and RESET) do not supply termination.

Rev. 1.1 / Jan. 2013 8

ROW AND COLUMN ADDRESS TABLE
4Gb
Configuration 512Mb x 8 256Mb x 16
# of Banks 8 8
Bank Address BA0 - BA2 BA0 - BA2
Auto precharge A10/AP A10/AP
BL switch on the fly A12/ BC A12/BC
Row Address A0 - A15 A0 - A14
Column Address A0 - A9 A0 - A9
Page size 1 1 KB 2 KB

Note1: Page size is the number of bytes of data delivered from the array to the internal sense amplifiers
when an ACTIVE command is registered. Page size is per bank, calculated as follows:
page size = 2 COLBI TS * ORG  8
w here COLBI TS = the number of column address bits, ORG = the number of I / O ( DQ) bits

Rev. 1.1 / Jan. 2013 9

Absolute Maximum Ratings
Absolute Maximum DC Ratings
Absolute Maximum DC Ratings

Symbol Parameter Rating Units Notes

VDD Voltage on VDD pin relative to Vss - 0.4 V ~ 1.975 V V 1,3
VDDQ Voltage on VDDQ pin relative to Vss - 0.4 V ~ 1.975 V V 1,3
VIN, VOUT Voltage on any pin relative to Vss - 0.4 V ~ 1.975 V V 1
TSTG -55 to + 100 oC 1, 2
Storage Temperature
Notes:

1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rat-
ing conditions for extended periods may affect reliability.
2. Storage Temperature is the case surface temperature on the center/ top side of the DRAM. For the measurement
conditions, please refer to JESD51-2 standard.
3. VDD and VDDQ must be within 300mV of each other at all times; and VREF must not be greater than
0.6XVDDQ,When VDD and VDDQ are less than 500mV; VREF may be equal to or less than 300mV.

DRAM Component Operating

Temperature Range
Symbol Parameter Rating Units Notes
oC
Normal Operating Temperature Range 0 to 85 1,2
TOPER oC
Industrial Temperature Range -40 to 95 1,3
Notes:

1. Operating Temperature TOPER is the case surface temperature on the center / top side of the DRAM. For measure-
ment conditions, please refer to the JEDEC document JESD51-2.
2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. Dur-
ing operation, the DRAM case temperature must be maintained between 0 - 85oC under all operating conditions.
3. Some applications require operation of the DRAM in the Extended Temperature Range between 85oC and 95oC
case temperature. Full specifications are guaranteed in this range, but the following additional conditions apply:

a. Refresh commands must be doubled in frequency, therefore reducing the Refresh interval tREFI to 3.9 µs.
b. If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to use the Man-
ual Self-Refresh mode with Extended Temperature Range capability (MR2 A6 = 0b and MR2 A7 = 1b).

Rev. 1.1 / Jan. 2013 10

AC & DC Operating Conditions
Recommended DC Operating Conditions
Recommended DC Operating Conditions - DDR3L ( 1.35V) operation
Rating
Symbol Parameter Units Notes
Min. Typ. Max.
VDD Supply Voltage 1.283 1.35 1.45 V 1,2,3,4
VDDQ Supply Voltage for Output 1.283 1.35 1.45 V 1,2,3,4
Notes:

1. Maximum DC value may not be greater than 1.425V. The DC value is the linear average of VDD/ VDDQ (t) over a
very long period of time (e.g., 1 sec).
2. If maximum limit is exceeded, input levels shall be governed by DDR3 specifications.
3. Under these supply voltages, the device operates to this DDR3L specification.
4. Once initialized for DDR3L operation, DDR3 operation may only be used if the device is in reset while VDD and
VDDQ are changed for DDR3 operation (see Figure 0).

Recommended DC Operating Conditions - DDR3 ( 1.5V) operation

Rating
Symbol Parameter Units Notes
Min. Typ. Max.
VDD Supply Voltage 1.425 1.5 1.575 V 1,2,3
VDDQ Supply Voltage for Output 1.425 1.5 1.575 V 1,2,3
Notes:

1. If minimum limit is exceeded, input levels shall be governed by DDR3L specifications.

2. Under 1.5V operation, this DDR3L device operates to the DDR3 specifications under the same speed timings as
defined for this device.
3. Once initialized for DDR3 operation, DDR3L operation may only be used if the device is in reset while VDD and
VDDQ are changed for DDR3L operation (see Figure 0).

Rev. 1.1 / Jan. 2013 11

 Ta Tb Tc Td Te Tf Tg Th Ti Tj Tk

CK,CK#

Tmin = 10ns tCKSRX

VDD, VDDQ (DDR3)
VDD, VDDQ (DDR3L)

Tmin = 10ns Tmin = 200us

T = 500us

RESET#

CKE Tmin = 10ns VALID

tDLLK

tIS
tXPR tMRD tMRD tMRD tMOD tZQinit

COMMAND READ 1) MRS MRS MRS MRS ZQCL 1) VALID

BA READ MR2 MR3 MR1 MR0 VALID

tIS tIS

ODT READ Static LOW in case RTT_Nom is enabled at time Tg, otherwise static HIGH or LOW VALID

RTT

NOTE 1: From time point Td until Tk NOP or DES commands must be applied
TIME BREAK DON T CARE
between MRS and ZQCL commands.

Figure 0 - VDD/ VDDQ Voltage Switch Between DDR3L and DDR3L

Rev. 1.1 / Jan. 2013 12

I DD and I DDQ Specification Parameters and Test Conditions
I DD and I DDQ Measurement Conditions

In this chapter, IDD and I DDQ measurement conditions such as test load and patterns are defined. Figure
1. shows the setup and test load for IDD and IDDQ measurements.
• IDD currents (such as IDD0, IDD1, IDD2N, IDD2NT , IDD2P0, IDD2P1, IDD2Q, IDD3N, IDD3P, IDD4R,
IDD4W, IDD5B, IDD6, IDD6ET, and IDD7) are measured as time-averaged currents with all VDD balls
of the DDR3L SDRAM under test tied together. Any IDDQ current is not included in IDD currents.
• IDDQ currents (such as IDDQ2NT and IDDQ4R) are measured as time-averaged currents with all
VDDQ balls of the DDR3L SDRAM under test tied together. Any IDD current is not included in IDDQ
currents.
Attention: IDDQ values cannot be directly used to calculate IO power of the DDR3L SDRAM. They can
be used to support correlation of simulated IO power to actual IO power as outlined in Figure 2. In
DRAM module application, I DDQ cannot be measured separately since VDD and VDDQ are using one
merged-power layer in Module PCB.
For I DD and IDDQ measurements, the following definitions apply:

• ”0” and “LOW” is defined as VIN < = VILAC(max).

• ”1” and “HIGH” is defined as VIN > = VIHAC(max).
• “MID_LEVEL” is defined asinputs are VREF = VDD/ 2.
• Timing used for IDD and IDDQ Measurement-Loop Patterns are provided in Table 1.
• Basic IDD and IDDQ Measurement Conditions are described in Table 2.
• Detailed IDD and IDDQ Measurement-Loop Patterns are described in Table 3 through Table 10.
• IDD Measurements are done after properly initializing the DDR3L SDRAM. This includes but is not lim-
ited to setting
RON = RZQ/ 7 (34 Ohm in MR1);
Qoff = 0B (Output Buffer enabled in MR1);
RTT_Nom = RZQ/ 6 (40 Ohm in MR1);
RTT_Wr = RZQ/ 2 (120 Ohm in MR2);
TDQS Feature disabled in MR1
• Attention: The IDD and IDDQ Measurement-Loop Patterns need to be executed at least one time
before actual IDD or IDDQ measurement is started.
• Define D = { CS, RAS, CAS, WE} := { HIGH, LOW, LOW, LOW}
• Define D= { CS, RAS, CAS, WE} := { HIGH, HIGH, HIGH, HIGH}

Rev. 1.1 / Jan. 2013 13

 IDD IDDQ (optional)

VDD VDDQ
RESET
CK/CK
DDR3L
SDRAM
CKE DQS, DQS RTT = 25 Ohm
CS DQ, DM, VDDQ/2
RAS, CAS, WE TDQS, TDQS

A, BA
ODT
ZQ
VSS VSSQ

Figure 1 - Measurement Setup and Test Load for IDD and IDDQ (optional) Measurements
[ Note: DIMM level Output test load condition may be different from above]

Application specific IDDQ

memory channel Test Load
environment

Channel
IDDQ IDDQ
IO Power
Simulation Simulation
Simulation

Correction

Channel IO Power
Number

Figure 2 - Correlation from simulated Channel IO Power to actual Channel IO Power supported
by IDDQ Measurement

Rev. 1.1 / Jan. 2013 14

Table 1 - Timings used for I DD and I DDQ Measurement-Loop Patterns
DDR3L-1066 DDR3L- 1333 DDR3L- 1600 DDR3L-1866
Symbol Unit
7- 7- 7 9-9-9 11-11- 11 13-13- 13
t CK 1.875 1.5 1.25 1.07 ns
CL 7 9 11 13 nCK
nRCD 7 9 11 13 nCK
nRC 27 33 39 45 nCK
nRAS 20 24 28 32 nCK
nRP 7 9 11 13 nCK
1KB page size 20 20 24 26 nCK
nFAW
2KB page size 27 30 32 33 nCK
1KB page size 4 4 5 5 nCK
nRRD
2KB page size 6 5 6 6 nCK
nRFC -512Mb 48 60 72 85 nCK
nRFC-1 Gb 59 74 88 103 nCK
nRFC- 2 Gb 86 107 128 150 nCK
nRFC- 4 Gb 139 174 208 243 nCK
nRFC- 8 Gb 187 234 280 328 nCK

Table 2 -Basic I DD and I DDQ Measurement Conditions

Symbol Description
Operating One Bank Active-Precharge Current

CKE: High; External clock: On; tCK, nRC, nRAS, CL: see Table 1; BL: 8a) ; AL: 0; CS: High between ACT
and PRE; Command, Address, Bank Address Inputs: partially toggling according to Table 3; Data IO:
I DD0
MID-LEVEL; DM: stable at 0; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,... (see

Table 3); Output Buffer and RTT: Enabled in Mode Registersb) ; ODT Signal: stable at 0; Pattern Details:
see Table 3.
Operating One Bank Active-Precharge Current

CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: see Table 1; BL: 8a) ; AL: 0; CS: High between
ACT, RD and PRE; Command, Address; Bank Address Inputs, Data IO: partially toggling according to
I DD1
Table 4; DM: stable at 0; Bank Activity: Cycling with on bank active at a time: 0,0,1,1,2,2,... (see Table

4); Output Buffer and RTT: Enabled in Mode Registersb) ; ODT Signal: stable at 0; Pattern Details: see
Table 4.

Rev. 1.1 / Jan. 2013 15

 Symbol Description
Precharge Standby Current

CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a) ; AL: 0; CS: stable at 1; Command, Address,
I DD2N Bank Address Inputs: partially toggling according to Table 5; Data IO: MID_LEVEL; DM: stable at 0;

Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb) ; ODT Signal: stable
at 0; Pattern Details: see Table 5.
Precharge Standby ODT Current

CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a) ; AL: 0; CS: stable at 1; Command, Address,
I DD2NT Bank Address Inputs: partially toggling according to Table 6; Data IO: MID_LEVEL; DM: stable at 0;

Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb) ; ODT Signal: tog-
gling according to Table 6; Pattern Details: see Table 6.
Precharge Power-Down Current Slow Exit

CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8a) ; AL: 0; CS: stable at 1; Command, Address,
I DD2P0 Bank Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed;

Output Buffer and RTT: Enabled in Mode Registersb) ; ODT Signal: stable at 0; Precharge Power Down

Mode: Slow Exit c)

Precharge Power-Down Current Fast Exit

CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8a) ; AL: 0; CS: stable at 1; Command, Address,
I DD2P1 Bank Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed;

Output Buffer and RTT: Enabled in Mode Registersb) ; ODT Signal: stable at 0; Precharge Power Down

Mode: Fast Exit c)

Precharge Quiet Standby Current

CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a) ; AL: 0; CS: stable at 1; Command, Address,
I DD2Q
Bank Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed;

Output Buffer and RTT: Enabled in Mode Registersb) ; ODT Signal: stable at 0
Active Standby Current

CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a) ; AL: 0; CS: stable at 1; Command, Address,
I DD3N Bank Address Inputs: partially toggling according to Table 5; Data IO: MID_LEVEL; DM: stable at 0;

Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registersb) ; ODT Signal: stable
at 0; Pattern Details: see Table 5.

Rev. 1.1 / Jan. 2013 16

 Symbol Description
Active Power-Down Current

CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8a) ; AL: 0; CS: stable at 1; Command, Address,
I DD3P
Bank Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks open;

Output Buffer and RTT: Enabled in Mode Registersb) ; ODT Signal: stable at 0
Operating Burst Read Current

CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a) ; AL: 0; CS: High between RD; Command,
Address, Bank Address Inputs: partially toggling according to Table 7; Data IO: seamless read data burst
I DD4R
with different data between one burst and the next one according to Table 7; DM: stable at 0; Bank
Activity: all banks open, RD commands cycling through banks: 0,0,1,1,2,2,...(see Table 7); Output Buffer

and RTT: Enabled in Mode Registersb) ; ODT Signal: stable at 0; Pattern Details: see Table 7.
Operating Burst Write Current

CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a) ; AL: 0; CS: High between WR; Command,
Address, Bank Address Inputs: partially toggling according to Table 8; Data IO: seamless read data burst
I DD4W
with different data between one burst and the next one according to Table 8; DM: stable at 0; Bank
Activity: all banks open, WR commands cycling through banks: 0,0,1,1,2,2,...(see Table 8); Output Buf-

fer and RTT: Enabled in Mode Registersb) ; ODT Signal: stable at HIGH; Pattern Details: see Table 8.
Burst Refresh Current

CKE: High; External clock: On; tCK, CL, nRFC: see Table 1; BL: 8a) ; AL: 0; CS: High between REF; Com-
I DD5B mand, Address, Bank Address Inputs: partially toggling according to Table 9; Data IO: MID_LEVEL; DM:
stable at 0; Bank Activity: REF command every nREF (see Table 9); Output Buffer and RTT: Enabled in

Mode Registersb) ; ODT Signal: stable at 0; Pattern Details: see Table 9.

Self-Refresh Current: Normal Temperature Range

TCASE: 0 - 85 oC; Auto Self-Refresh (ASR): Disabledd) ;Self-Refresh Temperature Range (SRT): Normale) ;
I DD6 CKE: Low; External clock: Off; CK and CK: LOW; CL: see Table 1; BL: 8a) ; AL: 0; CS, Command, Address,
Bank Address Inputs, Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: Self-Refresh operation; Out-

put Buffer and RTT: Enabled in Mode Registersb) ; ODT Signal: MID_LEVEL

Self-Refresh Current: Extended Temperature Range (optional) f)

TCASE: 0 - 95 oC; Auto Self-Refresh (ASR): Disabledd) ;Self-Refresh Temperature Range (SRT): Extend-

I DD6ET ede) ; CKE: Low; External clock: Off; CK and CK: LOW; CL: see Table 1; BL: 8a) ; AL: 0; CS, Command,
Address, Bank Address Inputs, Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: Extended Tempera-

ture Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registersb) ; ODT Signal:
MID_LEVEL

Rev. 1.1 / Jan. 2013 17

 Symbol Description
Operating Bank Interleave Read Current

CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, NRRD, nFAW, CL: see Table 1; BL: 8a), f) ; AL: CL-
1; CS: High between ACT and RDA; Command, Address, Bank Address Inputs: partially toggling accord-
I DD7 ing to Table 10; Data IO: read data burst with different data between one burst and the next one
according to Table 10; DM: stable at 0; Bank Activity: two times interleaved cycling through banks (0,

1,...7) with different addressing, wee Table 10; Output Buffer and RTT: Enabled in Mode Registersb) ;
ODT Signal: stable at 0; Pattern Details: see Table 10.

a) Burst Length: BL8 fixed by MRS: set MR0 A[ 1,0] = 00B

b) Output Buffer Enable: set MR1 A[ 12] = 0B; set MR1 A[5,1] = 01B; RTT_Nom enable: set MR1 A[ 9,6,2] = 011B;
RTT_Wr enable: set MR2 A[ 10,9] = 10B
c) Precharge Power Down Mode: set MR0 A12= 0B for Slow Exit or MR0 A12 = 1B for Fast Exit
d) Auto Self-Refresh (ASR): set MR2 A6 = 0B to disable or 1B to enable feature
e) Self-Refresh Temperature Range (SRT): set MR2 A7 = 0B for normal or 1B for extended temperature range
f) Read Burst Type: Nibble Sequential, set MR0 A[ 3] = 0B

Rev. 1.1 / Jan. 2013 18

Table 3 - I DD0 Measurement-Loop Patterna)

Command
Sub-Loop

Number

A[ 15:11]
BA[ 2:0]
CK, CK

A[ 9:7]

A[ 6:3]

A[ 2:0]
A[ 10]
Cycle

ODT
RAS
CKE

CAS

WE
CS
Data b)

0 0 ACT 0 0 1 1 0 0 00 0 0 0 0 -
1,2 D, D 1 0 0 0 0 0 00 0 0 0 0 -
3,4 D, D 1 1 1 1 0 0 00 0 0 0 0 -
... repeat pattern 1...4 until nRAS - 1, truncate if necessary
nRAS PRE 0 0 1 0 0 0 00 0 0 0 0 -
... repeat pattern 1...4 until nRC - 1, truncate if necessary
1* nRC+ 0 ACT 0 0 1 1 0 0 00 0 0 F 0 -
1* nRC+ 1, 2 D, D 1 0 0 0 0 0 00 0 0 F 0 -
Static High

1* nRC+ 3, 4 D, D 1 1 1 1 0 0 00 0 0 F 0 -
toggling

... repeat pattern 1...4 until 1* nRC + nRAS - 1, truncate if necessary

1* nRC+ nRAS PRE 0 0 1 0 0 0 00 0 0 F 0 -
... repeat pattern 1...4 until 2* nRC - 1, truncate if necessary
1 2* nRC repeat Sub-Loop 0, use BA[ 2:0] = 1 instead
2 4* nRC repeat Sub-Loop 0, use BA[ 2:0] = 2 instead
3 6* nRC repeat Sub-Loop 0, use BA[ 2:0] = 3 instead
4 8* nRC repeat Sub-Loop 0, use BA[ 2:0] = 4 instead
5 10* nRC repeat Sub-Loop 0, use BA[ 2:0] = 5 instead
6 12* nRC repeat Sub-Loop 0, use BA[ 2:0] = 6 instead
7 14* nRC repeat Sub-Loop 0, use BA[ 2:0] = 7 instead

a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.
b) DQ signals are MID-LEVEL.

Rev. 1.1 / Jan. 2013 19

Table 4 - I DD1 Measurement-Loop Patterna)

Command
Sub-Loop

Number

A[ 15:11]
BA[ 2:0]
CK, CK

A[ 9:7]

A[ 6:3]

A[ 2:0]
A[ 10]
Cycle

ODT
RAS
CKE

CAS

WE
CS
Data b)

0 0 ACT 0 0 1 1 0 0 00 0 0 0 0 -
1,2 D, D 1 0 0 0 0 0 00 0 0 0 0 -
3,4 D, D 1 1 1 1 0 0 00 0 0 0 0 -
... repeat pattern 1...4 until nRCD - 1, truncate if necessary
nRCD RD 0 1 0 1 0 0 00 0 0 0 0 00000000
... repeat pattern 1...4 until nRAS - 1, truncate if necessary
nRAS PRE 0 0 1 0 0 0 00 0 0 0 0 -
... repeat pattern 1...4 until nRC - 1, truncate if necessary
1* nRC+ 0 ACT 0 0 1 1 0 0 00 0 0 F 0 -
1* nRC+ 1,2 D, D 1 0 0 0 0 0 00 0 0 F 0 -
Static High

1* nRC+ 3,4 D, D 1 1 1 1 0 0 00 0 0 F 0 -
toggling

... repeat pattern nRC + 1,...4 until nRC + nRCE - 1, truncate if necessary
1* nRC+ nRCD RD 0 1 0 1 0 0 00 0 0 F 0 00110011
... repeat pattern nRC + 1,...4 until nRC + nRAS - 1, truncate if necessary
1* nRC+ nRAS PRE 0 0 1 0 0 0 00 0 0 F 0 -
... repeat pattern nRC + 1,...4 until * 2 nRC - 1, truncate if necessary
1 2* nRC repeat Sub-Loop 0, use BA[ 2:0] = 1 instead
2 4* nRC repeat Sub-Loop 0, use BA[ 2:0] = 2 instead
3 6* nRC repeat Sub-Loop 0, use BA[ 2:0] = 3 instead
4 8* nRC repeat Sub-Loop 0, use BA[ 2:0] = 4 instead
5 10* nRC repeat Sub-Loop 0, use BA[ 2:0] = 5 instead
6 12* nRC repeat Sub-Loop 0, use BA[ 2:0] = 6 instead
7 14* nRC repeat Sub-Loop 0, use BA[ 2:0] = 7 instead

a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL.
b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID_LEVEL.

Rev. 1.1 / Jan. 2013 20

Table 5 - I DD2N and I DD3N Measurement-Loop Patterna)

Command
Sub-Loop

Number

A[ 15:11]
BA[ 2:0]
CK, CK

A[ 9:7]

A[ 6:3]

A[ 2:0]
A[ 10]
Cycle

ODT
RAS
CKE

CAS

WE
CS
Data b)

0 0 D 1 0 0 0 0 0 0 0 0 0 0 -
1 D 1 0 0 0 0 0 0 0 0 0 0 -
2 D 1 1 1 1 0 0 0 0 0 F 0 -
3 D 1 1 1 1 0 0 0 0 0 F 0 -
Static High

1 4-7 repeat Sub-Loop 0, use BA[ 2:0] = 1 instead

toggling

2 8-11 repeat Sub-Loop 0, use BA[ 2:0] = 2 instead

3 12-15 repeat Sub-Loop 0, use BA[ 2:0] = 3 instead
4 16-19 repeat Sub-Loop 0, use BA[ 2:0] = 4 instead
5 20-23 repeat Sub-Loop 0, use BA[ 2:0] = 5 instead
6 24-17 repeat Sub-Loop 0, use BA[ 2:0] = 6 instead
7 28-31 repeat Sub-Loop 0, use BA[ 2:0] = 7 instead

a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.
b) DQ signals are MID-LEVEL.

Table 6 - I DD2NT and I DDQ2NT Measurement-Loop Patterna)

Command
Sub-Loop

Number

A[ 15:11]
BA[ 2:0]
CK, CK

A[ 9:7]

A[ 6:3]

A[ 2:0]
A[ 10]
Cycle

ODT
RAS
CKE

CAS

WE
CS

Data b)

0 0 D 1 0 0 0 0 0 0 0 0 0 0 -
1 D 1 0 0 0 0 0 0 0 0 0 0 -
2 D 1 1 1 1 0 0 0 0 0 F 0 -
3 D 1 1 1 1 0 0 0 0 0 F 0 -
Static High

1 4-7 repeat Sub-Loop 0, but ODT = 0 and BA[ 2:0] = 1

toggling

2 8-11 repeat Sub-Loop 0, but ODT = 1 and BA[ 2:0] = 2

3 12-15 repeat Sub-Loop 0, but ODT = 1 and BA[ 2:0] = 3
4 16-19 repeat Sub-Loop 0, but ODT = 0 and BA[ 2:0] = 4
5 20-23 repeat Sub-Loop 0, but ODT = 0 and BA[ 2:0] = 5
6 24-17 repeat Sub-Loop 0, but ODT = 1 and BA[ 2:0] = 6
7 28-31 repeat Sub-Loop 0, but ODT = 1 and BA[ 2:0] = 7

a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.
b) DQ signals are MID-LEVEL.

Rev. 1.1 / Jan. 2013 21

Table 7 - I DD4R and I DDQ4R Measurement-Loop Patterna)

Command
Sub-Loop

Number

A[ 15:11]
BA[ 2:0]
CK, CK

A[ 9:7]

A[ 6:3]

A[ 2:0]
A[ 10]
Cycle

ODT
RAS
CKE

CAS

WE
CS
Data b)

0 0 RD 0 1 0 1 0 0 00 0 0 0 0 00000000
1 D 1 0 0 0 0 0 00 0 0 0 0 -
2,3 D,D 1 1 1 1 0 0 00 0 0 0 0 -
4 RD 0 1 0 1 0 0 00 0 0 F 0 00110011
5 D 1 0 0 0 0 0 00 0 0 F 0 -
Static High

6,7 D,D 1 1 1 1 0 0 00 0 0 F 0 -
toggling

1 8-15 repeat Sub-Loop 0, but BA[ 2:0] = 1

2 16-23 repeat Sub-Loop 0, but BA[ 2:0] = 2
3 24-31 repeat Sub-Loop 0, but BA[ 2:0] = 3
4 32-39 repeat Sub-Loop 0, but BA[ 2:0] = 4
5 40-47 repeat Sub-Loop 0, but BA[ 2:0] = 5
6 48-55 repeat Sub-Loop 0, but BA[ 2:0] = 6
7 56-63 repeat Sub-Loop 0, but BA[ 2:0] = 7

a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL.
b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID-LEVEL.

Rev. 1.1 / Jan. 2013 22

Table 8 - I DD4W Measurement-Loop Patterna)

Command
Sub-Loop

Number

A[ 15:11]
BA[ 2:0]
CK, CK

A[ 9:7]

A[ 6:3]

A[ 2:0]
A[ 10]
Cycle

ODT
RAS
CKE

CAS

WE
CS
Data b)

0 0 WR 0 1 0 0 1 0 00 0 0 0 0 00000000
1 D 1 0 0 0 1 0 00 0 0 0 0 -
2,3 D,D 1 1 1 1 1 0 00 0 0 0 0 -
4 WR 0 1 0 0 1 0 00 0 0 F 0 00110011
5 D 1 0 0 0 1 0 00 0 0 F 0 -
Static High

6,7 D,D 1 1 1 1 1 0 00 0 0 F 0 -
toggling

1 8-15 repeat Sub-Loop 0, but BA[ 2:0] = 1

2 16-23 repeat Sub-Loop 0, but BA[ 2:0] = 2
3 24-31 repeat Sub-Loop 0, but BA[ 2:0] = 3
4 32-39 repeat Sub-Loop 0, but BA[ 2:0] = 4
5 40-47 repeat Sub-Loop 0, but BA[ 2:0] = 5
6 48-55 repeat Sub-Loop 0, but BA[ 2:0] = 6
7 56-63 repeat Sub-Loop 0, but BA[ 2:0] = 7

a) DM must be driven LOW all the time. DQS, DQS are used according to WR Commands, otherwise MID-LEVEL.
b) Burst Sequence driven on each DQ signal by Write Command. Outside burst operation, DQ signals are MID-LEVEL.

Table 9 - I DD5B Measurement-Loop Patterna)

Command
Sub-Loop

Number

A[ 15:11]
BA[ 2:0]
CK, CK

A[ 9:7]

A[ 6:3]

A[ 2:0]
A[ 10]
Cycle

ODT
RAS
CKE

CAS

WE
CS

Data b)

0 0 REF 0 0 0 1 0 0 0 0 0 0 0 -
1 1.2 D, D 1 0 0 0 0 0 00 0 0 0 0 -
3,4 D, D 1 1 1 1 0 0 00 0 0 F 0 -
5...8 repeat cycles 1...4, but BA[ 2:0] = 1
Static High

9...12 repeat cycles 1...4, but BA[ 2:0] = 2

toggling

13...16 repeat cycles 1...4, but BA[ 2:0] = 3

17...20 repeat cycles 1...4, but BA[ 2:0] = 4
21...24 repeat cycles 1...4, but BA[ 2:0] = 5
25...28 repeat cycles 1...4, but BA[ 2:0] = 6
29...32 repeat cycles 1...4, but BA[ 2:0] = 7
2 33...nRFC-1 repeat Sub-Loop 1, until nRFC - 1. Truncate, if necessary.

a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.
b) DQ signals are MID-LEVEL.

Rev. 1.1 / Jan. 2013 23

Table 10 - I DD7 Measurement-Loop Patterna)
ATTENTION! Sub-Loops 10-19 have inverse A[ 6:3] Pattern and Data Pattern than Sub-Loops 0-9

Command
Sub-Loop

Number

A[ 15:11]
BA[ 2:0]
CK, CK

A[ 9:7]

A[ 6:3]

A[ 2:0]
A[ 10]
Cycle

ODT
RAS
CKE

CAS

WE
CS
Data b)

0 0 ACT 0 0 1 1 0 0 00 0 0 0 0 -
1 RDA 0 1 0 1 0 0 00 1 0 0 0 00000000
2 D 1 0 0 0 0 0 00 0 0 0 0 -
... repeat above D Command until nRRD - 1
nRRD ACT 0 0 1 1 0 1 00 0 0 F 0 -
nRRD+ 1 RDA 0 1 0 1 0 1 00 1 0 F 0 00110011
1
nRRD+ 2 D 1 0 0 0 0 1 00 0 0 F 0 -
... repeat above D Command until 2* nRRD - 1
2 2* nRRD repeat Sub-Loop 0, but BA[ 2:0] = 2
3 3* nRRD repeat Sub-Loop 1, but BA[ 2:0] = 3
4* nRRD D 1 0 0 0 0 3 00 0 0 F 0 -
4
Assert and repeat above D Command until nFAW - 1, if necessary
5 nFAW repeat Sub-Loop 0, but BA[ 2:0] = 4
6 nFAW+ nRRD repeat Sub-Loop 1, but BA[ 2:0] = 5
7 nFAW+ 2* nRRD repeat Sub-Loop 0, but BA[ 2:0] = 6
8 nFAW+ 3* nRRD repeat Sub-Loop 1, but BA[ 2:0] = 7
nFAW+ 4* nRRD D 1 0 0 0 0 7 00 0 0 F 0 -
Static High

9
toggling

Assert and repeat above D Command until 2* nFAW - 1, if necessary

2* nFAW+ 0 ACT 0 0 1 1 0 0 00 0 0 F 0 -
2* nFAW+ 1 RDA 0 1 0 1 0 0 00 1 0 F 0 00110011
10
D 1 0 0 0 0 0 00 0 0 F 0 -
2&nFAW+ 2
Repeat above D Command until 2* nFAW + nRRD - 1
2* nFAW+ nRRD ACT 0 0 1 1 0 1 00 0 0 0 0 -
2* nFAW+ nRRD+ 1 RDA 0 1 0 1 0 1 00 1 0 0 0 00000000
11
2&nFAW+ nRRD+ D 1 0 0 0 0 1 00 0 0 0 0 -
2 Repeat above D Command until 2* nFAW + 2* nRRD - 1
12 2* nFAW+ 2* nRRD repeat Sub-Loop 10, but BA[ 2:0] = 2
13 2* nFAW+ 3* nRRD repeat Sub-Loop 11, but BA[ 2:0] = 3
D 1 0 0 0 0 3 00 0 0 0 0 -
14 2* nFAW+ 4* nRRD
Assert and repeat above D Command until 3* nFAW - 1, if necessary
15 3* nFAW repeat Sub-Loop 10, but BA[ 2:0] = 4
16 3* nFAW+ nRRD repeat Sub-Loop 11, but BA[ 2:0] = 5
17 3* nFAW+ 2* nRRD repeat Sub-Loop 10, but BA[ 2:0] = 6
18 3* nFAW+ 3* nRRD repeat Sub-Loop 11, but BA[ 2:0] = 7
D 1 0 0 0 0 7 00 0 0 0 0 -
19 3* nFAW+ 4* nRRD
Assert and repeat above D Command until 4* nFAW - 1, if necessary

a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL.
b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID-LEVEL.

Rev. 1.1 / Jan. 2013 24

I DD Specifications
IDD values are for full operating range of voltage and temperature unless otherwise noted.

I DD Specification
DDR3L - 1066 DDR3L - 1333 DDR3L - 1600 DDR3L - 1866
Speed Grade Bin
7-7-7 9- 9- 9 11-11-11 13- 13-13 Unit Notes
Symbol Max. Max. Max. Max.
I DD0 30 32 33 34 mA x8
41 42 43 44 mA x16
I DD1 37 39 40 41 mA x8
51 53 53 54 mA x16
15 16 17 18 mA x8
I DD2N
20 20 22 23 mA x16
18 20 21 22 mA x8
I DD2NT
23 24 27 29 mA x16
8 8 8 8 mA x8
I DD2P0
12 12 12 13 mA x16
9 10 10 11 mA x8
I DD2P1
14 14 14 15 mA x16
16 17 17 17 mA x8
I DD2Q
20 21 23 24 mA x16
24 25 26 27 mA x8
I DD3N
26 27 29 29 mA x16
17 17 18 18 mA x8
I DD3P
18 18 19 20 mA x16
65 75 85 95 mA x8
I DD4R
90 110 125 140 mA x16
70 80 90 100 mA x8
I DD4W
100 120 135 155 mA x16
I DD5B 200 200 200 200 mA x8/ x16
12 12 12 12 mA x8
I DD6
15 15 15 15 mA x16
16 16 16 16 mA x8
I DD6ET
18 18 18 18 mA x16
10 10 10 10 mA x8
I DD6 Low Power
12 12 12 12 mA x16
110 130 135 145 mA x8
I DD7
170 195 200 205 mA x16

Notes:

1. Applicable for MR2 settings A6= 0 and A7= 0. Temperature range for IDD6 is 0 - 85oC.

2. Applicable for MR2 settings A6= 0 and A7= 1. Temperature range for IDD6ET is 0 - 95oC.

Rev. 1.1 / Jan. 2013 25

I nput/ Output Capacitance
DDR3L-1066 DDR3L-1333 DDR3L- 1600 DDR3L- 1866 Unit Note
Parameter Symbol
Min Max Min Max Min Max Min Max s s

Input/ output capacitance

(DQ, DM, DQS, DQS, CIO 1.5 2.7 1.5 2.5 1.5 2.3 1.4 2.2 pF 1,2,3
TDQS, TDQS)
Input capacitance, CK and
CCK 0.8 1.6 0.8 1.4 0.8 1.4 0.8 1.3 pF 2,3
CK
Input capacitance delta
CDCK 0 0.15 0 0.15 0 0.15 0 0.15 pF 2,3,4
CK and CK
Input capacitance delta,
CDDQS 0 0.20 0 0.15 0 0.15 0 0.15 pF 2,3,5
DQS and DQS
Input capacitance
CI 0.75 1.35 0.75 1.3 0.75 1.3 0.75 1.2 pF 2,3,6
(All other input-only pins)
Input capacitance delta 2,3,7,
CDI_CTRL -0.5 0.3 -0.4 0.2 -0.4 0.2 -0.4 0.2 pF
(All CTRL input-only pins) 8
Input capacitance delta
CDI_ADD_ 2,3,9,
(All ADD/ CMD input-only -0.5 0.5 -0.4 0.4 -0.4 0.4 -0.4 0.4 pF
CMD 10
pins)
Input/ output capacitance
2,3,
delta CDIO -0.5 0.3 -0.5 0.3 -0.5 0.3 -0.5 0.3 pF
11
(DQ, DM, DQS, DQS)
Input/ output capacitance 2,3,
CZQ - 3 - 3 - 3 - 3 pF
of ZQ pin 12
Notes:
1. Although the DM, TDQS and TDQS pins have different functions, the loading matches DQ and DQS.
2. This parameter is not subject to production test. It is verified by design and characterization. The capacitance is
measured according to JEP147(“PROCEDURE FOR MEASURING INPUT CAPACITANCE USING A VECTOR NETWORK
ANALYZER(VNA)”) with VDD, VDDQ, VSS,VSSQ applied and all other pins floating (except the pin under test, CKE,
RESET and ODT as necessary). VDD= VDDQ= 1.5V, VBIAS= VDD/ 2 and on-die termination off.
3. This parameter applies to monolithic devices only; stacked/ dual-die devices are not covered here
4. Absolute value of CCK-CCK.

5. Absolute value of CIO(DQS)-CIO(DQS).

6. CI applies to ODT, CS, CKE, A0-A15, BA0-BA2, RAS, CAS, WE.

7. CDI_CTR applies to ODT, CS and CKE.

8. CDI_CTRL= CI (CNTL) - 0.5 * CI (CLK) + CI (CLK))

9. CDI_ADD_CMD applies to A0-A15, BA0-BA2, RAS, CAS and WE.

10. CDI_ADD_CMD= CI (ADD_CMD) - 0.5* (CI (CLK)+ CI (CLK))

11. CDIO= CIO(DQ) - 0.5* (CIO(DQS)+ CIO(DQS))

12. Maximum external load capacitance an ZQ pin: 5 pF.

Rev. 1.1 / Jan. 2013 26

Standard Speed Bins
DDR3L SDRAM Standard Speed Bins include tCK, tRCD, tRP, tRAS and tRC for each corresponding bin.

DDR3L- 1066 Speed Bins

For specific Notes see “Speed Bin Table Notes” on page 31.

Speed Bin DDR3L- 1066

Unit Note
CL - nRCD - nRP 7-7-7
Parameter Symbol min max
Internal read command to
t AA 13.125 20 ns
first data

ACT to internal read or

t RCD 13.125 — ns
write delay time

PRE command period t RP 13.125 — ns

ACT to ACT or REF

t RC 50.625 — ns
command period

ACT to PRE command

t RAS 37.5 9 * tREFI ns
period
1, 2, 3, 4, 6,
CWL = 5 t CK(AVG) 3.0 3.3 ns
CL = 5 12,13
CWL = 6 t CK(AVG) Reserved ns 4
CWL = 5 t CK(AVG) 2.5 3.3 ns 1, 2, 3, 6
CL = 6
CWL = 6 t CK(AVG) Reserved ns 1, 2, 3, 4
CWL = 5 t CK(AVG) Reserved ns 4
CL = 7
CWL = 6 t CK(AVG) 1.875 < 2.5 ns 1, 2, 3, 4
CWL = 5 t CK(AVG) Reserved ns 4
CL = 8
CWL = 6 t CK(AVG) 1.875 < 2.5 ns 1, 2, 3
Supported CL Settings 5, 6, 7, 8 nCK 13
Supported CWL Settings 5, 6 nCK

Rev. 1.1 / Jan. 2013 27

DDR3L- 1333 Speed Bins
For specific Notes see “Speed Bin Table Notes” on page 31.

Speed Bin DDR3L-1333

Unit Note
CL - nRCD - nRP 9- 9- 9
Parameter Symbol min max
Internal read 13.5
t AA 20 ns
command to first data (13.125) 5,11
ACT to internal read or 13.5
t RCD — ns
write delay time (13.125) 5,11
13.5
PRE command period t RP — ns
(13.125) 5,11
ACT to ACT or REF 49.5
t RC — ns
command period (49.125) 5,11
ACT to PRE command
t RAS 36 9 * tREFI ns
period
1, 2, 3, 4,
CWL = 5 t CK(AVG) 3.0 3.3 ns
CL = 5 7, 12,13
CWL = 6, 7 t CK(AVG) Reserved ns 4
CWL = 5 t CK(AVG) 2.5 3.3 ns 1, 2, 3, 7
CL = 6 CWL = 6 t CK(AVG) Reserved ns 1, 2, 3, 4, 7
CWL = 7 t CK(AVG) Reserved ns 4
CWL = 5 t CK(AVG) Reserved ns 4
1.875 < 2.5
CL = 7 CWL = 6 t CK(AVG) ns 1, 2, 3, 4, 7
(Optional) 5
CWL = 7 t CK(AVG) Reserved ns 1, 2, 3, 4
CWL = 5 t CK(AVG) Reserved ns 4
CL = 8 CWL = 6 t CK(AVG) 1.875 < 2.5 ns 1, 2, 3, 7
CWL = 7 t CK(AVG) Reserved ns 1, 2, 3, 4
CWL = 5, 6 t CK(AVG) Reserved ns 4
CL = 9
CWL = 7 t CK(AVG) 1.5 < 1.875 ns 1, 2, 3, 4
CWL = 5, 6 t CK(AVG) Reserved ns 4
CL = 10 1.5 < 1.875 ns 1, 2, 3
CWL = 7 t CK(AVG)
(Optional) ns 5
Supported CL Settings 5, 6, 8, (7), 9, (10) nCK
Supported CWL Settings 5, 6, 7 nCK

Rev. 1.1 / Jan. 2013 28

DDR3L- 1600 Speed Bins
For specific Notes see “Speed Bin Table Notes” on page 31.

Speed Bin DDR3L- 1600

Unit Note
CL - nRCD - nRP 11-11- 11
Parameter Symbol min max
Internal read 13.75
t AA 20 ns
command to first data (13.125) 5,11
ACT to internal read or 13.75
t RCD — ns
write delay time (13.125) 5,11
13.75
PRE command period t RP — ns
(13.125) 5,11
ACT to ACT or REF 48.75
t RC — ns
command period (48.125) 5,11
ACT to PRE command
t RAS 35 9 * tREFI ns
period
1, 2, 3, 4,
CWL = 5 t CK(AVG) 3.0 3.3 ns
CL = 5 8, 12,13
CWL = 6, 7 t CK(AVG) Reserved ns 4
CWL = 5 t CK(AVG) 2.5 3.3 ns 1, 2, 3, 8
CL = 6 CWL = 6 t CK(AVG) Reserved ns 1, 2, 3, 4, 8
CWL = 7 t CK(AVG) Reserved ns 4
CWL = 5 t CK(AVG) Reserved ns 4
1.875 < 2.5
CWL = 6 t CK(AVG) ns 1, 2, 3, 4, 8
CL = 7 5
(Optional)
CWL = 7 t CK(AVG) Reserved ns 1, 2, 3, 4, 8
CWL = 8 t CK(AVG) Reserved ns 4
CWL = 5 t CK(AVG) Reserved ns 4
CWL = 6 t CK(AVG) 1.875 < 2.5 ns 1, 2, 3, 8
CL = 8
CWL = 7 t CK(AVG) Reserved ns 1, 2, 3, 4, 8
CWL = 8 t CK(AVG) Reserved ns 1, 2, 3, 4
CWL = 5, 6 t CK(AVG) Reserved ns 4
1.5 < 1.875
CL = 9 CWL = 7 t CK(AVG) ns 1, 2, 3, 4, 8
(Optional) 5
CWL = 8 t CK(AVG) Reserved ns 1, 2, 3, 4
CWL = 5, 6 t CK(AVG) Reserved ns 4
CL = 10 CWL = 7 t CK(AVG) 1.5 < 1.875 ns 1, 2, 3, 8
CWL = 8 t CK(AVG) Reserved ns 1, 2, 3, 4
CWL = 5, 6,7 t CK(AVG) Reserved ns 4
CL = 11
CWL = 8 t CK(AVG) 1.25 < 1.5 ns 1, 2, 3
Supported CL Settings 5, 6, (7), 8, (9), 10, 11 nCK
Supported CWL Settings 5, 6, 7, 8 nCK

Rev. 1.1 / Jan. 2013 29

DDR3L- 1866 Speed Bins
For specific Notes see “Speed Bin Table Notes” on page 31.
Speed Bin DDR3L- 1866
Unit Note
CL - nRCD - nRP 13- 13- 13
Parameter Symbol min max
Internal read command 13.91
t AA 20 ns
to first data (13.125) 5,14
ACT to internal read or 13.91
t RCD — ns
write delay time (13.125) 5,14
13.91
PRE command period t RP — ns
(13.125) 5,14
ACT to PRE command
t RAS 34 9 * tREFI ns
period
ACT to ACT or PRE 47.91
t RC - ns
command period (47.125) 5,14
CWL = 5 t CK(AVG) 3.0 3.3 ns 1, 2, 3, 4, 9
CL = 5
CWL = 6,7,8,9 t CK(AVG) Reserved ns 4
CWL = 5 t CK(AVG) 2.5 3.3 ns 1, 2, 3, 9
CL = 6 CWL = 6 t CK(AVG) Reserved ns 1, 2, 3, 4, 9
CWL = 7,8,9 t CK(AVG) Reserved ns 4
CWL = 5 t CK(AVG) Reserved ns 4
CL = 7 CWL = 6 t CK(AVG) 1.875 < 2.5 ns 1, 2, 3, 4, 9
CWL = 7,8,9 t CK(AVG) Reserved ns 4
CWL = 5 t CK(AVG) Reserved ns 4
CWL = 6 t CK(AVG) 1.875 < 2.5 ns 1, 2, 3, 9
CL = 8
CWL = 7 t CK(AVG) Reserved ns 1, 2, 3, 4, 9
CWL = 8,9 t CK(AVG) Reserved ns 4
CWL = 5, 6 t CK(AVG) Reserved ns 4
CWL = 7 t CK(AVG) 1.5 < 1.875 ns 1, 2, 3, 4, 9
CL = 9
CWL = 8 t CK(AVG) Reserved ns 1, 2, 3, 4, 9
CWL = 9 t CK(AVG) Reserved ns 4
CWL = 5, 6 t CK(AVG) Reserved ns 4
CL = 10 CWL = 7 t CK(AVG) 1.5 < 1.875 ns 1, 2, 3, 9
CWL = 8 t CK(AVG) Reserved ns 1, 2, 3, 4, 9
CWL = 5,6,7 t CK(AVG) Reserved ns 4
CL = 11 CWL = 8 t CK(AVG) 1.25 < 1.5 ns 1, 2, 3, 4, 9
CWL = 9 t CK(AVG) Reserved ns 1, 2, 3, 4
CWL = 5,6,7,8 t CK(AVG) Reserved ns 4
CL = 12
CWL = 9 t CK(AVG) Reserved ns 1,2,3,4
CWL = 5,6,7,8 t CK(AVG) Reserved ns 4
CL = 13
CWL = 9 t CK(AVG) 1.07 < 1.25 ns 1, 2, 3
Supported CL Settings 6, 8, 10, 13, (7), (9), (11) nCK
Supported CWL Settings 5, 6, 7, 8, 9 nCK

Rev. 1.1 / Jan. 2013 30

Speed Bin Table Notes
Absolute Specification (TOPER; VDDQ = VDD = 1.5V + / - 0.075 V);
1. The CL setting and CWL setting result in tCK(AVG).MIN and tCK(AVG).MAX requirements. When making
a selection of tCK(AVG), both need to be fulfilled: Requirements from CL setting as well as requirements
from CWL setting.
2. tCK(AVG).MIN limits: Since CAS Latency is not purely analog - data and strobe output are synchronized
by the DLL - all possible intermediate frequencies may not be guaranteed. An application should use the
next smaller JEDEC standard tCK(AVG) value (3.0, 2.5, 1.875, 1.5, or 1.25 ns) when calculating CL [ nCK]
= tAA [ ns] / tCK(AVG) [ ns] , rounding up to the next ‘Supported CL’, where tCK(AVG) = 3.0 ns should
only be used for CL = 5 calculation.
3. tCK(AVG).MAX limits: Calculate tCK(AVG) = tAA.MAX / CL SELECTED and round the resulting tCK(AVG)
down to the next valid speed bin (i.e. 3.3ns or 2.5ns or 1.875 ns or 1.25 ns). This result is tCK(AVG).MAX
corresponding to CL SELECTED.
4. ‘Reserved’ settings are not allowed. User must program a different value.
5. ‘Optional’ settings allow certain devices in the industry to support this setting, however, it is not a man-
datory feature. Refer to SK Hynix DIMM data sheet and/ or the DIMM SPD information if and how this
setting is supported.
6. Any DDR3L-1066 speed bin also supports functional operation at lower frequencies as shown in the table
which are not subject to Production Tests but verified by Design/ Characterization.
7. Any DDR3L-1333 speed bin also supports functional operation at lower frequencies as shown in the table
which are not subject to Production Tests but verified by Design/ Characterization.
8. Any DDR3L-1600 speed bin also supports functional operation at lower frequencies as shown in the table
which are not subject to Production Tests but verified by Design/ Characterization.
9. Any DDR3L-1866 speed bin also supports functional operation at lower frequencies as shown in the table
which are not subject to Production Tests but verified by Design/ Characterization.
10. Any DDR3L-2133 speed bin also supports functional operation at lower frequencies as shown in the table
which are not subject to Production Tests but verified by Design/ Characterization.
11. SK Hynix DDR3L SDRAM devices supporting optional down binning to CL= 7 and CL= 9, and tAA/ tRCD/
tRP must be 13.125 ns or lower. SPD settings must be programmed to match. For example, DDR3L-
1333H devices supporting down binning to DDR3L-1066F should program 13.125 ns in SPD bytes for
tAAmin (Byte 16), tRCDmin (Byte 18), and tRPmin (Byte 20). DDR3L-1600K devices supporting down
binning to DDR3L-1333H or DDR3L-1600F should program 13.125 ns in SPD bytes for tAAmin (Byte 16),
tRCDmin (Byte 18), and tRPmin (Byte 20). Once tRP (Byte 20) is programmed to 13.125ns, tRCmin
(Byte 21,23) also should be programmed accordingly. For example, 49.125ns (tRASmin + tRPmin = 36
ns + 13.125 ns) for DDR3L-1333H and 48.125ns (tRASmin + tRPmin = 35 ns + 13.125 ns) for DDR3L-
1600K.
12. DDR3L 800 AC timing apply if DRAM operates at lower than 800 MT/ s data rate.
13. For CL5 support, refer to DIMM SPD information. DRAM is required to support CL5. CL5 is not mandatory
in SPD coding.
14. SK Hynix DDR3L SDRAM devices supporting optional down binning to CL= 11, CL= 9 and CL= 7, tAA/
tRCD/ tRPmin must be 13.125ns. SPD setting must be programed to match. For example, DDR3L-1866M
devices supporting down binning to DDR3L-1600K or DDR3L-1333H or 1066F should program 13.125ns
in SPD bytes for tAAmin(byte 16), tRCDmin(byte 18) and tRPmin(byte 20) is programmed to 13.125ns,
tRCmin(byte 21,23) also should be programmed accordingly. For example, 47.125ns (tRASmin + tRPmin
= 34ns + 13.125ns)

Rev. 1.1 / Jan. 2013 31

Package Dimensions
Package Dimension( x8) : 78Ball Fine Pitch Ball Grid Array Outline
A1 CORNER 9.000  0.100
INDEX AREA 1.100  0.100
(2.350)
0.340  0.050
(2.775)

11.100  0.100

3.0 X 5.0 MIN

FLAT AREA

TOP VI EW SI DE VI EW

0.800 X 8 = 6.400
0.800 1.300  0.100
A1 BALL MARK
9 8 7 3 2 1

A
B
C
D
0.800

E
0.800 X 12 = 9.600

F
G
H
J
K
L
M
N
0.750  0.100

78 x 0.450  0.050 1.600 1.600

BOTTOM VI EW

Rev. 1.1 / Jan. 2013 32

Package Dimension( x16) : 96Ball Fine Pitch Ball Grid Array Outline
A1 CORNER
INDEX AREA
(2.250) 1.100  0.100
9.000  0.100
0.340  0.050
(3.250)

13.000  0.100
3.0 X 5.0 MIN
FLAT AREA

TOP VI EW SI DE VI EW
0.800 X 8 = 6.400
0.800 1.300  0.100

9 8 7 3 2 1

A1 BALL MARK
A
B
C
D
0.800

E
0.800 X 15 = 12.000

F
G
H
J
K
L
M
N

P
R
T
0.500  0.100

1.600 1.600
96 x 0.450  0.050
BOTTOM VI EW

Rev. 1.1 / Jan. 2013 33